Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
842 |
1 |
|
|
T1 |
8 |
|
T13 |
11 |
|
T15 |
12 |
| auto[1] |
858 |
1 |
|
|
T1 |
12 |
|
T13 |
9 |
|
T15 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
852 |
1 |
|
|
T1 |
8 |
|
T13 |
11 |
|
T15 |
11 |
| auto[1] |
848 |
1 |
|
|
T1 |
12 |
|
T13 |
9 |
|
T15 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T1 |
12 |
|
T13 |
12 |
|
T15 |
13 |
| auto[1] |
867 |
1 |
|
|
T1 |
8 |
|
T13 |
8 |
|
T15 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
857 |
1 |
|
|
T1 |
11 |
|
T13 |
10 |
|
T15 |
12 |
| auto[1] |
843 |
1 |
|
|
T1 |
9 |
|
T13 |
10 |
|
T15 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T1 |
11 |
|
T13 |
9 |
|
T15 |
9 |
| auto[1] |
834 |
1 |
|
|
T1 |
9 |
|
T13 |
11 |
|
T15 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T1 |
11 |
|
T13 |
11 |
|
T15 |
10 |
| auto[1] |
867 |
1 |
|
|
T1 |
9 |
|
T13 |
9 |
|
T15 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
861 |
1 |
|
|
T1 |
11 |
|
T13 |
7 |
|
T15 |
13 |
| auto[1] |
839 |
1 |
|
|
T1 |
9 |
|
T13 |
13 |
|
T15 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T1 |
11 |
|
T13 |
9 |
|
T15 |
9 |
| auto[1] |
834 |
1 |
|
|
T1 |
9 |
|
T13 |
11 |
|
T15 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
856 |
1 |
|
|
T1 |
12 |
|
T13 |
12 |
|
T15 |
16 |
| auto[1] |
844 |
1 |
|
|
T1 |
8 |
|
T13 |
8 |
|
T15 |
4 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T1 |
5 |
|
T13 |
9 |
|
T15 |
12 |
| auto[1] |
869 |
1 |
|
|
T1 |
15 |
|
T13 |
11 |
|
T15 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T1 |
11 |
|
T13 |
16 |
|
T15 |
14 |
| auto[1] |
842 |
1 |
|
|
T1 |
9 |
|
T13 |
4 |
|
T15 |
6 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T1 |
9 |
|
T13 |
12 |
|
T15 |
11 |
| auto[1] |
845 |
1 |
|
|
T1 |
11 |
|
T13 |
8 |
|
T15 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T1 |
9 |
|
T13 |
8 |
|
T15 |
9 |
| auto[1] |
845 |
1 |
|
|
T1 |
11 |
|
T13 |
12 |
|
T15 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
852 |
1 |
|
|
T1 |
8 |
|
T13 |
11 |
|
T15 |
11 |
| auto[1] |
848 |
1 |
|
|
T1 |
12 |
|
T13 |
9 |
|
T15 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
819 |
1 |
|
|
T1 |
10 |
|
T13 |
10 |
|
T15 |
9 |
| auto[1] |
881 |
1 |
|
|
T1 |
10 |
|
T13 |
10 |
|
T15 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T1 |
13 |
|
T13 |
12 |
|
T15 |
14 |
| auto[1] |
845 |
1 |
|
|
T1 |
7 |
|
T13 |
8 |
|
T15 |
6 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
828 |
1 |
|
|
T1 |
11 |
|
T13 |
6 |
|
T15 |
9 |
| auto[1] |
872 |
1 |
|
|
T1 |
9 |
|
T13 |
14 |
|
T15 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
861 |
1 |
|
|
T1 |
13 |
|
T13 |
6 |
|
T15 |
8 |
| auto[1] |
839 |
1 |
|
|
T1 |
7 |
|
T13 |
14 |
|
T15 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
838 |
1 |
|
|
T1 |
9 |
|
T13 |
12 |
|
T15 |
11 |
| auto[1] |
862 |
1 |
|
|
T1 |
11 |
|
T13 |
8 |
|
T15 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
835 |
1 |
|
|
T1 |
9 |
|
T13 |
10 |
|
T15 |
9 |
| auto[1] |
865 |
1 |
|
|
T1 |
11 |
|
T13 |
10 |
|
T15 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
825 |
1 |
|
|
T1 |
12 |
|
T13 |
9 |
|
T15 |
9 |
| auto[1] |
875 |
1 |
|
|
T1 |
8 |
|
T13 |
11 |
|
T15 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
825 |
1 |
|
|
T1 |
9 |
|
T13 |
10 |
|
T15 |
10 |
| auto[1] |
875 |
1 |
|
|
T1 |
11 |
|
T13 |
10 |
|
T15 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T1 |
11 |
|
T13 |
9 |
|
T15 |
10 |
| auto[1] |
852 |
1 |
|
|
T1 |
9 |
|
T13 |
11 |
|
T15 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T1 |
9 |
|
T13 |
12 |
|
T15 |
11 |
| auto[1] |
845 |
1 |
|
|
T1 |
11 |
|
T13 |
8 |
|
T15 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
390 |
1 |
|
|
T1 |
6 |
|
T13 |
5 |
|
T15 |
7 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T1 |
4 |
|
T13 |
5 |
|
T15 |
2 |
| auto[1] |
auto[0] |
443 |
1 |
|
|
T1 |
6 |
|
T13 |
7 |
|
T15 |
6 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T1 |
4 |
|
T13 |
3 |
|
T15 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
420 |
1 |
|
|
T1 |
7 |
|
T13 |
5 |
|
T15 |
9 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T1 |
6 |
|
T13 |
7 |
|
T15 |
5 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T1 |
4 |
|
T13 |
5 |
|
T15 |
3 |
| auto[1] |
auto[1] |
408 |
1 |
|
|
T1 |
3 |
|
T13 |
3 |
|
T15 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
428 |
1 |
|
|
T1 |
6 |
|
T13 |
3 |
|
T15 |
5 |
| auto[0] |
auto[1] |
400 |
1 |
|
|
T1 |
5 |
|
T13 |
3 |
|
T15 |
4 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T1 |
5 |
|
T13 |
6 |
|
T15 |
4 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T1 |
4 |
|
T13 |
8 |
|
T15 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
428 |
1 |
|
|
T1 |
7 |
|
T13 |
4 |
|
T15 |
5 |
| auto[0] |
auto[1] |
433 |
1 |
|
|
T1 |
6 |
|
T13 |
2 |
|
T15 |
3 |
| auto[1] |
auto[0] |
405 |
1 |
|
|
T1 |
4 |
|
T13 |
7 |
|
T15 |
5 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T1 |
3 |
|
T13 |
7 |
|
T15 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
415 |
1 |
|
|
T1 |
6 |
|
T13 |
4 |
|
T15 |
7 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T1 |
3 |
|
T13 |
8 |
|
T15 |
4 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T1 |
5 |
|
T13 |
3 |
|
T15 |
6 |
| auto[1] |
auto[1] |
416 |
1 |
|
|
T1 |
6 |
|
T13 |
5 |
|
T15 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T1 |
6 |
|
T13 |
4 |
|
T15 |
4 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T1 |
3 |
|
T13 |
6 |
|
T15 |
5 |
| auto[1] |
auto[0] |
450 |
1 |
|
|
T1 |
5 |
|
T13 |
5 |
|
T15 |
5 |
| auto[1] |
auto[1] |
415 |
1 |
|
|
T1 |
6 |
|
T13 |
5 |
|
T15 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
404 |
1 |
|
|
T1 |
4 |
|
T13 |
5 |
|
T15 |
6 |
| auto[0] |
auto[1] |
421 |
1 |
|
|
T1 |
5 |
|
T13 |
5 |
|
T15 |
4 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T1 |
1 |
|
T13 |
4 |
|
T15 |
6 |
| auto[1] |
auto[1] |
448 |
1 |
|
|
T1 |
10 |
|
T13 |
6 |
|
T15 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
429 |
1 |
|
|
T1 |
8 |
|
T13 |
8 |
|
T15 |
7 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T1 |
3 |
|
T13 |
1 |
|
T15 |
3 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T1 |
3 |
|
T13 |
8 |
|
T15 |
7 |
| auto[1] |
auto[1] |
423 |
1 |
|
|
T1 |
6 |
|
T13 |
3 |
|
T15 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T1 |
4 |
|
T13 |
2 |
|
T15 |
5 |
| auto[0] |
auto[1] |
436 |
1 |
|
|
T1 |
5 |
|
T13 |
6 |
|
T15 |
4 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T1 |
4 |
|
T13 |
9 |
|
T15 |
7 |
| auto[1] |
auto[1] |
422 |
1 |
|
|
T1 |
7 |
|
T13 |
3 |
|
T15 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
852 |
1 |
|
|
T1 |
8 |
|
T13 |
11 |
|
T15 |
11 |
| auto[1] |
auto[1] |
848 |
1 |
|
|
T1 |
12 |
|
T13 |
9 |
|
T15 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T1 |
7 |
|
T13 |
5 |
|
T15 |
8 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T1 |
5 |
|
T13 |
4 |
|
T15 |
1 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T1 |
5 |
|
T13 |
7 |
|
T15 |
8 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T1 |
3 |
|
T13 |
4 |
|
T15 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
855 |
1 |
|
|
T1 |
9 |
|
T13 |
12 |
|
T15 |
11 |
| auto[1] |
auto[1] |
845 |
1 |
|
|
T1 |
11 |
|
T13 |
8 |
|
T15 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T1 |
10 |
|
T45 |
9 |
|
T31 |
9 |
| auto[1] |
159 |
1 |
|
|
T1 |
10 |
|
T45 |
11 |
|
T31 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T1 |
8 |
|
T45 |
11 |
|
T31 |
9 |
| auto[1] |
167 |
1 |
|
|
T1 |
12 |
|
T45 |
9 |
|
T31 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T1 |
12 |
|
T45 |
9 |
|
T31 |
8 |
| auto[1] |
175 |
1 |
|
|
T1 |
8 |
|
T45 |
11 |
|
T31 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T1 |
11 |
|
T45 |
10 |
|
T31 |
12 |
| auto[1] |
163 |
1 |
|
|
T1 |
9 |
|
T45 |
10 |
|
T31 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T1 |
9 |
|
T45 |
8 |
|
T31 |
8 |
| auto[1] |
181 |
1 |
|
|
T1 |
11 |
|
T45 |
12 |
|
T31 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T1 |
11 |
|
T45 |
15 |
|
T31 |
10 |
| auto[1] |
169 |
1 |
|
|
T1 |
9 |
|
T45 |
5 |
|
T31 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
160 |
1 |
|
|
T1 |
10 |
|
T45 |
9 |
|
T31 |
7 |
| auto[1] |
180 |
1 |
|
|
T1 |
10 |
|
T45 |
11 |
|
T31 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
176 |
1 |
|
|
T1 |
10 |
|
T45 |
10 |
|
T31 |
9 |
| auto[1] |
164 |
1 |
|
|
T1 |
10 |
|
T45 |
10 |
|
T31 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T1 |
9 |
|
T45 |
9 |
|
T31 |
12 |
| auto[1] |
176 |
1 |
|
|
T1 |
11 |
|
T45 |
11 |
|
T31 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
185 |
1 |
|
|
T1 |
11 |
|
T45 |
10 |
|
T31 |
7 |
| auto[1] |
155 |
1 |
|
|
T1 |
9 |
|
T45 |
10 |
|
T31 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T1 |
9 |
|
T45 |
12 |
|
T31 |
11 |
| auto[1] |
176 |
1 |
|
|
T1 |
11 |
|
T45 |
8 |
|
T31 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
166 |
1 |
|
|
T1 |
6 |
|
T45 |
8 |
|
T31 |
8 |
| auto[1] |
174 |
1 |
|
|
T1 |
14 |
|
T45 |
12 |
|
T31 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T1 |
11 |
|
T45 |
10 |
|
T31 |
12 |
| auto[1] |
161 |
1 |
|
|
T1 |
9 |
|
T45 |
10 |
|
T31 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T1 |
8 |
|
T45 |
11 |
|
T31 |
9 |
| auto[1] |
167 |
1 |
|
|
T1 |
12 |
|
T45 |
9 |
|
T31 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T1 |
11 |
|
T45 |
10 |
|
T31 |
6 |
| auto[1] |
163 |
1 |
|
|
T1 |
9 |
|
T45 |
10 |
|
T31 |
14 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T1 |
10 |
|
T45 |
9 |
|
T31 |
10 |
| auto[1] |
171 |
1 |
|
|
T1 |
10 |
|
T45 |
11 |
|
T31 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
166 |
1 |
|
|
T1 |
11 |
|
T45 |
13 |
|
T31 |
9 |
| auto[1] |
174 |
1 |
|
|
T1 |
9 |
|
T45 |
7 |
|
T31 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T1 |
7 |
|
T45 |
8 |
|
T31 |
7 |
| auto[1] |
166 |
1 |
|
|
T1 |
13 |
|
T45 |
12 |
|
T31 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T1 |
6 |
|
T45 |
10 |
|
T31 |
8 |
| auto[1] |
173 |
1 |
|
|
T1 |
14 |
|
T45 |
10 |
|
T31 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T1 |
12 |
|
T45 |
7 |
|
T31 |
8 |
| auto[1] |
169 |
1 |
|
|
T1 |
8 |
|
T45 |
13 |
|
T31 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T1 |
10 |
|
T45 |
15 |
|
T31 |
10 |
| auto[1] |
158 |
1 |
|
|
T1 |
10 |
|
T45 |
5 |
|
T31 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T1 |
12 |
|
T45 |
8 |
|
T31 |
10 |
| auto[1] |
179 |
1 |
|
|
T1 |
8 |
|
T45 |
12 |
|
T31 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
172 |
1 |
|
|
T1 |
12 |
|
T45 |
10 |
|
T31 |
12 |
| auto[1] |
168 |
1 |
|
|
T1 |
8 |
|
T45 |
10 |
|
T31 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
166 |
1 |
|
|
T1 |
6 |
|
T45 |
8 |
|
T31 |
8 |
| auto[1] |
174 |
1 |
|
|
T1 |
14 |
|
T45 |
12 |
|
T31 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T1 |
6 |
|
T45 |
3 |
|
T31 |
2 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T1 |
5 |
|
T45 |
7 |
|
T31 |
4 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T1 |
6 |
|
T45 |
6 |
|
T31 |
6 |
| auto[1] |
auto[1] |
84 |
1 |
|
|
T1 |
3 |
|
T45 |
4 |
|
T31 |
8 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
88 |
1 |
|
|
T1 |
5 |
|
T45 |
3 |
|
T31 |
6 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T1 |
5 |
|
T45 |
6 |
|
T31 |
4 |
| auto[1] |
auto[0] |
89 |
1 |
|
|
T1 |
6 |
|
T45 |
7 |
|
T31 |
6 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T1 |
4 |
|
T45 |
4 |
|
T31 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T1 |
5 |
|
T45 |
4 |
|
T31 |
2 |
| auto[0] |
auto[1] |
90 |
1 |
|
|
T1 |
6 |
|
T45 |
9 |
|
T31 |
7 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T1 |
4 |
|
T45 |
4 |
|
T31 |
6 |
| auto[1] |
auto[1] |
91 |
1 |
|
|
T1 |
5 |
|
T45 |
3 |
|
T31 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T1 |
4 |
|
T45 |
5 |
|
T31 |
2 |
| auto[0] |
auto[1] |
88 |
1 |
|
|
T1 |
3 |
|
T45 |
3 |
|
T31 |
5 |
| auto[1] |
auto[0] |
85 |
1 |
|
|
T1 |
7 |
|
T45 |
10 |
|
T31 |
8 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T1 |
6 |
|
T45 |
2 |
|
T31 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
87 |
1 |
|
|
T1 |
3 |
|
T45 |
5 |
|
T31 |
2 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T1 |
3 |
|
T45 |
5 |
|
T31 |
6 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T1 |
7 |
|
T45 |
4 |
|
T31 |
5 |
| auto[1] |
auto[1] |
100 |
1 |
|
|
T1 |
7 |
|
T45 |
6 |
|
T31 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
97 |
1 |
|
|
T1 |
6 |
|
T45 |
4 |
|
T31 |
3 |
| auto[0] |
auto[1] |
74 |
1 |
|
|
T1 |
6 |
|
T45 |
3 |
|
T31 |
5 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T1 |
4 |
|
T45 |
6 |
|
T31 |
6 |
| auto[1] |
auto[1] |
90 |
1 |
|
|
T1 |
4 |
|
T45 |
7 |
|
T31 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T1 |
6 |
|
T45 |
2 |
|
T31 |
4 |
| auto[0] |
auto[1] |
78 |
1 |
|
|
T1 |
6 |
|
T45 |
6 |
|
T31 |
6 |
| auto[1] |
auto[0] |
102 |
1 |
|
|
T1 |
5 |
|
T45 |
8 |
|
T31 |
3 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T1 |
3 |
|
T45 |
4 |
|
T31 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
78 |
1 |
|
|
T1 |
5 |
|
T45 |
4 |
|
T31 |
7 |
| auto[0] |
auto[1] |
94 |
1 |
|
|
T1 |
7 |
|
T45 |
6 |
|
T31 |
5 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T1 |
4 |
|
T45 |
8 |
|
T31 |
4 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T1 |
4 |
|
T45 |
2 |
|
T31 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
101 |
1 |
|
|
T1 |
6 |
|
T45 |
4 |
|
T31 |
6 |
| auto[0] |
auto[1] |
78 |
1 |
|
|
T1 |
5 |
|
T45 |
6 |
|
T31 |
6 |
| auto[1] |
auto[0] |
80 |
1 |
|
|
T1 |
4 |
|
T45 |
5 |
|
T31 |
3 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T1 |
5 |
|
T45 |
5 |
|
T31 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
173 |
1 |
|
|
T1 |
8 |
|
T45 |
11 |
|
T31 |
9 |
| auto[1] |
auto[1] |
167 |
1 |
|
|
T1 |
12 |
|
T45 |
9 |
|
T31 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
85 |
1 |
|
|
T1 |
5 |
|
T45 |
7 |
|
T31 |
7 |
| auto[0] |
auto[1] |
97 |
1 |
|
|
T1 |
5 |
|
T45 |
8 |
|
T31 |
3 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T1 |
4 |
|
T45 |
2 |
|
T31 |
5 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T1 |
6 |
|
T45 |
3 |
|
T31 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
166 |
1 |
|
|
T1 |
6 |
|
T45 |
8 |
|
T31 |
8 |
| auto[1] |
auto[1] |
174 |
1 |
|
|
T1 |
14 |
|
T45 |
12 |
|
T31 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
63 |
1 |
|
|
T128 |
12 |
|
T180 |
9 |
|
T181 |
8 |
| auto[1] |
57 |
1 |
|
|
T128 |
8 |
|
T180 |
11 |
|
T181 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T128 |
10 |
|
T180 |
12 |
|
T181 |
8 |
| auto[1] |
64 |
1 |
|
|
T128 |
10 |
|
T180 |
8 |
|
T181 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T128 |
11 |
|
T180 |
12 |
|
T181 |
9 |
| auto[1] |
66 |
1 |
|
|
T128 |
9 |
|
T180 |
8 |
|
T181 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T128 |
10 |
|
T180 |
10 |
|
T181 |
6 |
| auto[1] |
71 |
1 |
|
|
T128 |
10 |
|
T180 |
10 |
|
T181 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
58 |
1 |
|
|
T128 |
9 |
|
T180 |
7 |
|
T181 |
10 |
| auto[1] |
62 |
1 |
|
|
T128 |
11 |
|
T180 |
13 |
|
T181 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
63 |
1 |
|
|
T128 |
12 |
|
T180 |
10 |
|
T181 |
9 |
| auto[1] |
57 |
1 |
|
|
T128 |
8 |
|
T180 |
10 |
|
T181 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T128 |
14 |
|
T180 |
14 |
|
T181 |
13 |
| auto[1] |
52 |
1 |
|
|
T128 |
6 |
|
T180 |
6 |
|
T181 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T128 |
10 |
|
T180 |
7 |
|
T181 |
8 |
| auto[1] |
69 |
1 |
|
|
T128 |
10 |
|
T180 |
13 |
|
T181 |
12 |