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 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT23,T16,T50
110CoveredT288,T289,T294
111CoveredT8,T27,T28

 LINE       6680
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT288,T289,T290
111CoveredT2,T8,T9

 LINE       6682
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT23,T2,T16
110CoveredT280,T285,T288
111CoveredT23,T2,T8

 LINE       6695
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T21
110CoveredT280,T285,T288
111CoveredT4,T5,T21

 LINE       6712
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T6
110CoveredT286,T280,T288
111CoveredT4,T5,T6

 LINE       6721
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T21
110CoveredT280,T288,T293
111CoveredT4,T5,T21

 LINE       6730
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT23,T1,T3
110CoveredT288,T289,T295
111CoveredT1,T3,T8

 LINE       6745
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T1
110CoveredT280,T288,T289
111CoveredT22,T1,T14

 LINE       6747
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT23,T3,T29
110CoveredT280,T288,T295
111CoveredT29,T7,T8

 LINE       6750
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT23,T3,T29
110CoveredT285,T288,T290
111CoveredT29,T7,T8

 LINE       6757
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T288,T289
111CoveredT22,T18,T30

 LINE       6763
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T288,T289
111CoveredT22,T18,T30

 LINE       6769
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT288,T290,T296
111CoveredT22,T18,T30

 LINE       6775
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T292,T288
111CoveredT22,T18,T30

 LINE       6781
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T3
110CoveredT297,T288,T289
111CoveredT22,T18,T30

 LINE       6783
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T16
110CoveredT288,T298,T299
111CoveredT22,T18,T30

 LINE       6785
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T18
110CoveredT300,T288,T289
111CoveredT22,T18,T30

 LINE       6787
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T3
110CoveredT288,T289,T298
111CoveredT22,T18,T30

 LINE       6789
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT291,T288,T295
111CoveredT22,T14,T2

 LINE       6795
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T288,T301
111CoveredT22,T14,T2

 LINE       6801
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT288,T289,T290
111CoveredT22,T14,T2

 LINE       6807
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT288,T289,T294
111CoveredT22,T14,T2

 LINE       6813
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T35,T297
111CoveredT22,T14,T2

 LINE       6815
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT287,T288,T289
111CoveredT22,T14,T2

 LINE       6817
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T288,T289
111CoveredT22,T14,T2

 LINE       6819
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT288,T289,T301
111CoveredT22,T14,T2

 LINE       6821
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT293,T289,T298
111CoveredT22,T14,T2

 LINE       6826
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T288,T289
111CoveredT22,T14,T2

 LINE       6831
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T288,T290
111CoveredT22,T14,T2

 LINE       6836
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT280,T288,T298
111CoveredT22,T14,T2

 LINE       6841
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT22,T23,T14
110CoveredT288,T289,T302
111CoveredT2,T7,T8

 LINE       6850
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT23,T1,T3
110CoveredT288,T289,T295
111CoveredT1,T3,T8

 LINE       7105
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT4,T5,T6
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%