Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.29	96.38	100.00	96.79	98.71	99.52	93.35

Total tests in report: 912

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
52.55	52.55	75.98	75.98	61.07	61.07	62.33	62.33	10.26	10.26	77.52	77.52	63.49	63.49	17.18	17.18	/workspace/coverage/default/49.sysrst_ctrl_stress_all.2090922853
75.91	23.37	88.30	12.32	79.98	18.91	92.92	30.59	49.36	39.10	89.13	11.61	82.08	18.59	49.62	32.44	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1530622863
83.31	7.40	95.02	6.72	88.85	8.87	94.75	1.83	59.62	10.26	94.60	5.47	90.66	8.57	59.71	10.09	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.133300981
86.81	3.50	96.60	1.59	90.87	2.02	94.75	0.00	77.56	17.95	96.30	1.70	91.81	1.16	59.76	0.05	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.3822540014
89.00	2.20	97.70	1.10	91.89	1.01	94.75	0.00	85.90	8.33	97.23	0.92	94.99	3.18	60.58	0.82	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4275756051
90.25	1.25	97.78	0.07	93.05	1.16	95.43	0.68	85.90	0.00	97.34	0.11	94.99	0.00	67.28	6.71	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1738073447
91.31	1.06	98.08	0.30	93.38	0.33	98.06	2.63	88.46	2.56	97.60	0.26	95.28	0.29	68.32	1.04	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1316703019
92.25	0.94	98.19	0.11	93.83	0.46	98.06	0.00	89.10	0.64	97.67	0.07	95.38	0.10	73.50	5.18	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3774480378
93.09	0.84	98.19	0.00	93.86	0.03	98.06	0.00	89.10	0.00	97.67	0.00	95.38	0.00	79.39	5.89	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2363905778
93.61	0.52	98.25	0.06	93.93	0.08	98.06	0.00	89.10	0.00	97.74	0.07	97.01	1.64	81.19	1.80	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.214567772
94.13	0.52	98.43	0.19	94.21	0.28	98.06	0.00	91.03	1.92	97.89	0.15	97.78	0.77	81.52	0.33	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2282531707
94.51	0.38	98.53	0.09	94.26	0.05	98.06	0.00	92.31	1.28	98.08	0.18	97.88	0.10	82.44	0.93	/workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3356701441
94.83	0.32	98.62	0.09	94.34	0.08	98.06	0.00	92.31	0.00	98.08	0.00	97.88	0.00	84.51	2.07	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3186001817
95.09	0.26	98.68	0.06	94.39	0.05	98.06	0.00	92.31	0.00	98.08	0.00	97.88	0.00	86.26	1.74	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3996859259
95.33	0.24	98.75	0.07	94.44	0.05	98.06	0.00	93.59	1.28	98.15	0.07	98.07	0.19	86.26	0.00	/workspace/coverage/default/20.sysrst_ctrl_edge_detect.4284609232
95.57	0.24	98.81	0.06	94.51	0.08	99.43	1.37	93.59	0.00	98.15	0.00	98.07	0.00	86.42	0.16	/workspace/coverage/default/14.sysrst_ctrl_alert_test.1451796073
95.77	0.21	98.84	0.04	94.54	0.03	99.43	0.00	94.23	0.64	98.19	0.04	98.17	0.10	87.02	0.60	/workspace/coverage/default/7.sysrst_ctrl_stress_all.3553047855
95.95	0.17	98.90	0.06	94.87	0.33	99.43	0.00	94.87	0.64	98.26	0.07	98.27	0.10	87.02	0.00	/workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3537695131
96.08	0.14	98.90	0.00	95.83	0.96	99.43	0.00	94.87	0.00	98.26	0.00	98.27	0.00	87.02	0.00	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.270320823
96.21	0.12	99.01	0.11	95.83	0.00	99.43	0.00	95.51	0.64	98.37	0.11	98.27	0.00	87.02	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.189854935
96.33	0.12	99.07	0.06	95.85	0.03	99.43	0.00	95.51	0.00	98.37	0.00	98.27	0.00	87.79	0.76	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1633843614
96.45	0.12	99.10	0.04	95.88	0.03	99.43	0.00	96.15	0.64	98.41	0.04	98.36	0.10	87.79	0.00	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.1126513446
96.57	0.12	99.14	0.04	95.90	0.03	99.43	0.00	96.79	0.64	98.45	0.04	98.46	0.10	87.79	0.00	/workspace/coverage/default/40.sysrst_ctrl_edge_detect.1102658107
96.68	0.11	99.14	0.00	96.01	0.10	99.43	0.00	96.79	0.00	98.45	0.00	99.13	0.67	87.79	0.00	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3516910779
96.78	0.10	99.14	0.00	96.01	0.00	99.43	0.00	96.79	0.00	98.45	0.00	99.13	0.00	88.50	0.71	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3238955032
96.88	0.10	99.14	0.00	96.03	0.03	99.89	0.46	96.79	0.00	98.45	0.00	99.23	0.10	88.60	0.11	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.632238103
96.97	0.09	99.16	0.02	96.03	0.00	99.89	0.00	96.79	0.00	98.48	0.04	99.23	0.00	89.20	0.60	/workspace/coverage/default/32.sysrst_ctrl_combo_detect.2016764871
97.04	0.07	99.18	0.02	96.03	0.00	99.89	0.00	96.79	0.00	98.52	0.04	99.23	0.00	89.64	0.44	/workspace/coverage/default/47.sysrst_ctrl_stress_all.3999434717
97.11	0.07	99.18	0.00	96.03	0.00	99.89	0.00	96.79	0.00	98.52	0.00	99.23	0.00	90.13	0.49	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2530085910
97.17	0.06	99.18	0.00	96.03	0.00	99.89	0.00	96.79	0.00	98.52	0.00	99.23	0.00	90.57	0.44	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3724454242
97.23	0.05	99.18	0.00	96.03	0.00	99.89	0.00	96.79	0.00	98.52	0.00	99.23	0.00	90.95	0.38	/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.448557852
97.27	0.04	99.18	0.00	96.03	0.00	99.89	0.00	96.79	0.00	98.52	0.00	99.23	0.00	91.22	0.27	/workspace/coverage/default/20.sysrst_ctrl_combo_detect.4095223001
97.30	0.04	99.22	0.04	96.18	0.15	99.89	0.00	96.79	0.00	98.60	0.07	99.23	0.00	91.22	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.4060163778
97.34	0.03	99.22	0.00	96.26	0.08	100.00	0.11	96.79	0.00	98.60	0.00	99.23	0.00	91.28	0.05	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2066165102
97.37	0.03	99.22	0.00	96.26	0.00	100.00	0.00	96.79	0.00	98.60	0.00	99.23	0.00	91.49	0.22	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3234024420
97.40	0.03	99.23	0.02	96.26	0.00	100.00	0.00	96.79	0.00	98.60	0.00	99.23	0.00	91.66	0.16	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2553102498
97.42	0.02	99.25	0.02	96.26	0.00	100.00	0.00	96.79	0.00	98.63	0.04	99.23	0.00	91.77	0.11	/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3463729259
97.44	0.02	99.25	0.00	96.26	0.00	100.00	0.00	96.79	0.00	98.63	0.00	99.23	0.00	91.93	0.16	/workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2910830671
97.47	0.02	99.25	0.00	96.26	0.00	100.00	0.00	96.79	0.00	98.63	0.00	99.23	0.00	92.09	0.16	/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2074160666
97.49	0.02	99.25	0.00	96.28	0.03	100.00	0.00	96.79	0.00	98.63	0.00	99.23	0.00	92.20	0.11	/workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.439498122
97.50	0.02	99.25	0.00	96.31	0.03	100.00	0.00	96.79	0.00	98.63	0.00	99.33	0.10	92.20	0.00	/workspace/coverage/default/37.sysrst_ctrl_edge_detect.3167518706
97.52	0.02	99.25	0.00	96.33	0.03	100.00	0.00	96.79	0.00	98.63	0.00	99.42	0.10	92.20	0.00	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1293818098
97.54	0.02	99.25	0.00	96.33	0.00	100.00	0.00	96.79	0.00	98.63	0.00	99.42	0.00	92.31	0.11	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3232029271
97.55	0.02	99.25	0.00	96.33	0.00	100.00	0.00	96.79	0.00	98.63	0.00	99.42	0.00	92.42	0.11	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3784406287
97.57	0.02	99.25	0.00	96.33	0.00	100.00	0.00	96.79	0.00	98.63	0.00	99.42	0.00	92.53	0.11	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.2305504798
97.58	0.01	99.25	0.00	96.33	0.00	100.00	0.00	96.79	0.00	98.63	0.00	99.52	0.10	92.53	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2788857036
97.59	0.01	99.25	0.00	96.36	0.03	100.00	0.00	96.79	0.00	98.63	0.00	99.52	0.00	92.58	0.05	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3280551503
97.60	0.01	99.27	0.02	96.36	0.00	100.00	0.00	96.79	0.00	98.67	0.04	99.52	0.00	92.58	0.00	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.184477291
97.61	0.01	99.29	0.02	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.04	99.52	0.00	92.58	0.00	/workspace/coverage/default/31.sysrst_ctrl_edge_detect.213508227
97.62	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	92.64	0.05	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.486735257
97.62	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	92.69	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2915182724
97.63	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	92.75	0.05	/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1619115557
97.64	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	92.80	0.05	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1263537213
97.65	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	92.86	0.05	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.885425913
97.65	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	92.91	0.05	/workspace/coverage/default/16.sysrst_ctrl_stress_all.1357879425
97.66	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	92.97	0.05	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2880062191
97.67	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	93.02	0.05	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2687951733
97.68	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	93.08	0.05	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2761058528
97.69	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	93.13	0.05	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.402362077
97.69	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	93.18	0.05	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2757081084
97.70	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	93.24	0.05	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2580182876
97.71	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	93.29	0.05	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.474791589
97.72	0.01	99.29	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.52	0.00	93.35	0.05	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.196820690

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2312823320
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4133737320
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.151620870
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3446450742
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3950799617
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3552564135
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4023310628
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.731439
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.667223430
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1280673395
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1610695402
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3487756823
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.231343118
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2423514602
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2065748487
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1291136047
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1976335605
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2838809205
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.355568766
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3839398662
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3275299928
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2740080633
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1661435008
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2575139936
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1542971676
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2634695115
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3363117235
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1961796975
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1716666454
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1466359089
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.387717280
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.492790199
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.84578503
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.976850828
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2622871241
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.816379511
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2471847272
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2091919108
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3467318529
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2018443777
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1728350781
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3243026432
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3701400899
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3013739589
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.611868519
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1334757436
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.973930200
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4148832416
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1801826614
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2669535017
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2001567067
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.538562185
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.999432602
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1637657454
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1772349699
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1654235383
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.883607792
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.327438619
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1982790543
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.61066296
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.4212957291
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/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4215147579
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.1700162946
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4168251252
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1830578547
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3876182402
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2231030739
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.926772274
/workspace/coverage/default/40.sysrst_ctrl_smoke.3472334360
/workspace/coverage/default/40.sysrst_ctrl_stress_all.603792865
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.4223952068
/workspace/coverage/default/41.sysrst_ctrl_alert_test.1941366288
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3610619373
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.3029125955
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2358383807
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1867375418
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.1575299365
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2568322887
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1932571867
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1224633994
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.4263870403
/workspace/coverage/default/41.sysrst_ctrl_smoke.3227440073
/workspace/coverage/default/41.sysrst_ctrl_stress_all.1487034212
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.857843898
/workspace/coverage/default/42.sysrst_ctrl_alert_test.2358554289
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2761856630
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.918698159
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.182635854
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.183957527
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3803558336
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3003659584
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3574892153
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3740748654
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2512237308
/workspace/coverage/default/42.sysrst_ctrl_smoke.1730363408
/workspace/coverage/default/42.sysrst_ctrl_stress_all.2426877761
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2469058164
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2905681687
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2719558451
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3042210394
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3339937495
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2408588748
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2557406127
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.462745458
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3232102690
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1770531210
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3862258452
/workspace/coverage/default/43.sysrst_ctrl_smoke.811592577
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1001027510
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3792001700
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2495091058
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3327310432
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.991342426
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.688296064
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4244225387
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.661561061
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4238011153
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.658588976
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3167715720
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3510000285
/workspace/coverage/default/44.sysrst_ctrl_smoke.3744187361
/workspace/coverage/default/44.sysrst_ctrl_stress_all.531449897
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1183611522
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.397836336
/workspace/coverage/default/45.sysrst_ctrl_alert_test.1371024691
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.121692497
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.400053813
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2181440578
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.4106997908
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.985273895
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.572465195
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2002680545
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.4101307760
/workspace/coverage/default/45.sysrst_ctrl_smoke.1185976831
/workspace/coverage/default/45.sysrst_ctrl_stress_all.711218935
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1615828374
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1952915800
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1131373196
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2755063598
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.253569146
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1275205425
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3212695870
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.278170244
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2175187480
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3947794154
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3959358292
/workspace/coverage/default/46.sysrst_ctrl_smoke.885647301
/workspace/coverage/default/46.sysrst_ctrl_stress_all.975692624
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3505186749
/workspace/coverage/default/47.sysrst_ctrl_alert_test.4213074857
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3403849750
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2562276820
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2874651468
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.980777305
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2541927517
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.978729495
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1609595623
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1519326895
/workspace/coverage/default/47.sysrst_ctrl_smoke.2687052463
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2493483614
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.17048883
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2140187479
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.4120671401
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.1342828113
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1097416984
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1553041345
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1436266319
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3932892559
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3046755125
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.920548134
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1340899548
/workspace/coverage/default/48.sysrst_ctrl_smoke.1490750389
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2486176771
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1761067522
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1088356993
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3924300496
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1276370809
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3390842065
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2120756379
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3469720288
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3427173550
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3814942973
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3424282885
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.2556866983
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.90257498
/workspace/coverage/default/49.sysrst_ctrl_smoke.2556207362
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.89183356
/workspace/coverage/default/5.sysrst_ctrl_alert_test.3064496762
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1957134127
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.229838232
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.872235127
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3076960416
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2751458125
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3536058480
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.982731106
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1688975662
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3912720298
/workspace/coverage/default/5.sysrst_ctrl_smoke.3296621292
/workspace/coverage/default/5.sysrst_ctrl_stress_all.578826026
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3488309911
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1671052199
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2736490443
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2922857069
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2353792143
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3879351502
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4240232749
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.4012765802
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3418737032
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1086577483
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.929818997
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1684804096
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2664878666
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.515517902
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.102695188
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2671773402
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3871340537
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2356204585
/workspace/coverage/default/6.sysrst_ctrl_smoke.1464521427
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1168803780
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1833746465
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2002653012
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3696378351
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.625054477
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.568995874
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3369532877
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1237130594
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1000989767
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.732387451
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2062697363
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3728104588
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.808725537
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1461930336
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1693209507
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2321385628
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1970717548
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3284622473
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3047115899
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1297167522
/workspace/coverage/default/7.sysrst_ctrl_smoke.1533074518
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1638442003
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.4036452842
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2354723737
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1842300913
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.125705442
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4145832665
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3112471960
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3216493868
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.4263648567
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2535869383
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1602607719
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3507207688
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3247007205
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4250948041
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1225137716
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.4062842390
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2635154294
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3389663787
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1353285583
/workspace/coverage/default/8.sysrst_ctrl_smoke.2860531729
/workspace/coverage/default/8.sysrst_ctrl_stress_all.800046480
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1569585181
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3136293749
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.4081000172
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3489899046
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2240461387
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2362334872
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2996312116
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2959661581
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.689395563
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.131870062
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2606071292
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1092483169
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.463472971
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2112392356
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.530231477
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1787502137
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.4214365031
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.121305497
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2036158359
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2780167983
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2719118926
/workspace/coverage/default/9.sysrst_ctrl_smoke.601039755
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2700120842
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2995774813
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3432023765
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2706417082
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3410218217
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2543656187
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1462255528
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3694469774
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3796294337
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3697683969
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3754536136
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2102714109

Total test records in report: 912

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2322398227	Apr 18 02:22:41 PM PDT 24	Apr 18 02:22:45 PM PDT 24	2520451164 ps
T5	/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3807445228	Apr 18 02:20:54 PM PDT 24	Apr 18 02:20:57 PM PDT 24	2620891497 ps
T6	/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1787502137	Apr 18 02:20:36 PM PDT 24	Apr 18 02:20:39 PM PDT 24	2453340803 ps
T21	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2066165102	Apr 18 02:21:19 PM PDT 24	Apr 18 02:21:21 PM PDT 24	2521252123 ps
T22	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.4036452842	Apr 18 02:23:29 PM PDT 24	Apr 18 02:24:55 PM PDT 24	33143423788 ps
T23	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1157979178	Apr 18 02:21:01 PM PDT 24	Apr 18 02:21:04 PM PDT 24	2468798834 ps
T1	/workspace/coverage/default/35.sysrst_ctrl_edge_detect.250688057	Apr 18 02:22:30 PM PDT 24	Apr 18 02:22:39 PM PDT 24	3176956603 ps
T14	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.2584494131	Apr 18 02:22:22 PM PDT 24	Apr 18 02:25:12 PM PDT 24	64795552766 ps
T2	/workspace/coverage/default/49.sysrst_ctrl_stress_all.2090922853	Apr 18 02:23:23 PM PDT 24	Apr 18 02:26:51 PM PDT 24	81580020605 ps
T3	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.2013947031	Apr 18 02:19:56 PM PDT 24	Apr 18 02:19:59 PM PDT 24	3469623478 ps
T15	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.4277961029	Apr 18 02:21:30 PM PDT 24	Apr 18 02:21:41 PM PDT 24	48647315400 ps
T16	/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1719314371	Apr 18 02:22:12 PM PDT 24	Apr 18 02:22:21 PM PDT 24	2610250842 ps
T17	/workspace/coverage/default/17.sysrst_ctrl_alert_test.4117553438	Apr 18 02:21:10 PM PDT 24	Apr 18 02:21:12 PM PDT 24	2042338108 ps
T18	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1316703019	Apr 18 02:23:23 PM PDT 24	Apr 18 02:24:34 PM PDT 24	25829321513 ps
T19	/workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2728981953	Apr 18 02:20:40 PM PDT 24	Apr 18 02:20:43 PM PDT 24	2634394962 ps
T20	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1688975662	Apr 18 02:20:12 PM PDT 24	Apr 18 02:20:15 PM PDT 24	2078547800 ps
T29	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1263537213	Apr 18 02:20:43 PM PDT 24	Apr 18 02:22:25 PM PDT 24	171855435445 ps
T59	/workspace/coverage/default/22.sysrst_ctrl_pin_override_test.3932564155	Apr 18 02:21:38 PM PDT 24	Apr 18 02:21:41 PM PDT 24	2525242937 ps
T60	/workspace/coverage/default/14.sysrst_ctrl_smoke.1185622204	Apr 18 02:20:59 PM PDT 24	Apr 18 02:21:00 PM PDT 24	2162456447 ps
T30	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.73872328	Apr 18 02:21:10 PM PDT 24	Apr 18 02:21:17 PM PDT 24	28503412644 ps
T50	/workspace/coverage/default/18.sysrst_ctrl_combo_detect.1307628328	Apr 18 02:21:18 PM PDT 24	Apr 18 02:23:22 PM PDT 24	44966563835 ps
T61	/workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1822228859	Apr 18 02:21:49 PM PDT 24	Apr 18 02:21:52 PM PDT 24	4231011108 ps
T7	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1943797712	Apr 18 02:21:50 PM PDT 24	Apr 18 02:23:09 PM PDT 24	31616228516 ps
T8	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1530622863	Apr 18 02:21:55 PM PDT 24	Apr 18 02:24:55 PM PDT 24	130203307397 ps
T62	/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.685991488	Apr 18 02:21:22 PM PDT 24	Apr 18 02:21:26 PM PDT 24	2052678918 ps
T9	/workspace/coverage/default/5.sysrst_ctrl_combo_detect.229838232	Apr 18 02:20:20 PM PDT 24	Apr 18 02:20:52 PM PDT 24	45136734326 ps
T10	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3186001817	Apr 18 02:20:29 PM PDT 24	Apr 18 02:21:52 PM PDT 24	68336771191 ps
T69	/workspace/coverage/default/30.sysrst_ctrl_smoke.4003375982	Apr 18 02:22:09 PM PDT 24	Apr 18 02:22:11 PM PDT 24	2133959978 ps
T11	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.139505400	Apr 18 02:21:10 PM PDT 24	Apr 18 02:21:14 PM PDT 24	3364524800 ps
T70	/workspace/coverage/default/17.sysrst_ctrl_smoke.1719107110	Apr 18 02:21:10 PM PDT 24	Apr 18 02:21:12 PM PDT 24	2130004829 ps
T71	/workspace/coverage/default/43.sysrst_ctrl_smoke.811592577	Apr 18 02:22:57 PM PDT 24	Apr 18 02:23:03 PM PDT 24	2108145552 ps
T72	/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3834381118	Apr 18 02:19:50 PM PDT 24	Apr 18 02:19:53 PM PDT 24	2255233514 ps
T73	/workspace/coverage/default/16.sysrst_ctrl_pin_override_test.168218162	Apr 18 02:21:06 PM PDT 24	Apr 18 02:21:08 PM PDT 24	2536572162 ps
T74	/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1574301550	Apr 18 02:21:21 PM PDT 24	Apr 18 02:21:24 PM PDT 24	2485818325 ps
T12	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.3908274245	Apr 18 02:19:55 PM PDT 24	Apr 18 02:24:54 PM PDT 24	119616323981 ps
T36	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2251321406	Apr 18 02:21:01 PM PDT 24	Apr 18 02:21:03 PM PDT 24	3159762066 ps
T13	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3238955032	Apr 18 02:23:13 PM PDT 24	Apr 18 02:24:54 PM PDT 24	78201314499 ps
T157	/workspace/coverage/default/35.sysrst_ctrl_alert_test.4082110496	Apr 18 02:22:30 PM PDT 24	Apr 18 02:22:32 PM PDT 24	2028837108 ps
T38	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.133300981	Apr 18 02:19:55 PM PDT 24	Apr 18 02:24:25 PM PDT 24	111277520856 ps
T51	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.131870062	Apr 18 02:23:33 PM PDT 24	Apr 18 02:23:49 PM PDT 24	24362034417 ps
T37	/workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.583385703	Apr 18 02:22:12 PM PDT 24	Apr 18 02:22:14 PM PDT 24	12461421641 ps
T324	/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2781001911	Apr 18 02:22:00 PM PDT 24	Apr 18 02:22:04 PM PDT 24	2514189635 ps
T52	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.463472971	Apr 18 02:20:33 PM PDT 24	Apr 18 02:20:43 PM PDT 24	3314938225 ps
T63	/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2562276820	Apr 18 02:23:12 PM PDT 24	Apr 18 02:24:48 PM PDT 24	144197876353 ps
T64	/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2112392356	Apr 18 02:20:48 PM PDT 24	Apr 18 02:23:50 PM PDT 24	136942915284 ps
T65	/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1620614638	Apr 18 02:19:58 PM PDT 24	Apr 18 02:20:04 PM PDT 24	2784575025 ps
T397	/workspace/coverage/default/27.sysrst_ctrl_smoke.304934001	Apr 18 02:21:56 PM PDT 24	Apr 18 02:21:58 PM PDT 24	2181894042 ps
T53	/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.448557852	Apr 18 02:21:15 PM PDT 24	Apr 18 02:21:18 PM PDT 24	3393887934 ps
T66	/workspace/coverage/default/26.sysrst_ctrl_stress_all.3361824681	Apr 18 02:21:54 PM PDT 24	Apr 18 02:24:16 PM PDT 24	1326050177976 ps
T54	/workspace/coverage/default/31.sysrst_ctrl_stress_all.1130160069	Apr 18 02:22:19 PM PDT 24	Apr 18 02:22:29 PM PDT 24	63380286653 ps
T75	/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.3422445722	Apr 18 02:22:15 PM PDT 24	Apr 18 02:22:22 PM PDT 24	2469365788 ps
T55	/workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2346736610	Apr 18 02:21:29 PM PDT 24	Apr 18 02:35:57 PM PDT 24	328902116118 ps
T315	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.2305504798	Apr 18 02:21:27 PM PDT 24	Apr 18 02:21:30 PM PDT 24	2539026736 ps
T316	/workspace/coverage/default/22.sysrst_ctrl_smoke.4109351986	Apr 18 02:21:37 PM PDT 24	Apr 18 02:21:44 PM PDT 24	2110912111 ps
T27	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1569585181	Apr 18 02:20:32 PM PDT 24	Apr 18 02:21:21 PM PDT 24	26824055265 ps
T56	/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1014079788	Apr 18 02:22:13 PM PDT 24	Apr 18 02:22:22 PM PDT 24	3437707068 ps
T46	/workspace/coverage/default/24.sysrst_ctrl_stress_all.2646445711	Apr 18 02:21:47 PM PDT 24	Apr 18 02:22:19 PM PDT 24	12060797541 ps
T203	/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3331357720	Apr 18 02:22:10 PM PDT 24	Apr 18 02:22:13 PM PDT 24	2077900779 ps
T57	/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.4120671401	Apr 18 02:23:16 PM PDT 24	Apr 18 02:23:26 PM PDT 24	3586729598 ps
T28	/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.4223952068	Apr 18 02:22:56 PM PDT 24	Apr 18 02:23:04 PM PDT 24	3963565601 ps
T42	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.214567772	Apr 18 02:20:28 PM PDT 24	Apr 18 02:22:22 PM PDT 24	52364187066 ps
T122	/workspace/coverage/default/34.sysrst_ctrl_pin_override_test.116469884	Apr 18 02:22:26 PM PDT 24	Apr 18 02:22:34 PM PDT 24	2512137853 ps
T123	/workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4278029489	Apr 18 02:21:57 PM PDT 24	Apr 18 02:22:06 PM PDT 24	3076605819 ps
T49	/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2922857069	Apr 18 02:23:31 PM PDT 24	Apr 18 02:25:44 PM PDT 24	50836182181 ps
T58	/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.305118078	Apr 18 02:22:22 PM PDT 24	Apr 18 02:46:52 PM PDT 24	568418098423 ps
T115	/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3866782112	Apr 18 02:20:06 PM PDT 24	Apr 18 02:21:03 PM PDT 24	21993632761 ps
T124	/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2217369194	Apr 18 02:19:50 PM PDT 24	Apr 18 02:19:56 PM PDT 24	4357249090 ps
T125	/workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1380797089	Apr 18 02:22:36 PM PDT 24	Apr 18 02:22:42 PM PDT 24	3633334803 ps
T76	/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3424282885	Apr 18 02:23:17 PM PDT 24	Apr 18 02:23:20 PM PDT 24	2494146362 ps
T318	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3912720298	Apr 18 02:20:20 PM PDT 24	Apr 18 02:20:21 PM PDT 24	2808509343 ps
T320	/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.4250204052	Apr 18 02:22:21 PM PDT 24	Apr 18 02:22:24 PM PDT 24	2537697770 ps
T39	/workspace/coverage/default/3.sysrst_ctrl_stress_all.3254652583	Apr 18 02:20:09 PM PDT 24	Apr 18 02:21:25 PM PDT 24	64344224268 ps
T206	/workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.816270510	Apr 18 02:21:40 PM PDT 24	Apr 18 02:21:43 PM PDT 24	3220780801 ps
T77	/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2175187480	Apr 18 02:23:11 PM PDT 24	Apr 18 02:23:16 PM PDT 24	2470918746 ps
T207	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2455465456	Apr 18 02:22:26 PM PDT 24	Apr 18 02:22:29 PM PDT 24	2629194965 ps
T208	/workspace/coverage/default/48.sysrst_ctrl_alert_test.2140187479	Apr 18 02:23:17 PM PDT 24	Apr 18 02:23:23 PM PDT 24	2008689035 ps
T209	/workspace/coverage/default/37.sysrst_ctrl_alert_test.579876455	Apr 18 02:22:36 PM PDT 24	Apr 18 02:22:40 PM PDT 24	2015481275 ps
T210	/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3599793289	Apr 18 02:20:57 PM PDT 24	Apr 18 02:21:01 PM PDT 24	2638824589 ps
T80	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2955805946	Apr 18 02:21:53 PM PDT 24	Apr 18 02:24:32 PM PDT 24	60834985561 ps
T211	/workspace/coverage/default/23.sysrst_ctrl_smoke.4075046188	Apr 18 02:21:38 PM PDT 24	Apr 18 02:21:43 PM PDT 24	2122491590 ps
T78	/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3876182402	Apr 18 02:22:46 PM PDT 24	Apr 18 02:22:49 PM PDT 24	2469899916 ps
T398	/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2999926812	Apr 18 02:22:41 PM PDT 24	Apr 18 02:22:43 PM PDT 24	2547026222 ps
T40	/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2874651468	Apr 18 02:23:19 PM PDT 24	Apr 18 02:26:36 PM PDT 24	75297469635 ps
T81	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1097416984	Apr 18 02:23:17 PM PDT 24	Apr 18 02:24:59 PM PDT 24	75686199908 ps
T104	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3999518724	Apr 18 02:21:17 PM PDT 24	Apr 18 02:21:36 PM PDT 24	25612247933 ps
T321	/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.3643825075	Apr 18 02:20:55 PM PDT 24	Apr 18 02:21:02 PM PDT 24	2509530803 ps
T261	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4008004287	Apr 18 02:20:01 PM PDT 24	Apr 18 02:20:06 PM PDT 24	2548388883 ps
T399	/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2603277753	Apr 18 02:20:14 PM PDT 24	Apr 18 02:20:18 PM PDT 24	3977506260 ps
T105	/workspace/coverage/default/3.sysrst_ctrl_combo_detect.3998173415	Apr 18 02:20:02 PM PDT 24	Apr 18 02:20:38 PM PDT 24	28442998271 ps
T400	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1926272476	Apr 18 02:21:28 PM PDT 24	Apr 18 02:21:31 PM PDT 24	3026555935 ps
T99	/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3932165940	Apr 18 02:22:26 PM PDT 24	Apr 18 02:30:35 PM PDT 24	183345681333 ps
T67	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.852136747	Apr 18 02:21:07 PM PDT 24	Apr 18 02:21:10 PM PDT 24	4059374018 ps
T68	/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2905681687	Apr 18 02:22:55 PM PDT 24	Apr 18 02:23:00 PM PDT 24	3195065419 ps
T146	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3167715720	Apr 18 02:23:02 PM PDT 24	Apr 18 02:23:05 PM PDT 24	2102368257 ps
T147	/workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3870808871	Apr 18 02:22:23 PM PDT 24	Apr 18 02:22:31 PM PDT 24	2608929512 ps
T148	/workspace/coverage/default/14.sysrst_ctrl_alert_test.1451796073	Apr 18 02:21:00 PM PDT 24	Apr 18 02:21:07 PM PDT 24	2010197551 ps
T149	/workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3775193628	Apr 18 02:21:31 PM PDT 24	Apr 18 02:21:39 PM PDT 24	2611118316 ps
T150	/workspace/coverage/default/44.sysrst_ctrl_alert_test.2495091058	Apr 18 02:23:07 PM PDT 24	Apr 18 02:23:11 PM PDT 24	2019816817 ps
T41	/workspace/coverage/default/39.sysrst_ctrl_combo_detect.428524509	Apr 18 02:22:46 PM PDT 24	Apr 18 02:30:35 PM PDT 24	167051622707 ps
T45	/workspace/coverage/default/40.sysrst_ctrl_edge_detect.1102658107	Apr 18 02:22:52 PM PDT 24	Apr 18 02:22:54 PM PDT 24	4002242244 ps
T100	/workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.533508164	Apr 18 02:19:57 PM PDT 24	Apr 18 02:20:07 PM PDT 24	2965201390 ps
T151	/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3947794154	Apr 18 02:23:10 PM PDT 24	Apr 18 02:23:17 PM PDT 24	2166353791 ps
T106	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1633843614	Apr 18 02:23:26 PM PDT 24	Apr 18 02:28:07 PM PDT 24	116945010328 ps
T247	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3507207688	Apr 18 02:20:28 PM PDT 24	Apr 18 02:23:16 PM PDT 24	123565399932 ps
T248	/workspace/coverage/default/41.sysrst_ctrl_smoke.3227440073	Apr 18 02:22:56 PM PDT 24	Apr 18 02:23:02 PM PDT 24	2110127730 ps
T107	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2757081084	Apr 18 02:23:02 PM PDT 24	Apr 18 02:23:43 PM PDT 24	55547189574 ps
T249	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.687002499	Apr 18 02:22:17 PM PDT 24	Apr 18 02:22:23 PM PDT 24	2117498315 ps
T47	/workspace/coverage/default/21.sysrst_ctrl_edge_detect.469247263	Apr 18 02:21:30 PM PDT 24	Apr 18 02:21:36 PM PDT 24	4700107528 ps
T44	/workspace/coverage/default/45.sysrst_ctrl_edge_detect.4106997908	Apr 18 02:23:05 PM PDT 24	Apr 18 02:23:12 PM PDT 24	4523304299 ps
T216	/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1297167522	Apr 18 02:20:23 PM PDT 24	Apr 18 02:20:26 PM PDT 24	2529234893 ps
T79	/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.28832740	Apr 18 02:22:12 PM PDT 24	Apr 18 02:22:20 PM PDT 24	2448328220 ps
T217	/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3814942973	Apr 18 02:23:24 PM PDT 24	Apr 18 02:23:32 PM PDT 24	2610301941 ps
T218	/workspace/coverage/default/37.sysrst_ctrl_stress_all.422482993	Apr 18 02:22:39 PM PDT 24	Apr 18 02:22:45 PM PDT 24	10362577592 ps
T82	/workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3537695131	Apr 18 02:22:36 PM PDT 24	Apr 18 02:22:42 PM PDT 24	6060694436 ps
T219	/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3221009628	Apr 18 02:22:24 PM PDT 24	Apr 18 02:22:32 PM PDT 24	2467554048 ps
T98	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3879351502	Apr 18 02:23:22 PM PDT 24	Apr 18 02:26:33 PM PDT 24	73332936779 ps
T220	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2887718814	Apr 18 02:21:21 PM PDT 24	Apr 18 02:21:26 PM PDT 24	2617838129 ps
T221	/workspace/coverage/default/45.sysrst_ctrl_smoke.1185976831	Apr 18 02:23:11 PM PDT 24	Apr 18 02:23:18 PM PDT 24	2108053634 ps
T101	/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3610619373	Apr 18 02:22:56 PM PDT 24	Apr 18 02:23:07 PM PDT 24	3753977381 ps
T262	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1540947963	Apr 18 02:20:17 PM PDT 24	Apr 18 02:21:39 PM PDT 24	62595278856 ps
T102	/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3403849750	Apr 18 02:23:14 PM PDT 24	Apr 18 02:23:17 PM PDT 24	3159755686 ps
T401	/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2664878666	Apr 18 02:20:19 PM PDT 24	Apr 18 02:20:31 PM PDT 24	4772744527 ps
T108	/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4240232749	Apr 18 02:23:24 PM PDT 24	Apr 18 02:24:00 PM PDT 24	26840972755 ps
T103	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3830117324	Apr 18 02:21:35 PM PDT 24	Apr 18 02:21:38 PM PDT 24	3018657090 ps
T402	/workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2229843479	Apr 18 02:21:53 PM PDT 24	Apr 18 02:21:57 PM PDT 24	2543485531 ps
T403	/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2181440578	Apr 18 02:23:11 PM PDT 24	Apr 18 02:23:13 PM PDT 24	2701724785 ps
T191	/workspace/coverage/default/29.sysrst_ctrl_edge_detect.3103820236	Apr 18 02:22:10 PM PDT 24	Apr 18 02:22:20 PM PDT 24	3106360706 ps
T404	/workspace/coverage/default/43.sysrst_ctrl_alert_test.2719558451	Apr 18 02:23:04 PM PDT 24	Apr 18 02:23:07 PM PDT 24	2019922626 ps
T48	/workspace/coverage/default/42.sysrst_ctrl_stress_all.2426877761	Apr 18 02:22:55 PM PDT 24	Apr 18 02:23:29 PM PDT 24	15566596603 ps
T405	/workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.935727896	Apr 18 02:21:18 PM PDT 24	Apr 18 02:21:22 PM PDT 24	2684382639 ps
T406	/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.920548134	Apr 18 02:23:18 PM PDT 24	Apr 18 02:23:20 PM PDT 24	2106638375 ps
T407	/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1693209507	Apr 18 02:20:29 PM PDT 24	Apr 18 02:20:37 PM PDT 24	3379264239 ps
T408	/workspace/coverage/default/40.sysrst_ctrl_alert_test.1137943912	Apr 18 02:22:51 PM PDT 24	Apr 18 02:22:56 PM PDT 24	2013878004 ps
T263	/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3247007205	Apr 18 02:20:30 PM PDT 24	Apr 18 02:22:19 PM PDT 24	165080222804 ps
T409	/workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.567449472	Apr 18 02:19:50 PM PDT 24	Apr 18 02:19:52 PM PDT 24	2475058881 ps
T83	/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.397836336	Apr 18 02:23:03 PM PDT 24	Apr 18 02:23:11 PM PDT 24	12829372478 ps
T109	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3774480378	Apr 18 02:21:26 PM PDT 24	Apr 18 02:24:10 PM PDT 24	250149376142 ps
T84	/workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.1343983915	Apr 18 02:22:30 PM PDT 24	Apr 18 02:23:05 PM PDT 24	796918160742 ps
T410	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4244225387	Apr 18 02:23:03 PM PDT 24	Apr 18 02:23:55 PM PDT 24	79224491617 ps
T116	/workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3532586755	Apr 18 02:21:13 PM PDT 24	Apr 18 02:21:23 PM PDT 24	3586668993 ps
T411	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.102695188	Apr 18 02:20:18 PM PDT 24	Apr 18 02:20:21 PM PDT 24	2627528079 ps
T412	/workspace/coverage/default/34.sysrst_ctrl_alert_test.1814975409	Apr 18 02:22:42 PM PDT 24	Apr 18 02:22:44 PM PDT 24	2055820478 ps
T117	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3692940737	Apr 18 02:22:21 PM PDT 24	Apr 18 02:23:43 PM PDT 24	68483245138 ps
T413	/workspace/coverage/default/32.sysrst_ctrl_alert_test.135001001	Apr 18 02:22:21 PM PDT 24	Apr 18 02:22:24 PM PDT 24	2017280274 ps
T110	/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2606071292	Apr 18 02:23:33 PM PDT 24	Apr 18 02:24:52 PM PDT 24	27578277669 ps
T414	/workspace/coverage/default/2.sysrst_ctrl_smoke.2166146365	Apr 18 02:19:59 PM PDT 24	Apr 18 02:20:06 PM PDT 24	2111927657 ps
T415	/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.121305497	Apr 18 02:20:33 PM PDT 24	Apr 18 02:20:40 PM PDT 24	2609931085 ps
T322	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3474176998	Apr 18 02:21:56 PM PDT 24	Apr 18 02:21:59 PM PDT 24	2532709494 ps
T192	/workspace/coverage/default/13.sysrst_ctrl_stress_all.800871437	Apr 18 02:20:57 PM PDT 24	Apr 18 02:21:05 PM PDT 24	10632799772 ps
T416	/workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1992071442	Apr 18 02:20:47 PM PDT 24	Apr 18 02:20:50 PM PDT 24	3284091870 ps
T176	/workspace/coverage/default/39.sysrst_ctrl_edge_detect.4146024611	Apr 18 02:22:44 PM PDT 24	Apr 18 02:22:46 PM PDT 24	3684946591 ps
T417	/workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3091488318	Apr 18 02:21:16 PM PDT 24	Apr 18 02:21:18 PM PDT 24	2223169911 ps
T418	/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3327310432	Apr 18 02:23:06 PM PDT 24	Apr 18 02:23:11 PM PDT 24	3050197283 ps
T276	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2553102498	Apr 18 02:22:37 PM PDT 24	Apr 18 02:24:42 PM PDT 24	51094003663 ps
T419	/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3410169210	Apr 18 02:22:00 PM PDT 24	Apr 18 02:22:04 PM PDT 24	3459976271 ps
T313	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2469058164	Apr 18 02:23:00 PM PDT 24	Apr 18 02:23:26 PM PDT 24	10561623126 ps
T420	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.913970498	Apr 18 02:21:00 PM PDT 24	Apr 18 02:21:08 PM PDT 24	2613772631 ps
T395	/workspace/coverage/default/21.sysrst_ctrl_stress_all.4029521516	Apr 18 02:21:33 PM PDT 24	Apr 18 02:21:44 PM PDT 24	14133192826 ps
T381	/workspace/coverage/default/44.sysrst_ctrl_stress_all.531449897	Apr 18 02:23:09 PM PDT 24	Apr 18 02:23:32 PM PDT 24	8450389547 ps
T43	/workspace/coverage/default/6.sysrst_ctrl_edge_detect.515517902	Apr 18 02:20:25 PM PDT 24	Apr 18 02:20:36 PM PDT 24	3680530330 ps
T314	/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3684751438	Apr 18 02:21:57 PM PDT 24	Apr 18 02:22:00 PM PDT 24	3686320836 ps
T111	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.4261306079	Apr 18 02:21:49 PM PDT 24	Apr 18 02:23:51 PM PDT 24	51583278818 ps
T213	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.2958945406	Apr 18 02:20:06 PM PDT 24	Apr 18 02:20:16 PM PDT 24	6045979920 ps
T85	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2493483614	Apr 18 02:23:16 PM PDT 24	Apr 18 02:24:06 PM PDT 24	95951701972 ps
T281	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.2528851947	Apr 18 02:19:56 PM PDT 24	Apr 18 02:20:11 PM PDT 24	22064109081 ps
T305	/workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.2352395348	Apr 18 02:20:02 PM PDT 24	Apr 18 02:20:04 PM PDT 24	2456357875 ps
T306	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.1701805694	Apr 18 02:20:44 PM PDT 24	Apr 18 02:20:52 PM PDT 24	2510816388 ps
T307	/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3046755125	Apr 18 02:23:18 PM PDT 24	Apr 18 02:23:22 PM PDT 24	2469309921 ps
T308	/workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2947372730	Apr 18 02:20:02 PM PDT 24	Apr 18 02:20:11 PM PDT 24	2983038294 ps
T309	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2161424757	Apr 18 02:21:47 PM PDT 24	Apr 18 02:22:23 PM PDT 24	116471982762 ps
T174	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.700156390	Apr 18 02:21:23 PM PDT 24	Apr 18 02:21:34 PM PDT 24	4668666234 ps
T310	/workspace/coverage/default/46.sysrst_ctrl_smoke.885647301	Apr 18 02:23:07 PM PDT 24	Apr 18 02:23:14 PM PDT 24	2110971706 ps
T311	/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2865724369	Apr 18 02:22:18 PM PDT 24	Apr 18 02:22:20 PM PDT 24	2649923745 ps
T312	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1638442003	Apr 18 02:23:30 PM PDT 24	Apr 18 02:24:09 PM PDT 24	57006701848 ps
T177	/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1761067522	Apr 18 02:23:18 PM PDT 24	Apr 18 02:24:55 PM PDT 24	62411508760 ps
T421	/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.89183356	Apr 18 02:23:24 PM PDT 24	Apr 18 02:23:25 PM PDT 24	3038960926 ps
T422	/workspace/coverage/default/21.sysrst_ctrl_pin_access_test.1203505517	Apr 18 02:21:31 PM PDT 24	Apr 18 02:21:35 PM PDT 24	2245879249 ps
T423	/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3474960037	Apr 18 02:22:14 PM PDT 24	Apr 18 02:22:17 PM PDT 24	2734407372 ps
T424	/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2703547935	Apr 18 02:20:14 PM PDT 24	Apr 18 02:20:22 PM PDT 24	2609968813 ps
T425	/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4238011153	Apr 18 02:23:01 PM PDT 24	Apr 18 02:23:04 PM PDT 24	2625062632 ps
T264	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.800567449	Apr 18 02:22:09 PM PDT 24	Apr 18 02:22:38 PM PDT 24	73572589751 ps
T201	/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1225137716	Apr 18 02:20:30 PM PDT 24	Apr 18 02:20:34 PM PDT 24	2424824797 ps
T426	/workspace/coverage/default/48.sysrst_ctrl_smoke.1490750389	Apr 18 02:23:20 PM PDT 24	Apr 18 02:23:22 PM PDT 24	2133232648 ps
T205	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3792001700	Apr 18 02:23:01 PM PDT 24	Apr 18 02:23:14 PM PDT 24	36843966432 ps
T427	/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3372119473	Apr 18 02:21:43 PM PDT 24	Apr 18 02:21:52 PM PDT 24	3140557457 ps
T428	/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1642731951	Apr 18 02:22:20 PM PDT 24	Apr 18 02:22:25 PM PDT 24	2460986466 ps
T86	/workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2542610524	Apr 18 02:22:02 PM PDT 24	Apr 18 02:22:09 PM PDT 24	7628240879 ps
T429	/workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3082167100	Apr 18 02:21:36 PM PDT 24	Apr 18 02:21:39 PM PDT 24	2076846412 ps
T430	/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2569014125	Apr 18 02:21:53 PM PDT 24	Apr 18 02:22:02 PM PDT 24	2475411542 ps
T112	/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1842300913	Apr 18 02:23:28 PM PDT 24	Apr 18 02:23:58 PM PDT 24	25841768829 ps
T431	/workspace/coverage/default/46.sysrst_ctrl_stress_all.975692624	Apr 18 02:23:11 PM PDT 24	Apr 18 02:23:22 PM PDT 24	7086489811 ps
T266	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.2148931480	Apr 18 02:20:54 PM PDT 24	Apr 18 02:21:14 PM PDT 24	31619863611 ps
T432	/workspace/coverage/default/12.sysrst_ctrl_pin_access_test.295771061	Apr 18 02:20:49 PM PDT 24	Apr 18 02:20:53 PM PDT 24	2247284023 ps
T260	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3369532877	Apr 18 02:23:30 PM PDT 24	Apr 18 02:24:01 PM PDT 24	24833642061 ps
T433	/workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1656089996	Apr 18 02:21:11 PM PDT 24	Apr 18 02:21:14 PM PDT 24	2526097417 ps
T434	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.763348443	Apr 18 02:20:13 PM PDT 24	Apr 18 02:20:16 PM PDT 24	2377260900 ps
T175	/workspace/coverage/default/35.sysrst_ctrl_stress_all.3773286139	Apr 18 02:22:32 PM PDT 24	Apr 18 02:58:27 PM PDT 24	1243215120942 ps
T435	/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1681253577	Apr 18 02:22:14 PM PDT 24	Apr 18 02:22:21 PM PDT 24	2182909900 ps
T436	/workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3757679331	Apr 18 02:22:08 PM PDT 24	Apr 18 02:22:13 PM PDT 24	2711823895 ps
T437	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2681102478	Apr 18 02:21:50 PM PDT 24	Apr 18 02:21:58 PM PDT 24	2468165711 ps
T323	/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1391211060	Apr 18 02:20:40 PM PDT 24	Apr 18 02:20:43 PM PDT 24	5735693576 ps
T178	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.462982751	Apr 18 02:19:52 PM PDT 24	Apr 18 02:19:55 PM PDT 24	2480330164 ps
T267	/workspace/coverage/default/11.sysrst_ctrl_combo_detect.3613778012	Apr 18 02:20:43 PM PDT 24	Apr 18 02:22:31 PM PDT 24	42616849381 ps
T438	/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3828551420	Apr 18 02:22:21 PM PDT 24	Apr 18 02:22:27 PM PDT 24	2513516534 ps
T439	/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.189918975	Apr 18 02:19:45 PM PDT 24	Apr 18 02:19:54 PM PDT 24	2839629790 ps
T440	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.857843898	Apr 18 02:22:56 PM PDT 24	Apr 18 02:23:27 PM PDT 24	10694301809 ps
T265	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2580182876	Apr 18 02:23:14 PM PDT 24	Apr 18 02:24:01 PM PDT 24	32931487760 ps
T113	/workspace/coverage/default/4.sysrst_ctrl_combo_detect.3762141096	Apr 18 02:20:14 PM PDT 24	Apr 18 02:20:42 PM PDT 24	105636246089 ps
T371	/workspace/coverage/default/17.sysrst_ctrl_combo_detect.3671104425	Apr 18 02:21:11 PM PDT 24	Apr 18 02:28:31 PM PDT 24	166917418174 ps
T270	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2736490443	Apr 18 02:23:24 PM PDT 24	Apr 18 02:24:05 PM PDT 24	107835608331 ps
T268	/workspace/coverage/default/39.sysrst_ctrl_stress_all.769305633	Apr 18 02:22:48 PM PDT 24	Apr 18 02:23:55 PM PDT 24	154187712925 ps
T441	/workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.101711794	Apr 18 02:22:23 PM PDT 24	Apr 18 02:22:29 PM PDT 24	3642581152 ps
T442	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.926772274	Apr 18 02:22:49 PM PDT 24	Apr 18 02:22:57 PM PDT 24	2509862894 ps
T443	/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2408588748	Apr 18 02:23:03 PM PDT 24	Apr 18 02:23:06 PM PDT 24	3535874020 ps
T370	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3352749470	Apr 18 02:22:20 PM PDT 24	Apr 18 02:22:35 PM PDT 24	46809700263 ps
T444	/workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3849291399	Apr 18 02:22:20 PM PDT 24	Apr 18 02:22:23 PM PDT 24	3391115430 ps
T445	/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1761961025	Apr 18 02:21:31 PM PDT 24	Apr 18 02:23:20 PM PDT 24	156392609385 ps
T271	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.238543730	Apr 18 02:22:11 PM PDT 24	Apr 18 02:24:43 PM PDT 24	55652633849 ps
T446	/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3940806755	Apr 18 02:20:41 PM PDT 24	Apr 18 02:20:47 PM PDT 24	2172944551 ps
T447	/workspace/coverage/default/21.sysrst_ctrl_alert_test.1568602205	Apr 18 02:21:35 PM PDT 24	Apr 18 02:21:39 PM PDT 24	2039172048 ps
T373	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4145832665	Apr 18 02:23:28 PM PDT 24	Apr 18 02:27:30 PM PDT 24	91268118608 ps
T357	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3996859259	Apr 18 02:21:22 PM PDT 24	Apr 18 02:21:54 PM PDT 24	115972574247 ps
T448	/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.241127097	Apr 18 02:21:37 PM PDT 24	Apr 18 02:21:48 PM PDT 24	3544732179 ps
T449	/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.982731106	Apr 18 02:20:14 PM PDT 24	Apr 18 02:20:16 PM PDT 24	2500197760 ps
T152	/workspace/coverage/default/31.sysrst_ctrl_edge_detect.213508227	Apr 18 02:22:14 PM PDT 24	Apr 18 02:22:23 PM PDT 24	5074030069 ps
T164	/workspace/coverage/default/26.sysrst_ctrl_combo_detect.585862681	Apr 18 02:21:53 PM PDT 24	Apr 18 02:29:32 PM PDT 24	173501935324 ps
T165	/workspace/coverage/default/0.sysrst_ctrl_smoke.174717073	Apr 18 02:19:45 PM PDT 24	Apr 18 02:19:52 PM PDT 24	2113568995 ps
T166	/workspace/coverage/default/24.sysrst_ctrl_alert_test.1738163720	Apr 18 02:21:46 PM PDT 24	Apr 18 02:21:50 PM PDT 24	2023067294 ps
T167	/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.314504813	Apr 18 02:21:54 PM PDT 24	Apr 18 02:21:56 PM PDT 24	2181455814 ps
T168	/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1970717548	Apr 18 02:20:25 PM PDT 24	Apr 18 02:20:33 PM PDT 24	2608011785 ps
T169	/workspace/coverage/default/4.sysrst_ctrl_alert_test.893424748	Apr 18 02:20:12 PM PDT 24	Apr 18 02:20:14 PM PDT 24	2023861374 ps
T90	/workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2810099693	Apr 18 02:20:02 PM PDT 24	Apr 18 02:22:06 PM PDT 24	48910709861 ps
T170	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3724454242	Apr 18 02:22:26 PM PDT 24	Apr 18 02:26:54 PM PDT 24	101826756020 ps
T171	/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2989721342	Apr 18 02:21:48 PM PDT 24	Apr 18 02:26:36 PM PDT 24	967614772633 ps
T450	/workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3906137224	Apr 18 02:21:34 PM PDT 24	Apr 18 02:21:49 PM PDT 24	5655166191 ps
T451	/workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3448591577	Apr 18 02:21:36 PM PDT 24	Apr 18 02:21:45 PM PDT 24	2615305725 ps
T452	/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.68894489	Apr 18 02:21:06 PM PDT 24	Apr 18 02:21:15 PM PDT 24	3010758212 ps
T95	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4275756051	Apr 18 02:20:59 PM PDT 24	Apr 18 02:22:13 PM PDT 24	121211772438 ps
T87	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.3822540014	Apr 18 02:19:51 PM PDT 24	Apr 18 02:20:21 PM PDT 24	41822761240 ps
T133	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2751458125	Apr 18 02:20:23 PM PDT 24	Apr 18 02:20:32 PM PDT 24	4465149275 ps
T134	/workspace/coverage/default/12.sysrst_ctrl_stress_all.4004540356	Apr 18 02:20:59 PM PDT 24	Apr 18 02:27:39 PM PDT 24	152901911095 ps
T135	/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.689395563	Apr 18 02:23:36 PM PDT 24	Apr 18 02:23:54 PM PDT 24	25853434437 ps
T136	/workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1229056422	Apr 18 02:21:01 PM PDT 24	Apr 18 02:21:04 PM PDT 24	3668232286 ps
T137	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2353792143	Apr 18 02:23:26 PM PDT 24	Apr 18 02:24:35 PM PDT 24	52130451932 ps
T138	/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2036158359	Apr 18 02:20:28 PM PDT 24	Apr 18 02:20:33 PM PDT 24	2457722942 ps
T139	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.2533726302	Apr 18 02:21:42 PM PDT 24	Apr 18 02:21:46 PM PDT 24	3189407538 ps
T140	/workspace/coverage/default/32.sysrst_ctrl_combo_detect.2016764871	Apr 18 02:22:21 PM PDT 24	Apr 18 02:29:56 PM PDT 24	169019950999 ps
T453	/workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.879573453	Apr 18 02:22:15 PM PDT 24	Apr 18 02:22:48 PM PDT 24	48208025688 ps
T454	/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1451614778	Apr 18 02:21:00 PM PDT 24	Apr 18 02:21:03 PM PDT 24	2083742604 ps
T118	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1725756817	Apr 18 02:22:21 PM PDT 24	Apr 18 02:22:27 PM PDT 24	6202295220 ps