Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_inXval
Uncovered bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_outXval
Uncovered bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_inXval
Uncovered bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_outXval
Uncovered bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_inXval
Uncovered bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_outXval
Uncovered bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_inXval
Uncovered bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_outXval
Uncovered bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for ac_presentXval
Uncovered bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Uncovered bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for lid_openXval
Uncovered bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Uncovered bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T1 |
13 |
|
T4 |
10 |
|
T21 |
10 |
| auto[1] |
871 |
1 |
|
|
T1 |
7 |
|
T4 |
10 |
|
T21 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
859 |
1 |
|
|
T1 |
5 |
|
T4 |
6 |
|
T21 |
8 |
| auto[1] |
921 |
1 |
|
|
T1 |
15 |
|
T4 |
14 |
|
T21 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T1 |
12 |
|
T4 |
9 |
|
T21 |
11 |
| auto[1] |
874 |
1 |
|
|
T1 |
8 |
|
T4 |
11 |
|
T21 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T1 |
7 |
|
T4 |
9 |
|
T21 |
13 |
| auto[1] |
901 |
1 |
|
|
T1 |
13 |
|
T4 |
11 |
|
T21 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
915 |
1 |
|
|
T1 |
12 |
|
T4 |
12 |
|
T21 |
10 |
| auto[1] |
865 |
1 |
|
|
T1 |
8 |
|
T4 |
8 |
|
T21 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T1 |
8 |
|
T4 |
11 |
|
T21 |
10 |
| auto[1] |
893 |
1 |
|
|
T1 |
12 |
|
T4 |
9 |
|
T21 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T1 |
12 |
|
T4 |
11 |
|
T21 |
12 |
| auto[1] |
887 |
1 |
|
|
T1 |
8 |
|
T4 |
9 |
|
T21 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
924 |
1 |
|
|
T1 |
12 |
|
T4 |
10 |
|
T21 |
10 |
| auto[1] |
856 |
1 |
|
|
T1 |
8 |
|
T4 |
10 |
|
T21 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T1 |
9 |
|
T4 |
9 |
|
T21 |
11 |
| auto[1] |
908 |
1 |
|
|
T1 |
11 |
|
T4 |
11 |
|
T21 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
910 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T21 |
7 |
| auto[1] |
870 |
1 |
|
|
T1 |
11 |
|
T4 |
6 |
|
T21 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
920 |
1 |
|
|
T1 |
11 |
|
T4 |
13 |
|
T21 |
14 |
| auto[1] |
860 |
1 |
|
|
T1 |
9 |
|
T4 |
7 |
|
T21 |
6 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
828 |
1 |
|
|
T1 |
6 |
|
T4 |
6 |
|
T21 |
11 |
| auto[1] |
952 |
1 |
|
|
T1 |
14 |
|
T4 |
14 |
|
T21 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T1 |
7 |
|
T4 |
6 |
|
T21 |
9 |
| auto[1] |
895 |
1 |
|
|
T1 |
13 |
|
T4 |
14 |
|
T21 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
859 |
1 |
|
|
T1 |
5 |
|
T4 |
6 |
|
T21 |
8 |
| auto[1] |
921 |
1 |
|
|
T1 |
15 |
|
T4 |
14 |
|
T21 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T1 |
14 |
|
T4 |
12 |
|
T21 |
9 |
| auto[1] |
898 |
1 |
|
|
T1 |
6 |
|
T4 |
8 |
|
T21 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T1 |
5 |
|
T4 |
12 |
|
T21 |
11 |
| auto[1] |
863 |
1 |
|
|
T1 |
15 |
|
T4 |
8 |
|
T21 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T1 |
13 |
|
T4 |
13 |
|
T21 |
11 |
| auto[1] |
883 |
1 |
|
|
T1 |
7 |
|
T4 |
7 |
|
T21 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T1 |
13 |
|
T4 |
10 |
|
T21 |
7 |
| auto[1] |
881 |
1 |
|
|
T1 |
7 |
|
T4 |
10 |
|
T21 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
861 |
1 |
|
|
T1 |
9 |
|
T4 |
10 |
|
T21 |
9 |
| auto[1] |
919 |
1 |
|
|
T1 |
11 |
|
T4 |
10 |
|
T21 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T1 |
7 |
|
T4 |
7 |
|
T21 |
9 |
| auto[1] |
914 |
1 |
|
|
T1 |
13 |
|
T4 |
13 |
|
T21 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T1 |
11 |
|
T4 |
11 |
|
T21 |
12 |
| auto[1] |
912 |
1 |
|
|
T1 |
9 |
|
T4 |
9 |
|
T21 |
8 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
888 |
1 |
|
|
T1 |
12 |
|
T4 |
11 |
|
T21 |
13 |
| auto[1] |
892 |
1 |
|
|
T1 |
8 |
|
T4 |
9 |
|
T21 |
7 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T1 |
14 |
|
T4 |
8 |
|
T21 |
4 |
| auto[1] |
922 |
1 |
|
|
T1 |
6 |
|
T4 |
12 |
|
T21 |
16 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
828 |
1 |
|
|
T1 |
6 |
|
T4 |
6 |
|
T21 |
11 |
| auto[1] |
952 |
1 |
|
|
T1 |
14 |
|
T4 |
14 |
|
T21 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
459 |
1 |
|
|
T1 |
10 |
|
T4 |
6 |
|
T21 |
5 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T1 |
4 |
|
T4 |
6 |
|
T21 |
4 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T1 |
2 |
|
T4 |
3 |
|
T21 |
6 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T1 |
4 |
|
T4 |
5 |
|
T21 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
463 |
1 |
|
|
T1 |
3 |
|
T4 |
6 |
|
T21 |
7 |
| auto[0] |
auto[1] |
454 |
1 |
|
|
T1 |
2 |
|
T4 |
6 |
|
T21 |
4 |
| auto[1] |
auto[0] |
416 |
1 |
|
|
T1 |
4 |
|
T4 |
3 |
|
T21 |
6 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T1 |
11 |
|
T4 |
5 |
|
T21 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
462 |
1 |
|
|
T1 |
6 |
|
T4 |
8 |
|
T21 |
6 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T1 |
7 |
|
T4 |
5 |
|
T21 |
5 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T1 |
6 |
|
T4 |
4 |
|
T21 |
4 |
| auto[1] |
auto[1] |
430 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T21 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
449 |
1 |
|
|
T1 |
4 |
|
T4 |
6 |
|
T21 |
4 |
| auto[0] |
auto[1] |
450 |
1 |
|
|
T1 |
9 |
|
T4 |
4 |
|
T21 |
3 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T1 |
4 |
|
T4 |
5 |
|
T21 |
6 |
| auto[1] |
auto[1] |
443 |
1 |
|
|
T1 |
3 |
|
T4 |
5 |
|
T21 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T1 |
7 |
|
T4 |
5 |
|
T21 |
4 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T1 |
2 |
|
T4 |
5 |
|
T21 |
5 |
| auto[1] |
auto[0] |
466 |
1 |
|
|
T1 |
5 |
|
T4 |
6 |
|
T21 |
8 |
| auto[1] |
auto[1] |
453 |
1 |
|
|
T1 |
6 |
|
T4 |
4 |
|
T21 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
445 |
1 |
|
|
T1 |
6 |
|
T4 |
3 |
|
T21 |
3 |
| auto[0] |
auto[1] |
421 |
1 |
|
|
T1 |
1 |
|
T4 |
4 |
|
T21 |
6 |
| auto[1] |
auto[0] |
479 |
1 |
|
|
T1 |
6 |
|
T4 |
7 |
|
T21 |
7 |
| auto[1] |
auto[1] |
435 |
1 |
|
|
T1 |
7 |
|
T4 |
6 |
|
T21 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
453 |
1 |
|
|
T1 |
7 |
|
T4 |
7 |
|
T21 |
4 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T1 |
5 |
|
T4 |
4 |
|
T21 |
9 |
| auto[1] |
auto[0] |
457 |
1 |
|
|
T1 |
2 |
|
T4 |
7 |
|
T21 |
3 |
| auto[1] |
auto[1] |
435 |
1 |
|
|
T1 |
6 |
|
T4 |
2 |
|
T21 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
443 |
1 |
|
|
T1 |
9 |
|
T4 |
5 |
|
T21 |
3 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T1 |
5 |
|
T4 |
3 |
|
T21 |
1 |
| auto[1] |
auto[0] |
477 |
1 |
|
|
T1 |
2 |
|
T4 |
8 |
|
T21 |
11 |
| auto[1] |
auto[1] |
445 |
1 |
|
|
T1 |
4 |
|
T4 |
4 |
|
T21 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
446 |
1 |
|
|
T1 |
5 |
|
T4 |
2 |
|
T21 |
4 |
| auto[0] |
auto[1] |
439 |
1 |
|
|
T1 |
2 |
|
T4 |
4 |
|
T21 |
5 |
| auto[1] |
auto[0] |
463 |
1 |
|
|
T1 |
8 |
|
T4 |
8 |
|
T21 |
6 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T1 |
5 |
|
T4 |
6 |
|
T21 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
859 |
1 |
|
|
T1 |
5 |
|
T4 |
6 |
|
T21 |
8 |
| auto[1] |
auto[1] |
921 |
1 |
|
|
T1 |
15 |
|
T4 |
14 |
|
T21 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T1 |
3 |
|
T4 |
7 |
|
T21 |
6 |
| auto[0] |
auto[1] |
449 |
1 |
|
|
T1 |
8 |
|
T4 |
4 |
|
T21 |
6 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T1 |
6 |
|
T4 |
2 |
|
T21 |
5 |
| auto[1] |
auto[1] |
459 |
1 |
|
|
T1 |
3 |
|
T4 |
7 |
|
T21 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
828 |
1 |
|
|
T1 |
6 |
|
T4 |
6 |
|
T21 |
11 |
| auto[1] |
auto[1] |
952 |
1 |
|
|
T1 |
14 |
|
T4 |
14 |
|
T21 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
207 |
1 |
|
|
T4 |
7 |
|
T67 |
11 |
|
T11 |
10 |
| auto[1] |
213 |
1 |
|
|
T4 |
13 |
|
T67 |
9 |
|
T11 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
220 |
1 |
|
|
T4 |
12 |
|
T67 |
8 |
|
T11 |
11 |
| auto[1] |
200 |
1 |
|
|
T4 |
8 |
|
T67 |
12 |
|
T11 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
198 |
1 |
|
|
T4 |
7 |
|
T67 |
12 |
|
T11 |
13 |
| auto[1] |
222 |
1 |
|
|
T4 |
13 |
|
T67 |
8 |
|
T11 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
230 |
1 |
|
|
T4 |
14 |
|
T67 |
15 |
|
T11 |
12 |
| auto[1] |
190 |
1 |
|
|
T4 |
6 |
|
T67 |
5 |
|
T11 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
212 |
1 |
|
|
T4 |
11 |
|
T67 |
11 |
|
T11 |
9 |
| auto[1] |
208 |
1 |
|
|
T4 |
9 |
|
T67 |
9 |
|
T11 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
212 |
1 |
|
|
T4 |
9 |
|
T67 |
11 |
|
T11 |
12 |
| auto[1] |
208 |
1 |
|
|
T4 |
11 |
|
T67 |
9 |
|
T11 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
217 |
1 |
|
|
T4 |
11 |
|
T67 |
9 |
|
T11 |
11 |
| auto[1] |
203 |
1 |
|
|
T4 |
9 |
|
T67 |
11 |
|
T11 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
211 |
1 |
|
|
T4 |
13 |
|
T67 |
12 |
|
T11 |
11 |
| auto[1] |
209 |
1 |
|
|
T4 |
7 |
|
T67 |
8 |
|
T11 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
210 |
1 |
|
|
T4 |
9 |
|
T67 |
11 |
|
T11 |
13 |
| auto[1] |
210 |
1 |
|
|
T4 |
11 |
|
T67 |
9 |
|
T11 |
7 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
200 |
1 |
|
|
T4 |
8 |
|
T67 |
5 |
|
T11 |
7 |
| auto[1] |
220 |
1 |
|
|
T4 |
12 |
|
T67 |
15 |
|
T11 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
210 |
1 |
|
|
T4 |
13 |
|
T67 |
10 |
|
T11 |
10 |
| auto[1] |
210 |
1 |
|
|
T4 |
7 |
|
T67 |
10 |
|
T11 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
216 |
1 |
|
|
T4 |
7 |
|
T67 |
9 |
|
T11 |
10 |
| auto[1] |
204 |
1 |
|
|
T4 |
13 |
|
T67 |
11 |
|
T11 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
233 |
1 |
|
|
T4 |
11 |
|
T67 |
14 |
|
T11 |
12 |
| auto[1] |
187 |
1 |
|
|
T4 |
9 |
|
T67 |
6 |
|
T11 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
220 |
1 |
|
|
T4 |
12 |
|
T67 |
8 |
|
T11 |
11 |
| auto[1] |
200 |
1 |
|
|
T4 |
8 |
|
T67 |
12 |
|
T11 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
201 |
1 |
|
|
T4 |
11 |
|
T67 |
9 |
|
T11 |
8 |
| auto[1] |
219 |
1 |
|
|
T4 |
9 |
|
T67 |
11 |
|
T11 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
201 |
1 |
|
|
T4 |
8 |
|
T67 |
8 |
|
T11 |
9 |
| auto[1] |
219 |
1 |
|
|
T4 |
12 |
|
T67 |
12 |
|
T11 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
194 |
1 |
|
|
T4 |
9 |
|
T67 |
9 |
|
T11 |
12 |
| auto[1] |
226 |
1 |
|
|
T4 |
11 |
|
T67 |
11 |
|
T11 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
196 |
1 |
|
|
T4 |
9 |
|
T67 |
11 |
|
T11 |
11 |
| auto[1] |
224 |
1 |
|
|
T4 |
11 |
|
T67 |
9 |
|
T11 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
202 |
1 |
|
|
T4 |
9 |
|
T67 |
9 |
|
T11 |
11 |
| auto[1] |
218 |
1 |
|
|
T4 |
11 |
|
T67 |
11 |
|
T11 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
216 |
1 |
|
|
T4 |
9 |
|
T67 |
14 |
|
T11 |
13 |
| auto[1] |
204 |
1 |
|
|
T4 |
11 |
|
T67 |
6 |
|
T11 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
202 |
1 |
|
|
T4 |
8 |
|
T67 |
9 |
|
T11 |
5 |
| auto[1] |
218 |
1 |
|
|
T4 |
12 |
|
T67 |
11 |
|
T11 |
15 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
213 |
1 |
|
|
T4 |
12 |
|
T67 |
9 |
|
T11 |
14 |
| auto[1] |
207 |
1 |
|
|
T4 |
8 |
|
T67 |
11 |
|
T11 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
205 |
1 |
|
|
T4 |
11 |
|
T67 |
4 |
|
T11 |
9 |
| auto[1] |
215 |
1 |
|
|
T4 |
9 |
|
T67 |
16 |
|
T11 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
216 |
1 |
|
|
T4 |
7 |
|
T67 |
9 |
|
T11 |
10 |
| auto[1] |
204 |
1 |
|
|
T4 |
13 |
|
T67 |
11 |
|
T11 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
87 |
1 |
|
|
T4 |
3 |
|
T67 |
4 |
|
T11 |
4 |
| auto[0] |
auto[1] |
114 |
1 |
|
|
T4 |
8 |
|
T67 |
5 |
|
T11 |
4 |
| auto[1] |
auto[0] |
111 |
1 |
|
|
T4 |
4 |
|
T67 |
8 |
|
T11 |
9 |
| auto[1] |
auto[1] |
108 |
1 |
|
|
T4 |
5 |
|
T67 |
3 |
|
T11 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T4 |
5 |
|
T67 |
5 |
|
T11 |
4 |
| auto[0] |
auto[1] |
98 |
1 |
|
|
T4 |
3 |
|
T67 |
3 |
|
T11 |
5 |
| auto[1] |
auto[0] |
127 |
1 |
|
|
T4 |
9 |
|
T67 |
10 |
|
T11 |
8 |
| auto[1] |
auto[1] |
92 |
1 |
|
|
T4 |
3 |
|
T67 |
2 |
|
T11 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
108 |
1 |
|
|
T4 |
6 |
|
T67 |
5 |
|
T11 |
5 |
| auto[0] |
auto[1] |
86 |
1 |
|
|
T4 |
3 |
|
T67 |
4 |
|
T11 |
7 |
| auto[1] |
auto[0] |
104 |
1 |
|
|
T4 |
5 |
|
T67 |
6 |
|
T11 |
4 |
| auto[1] |
auto[1] |
122 |
1 |
|
|
T4 |
6 |
|
T67 |
5 |
|
T11 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
109 |
1 |
|
|
T4 |
5 |
|
T67 |
6 |
|
T11 |
6 |
| auto[0] |
auto[1] |
87 |
1 |
|
|
T4 |
4 |
|
T67 |
5 |
|
T11 |
5 |
| auto[1] |
auto[0] |
103 |
1 |
|
|
T4 |
4 |
|
T67 |
5 |
|
T11 |
6 |
| auto[1] |
auto[1] |
121 |
1 |
|
|
T4 |
7 |
|
T67 |
4 |
|
T11 |
3 |