Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
106 |
1 |
|
|
T4 |
5 |
|
T67 |
5 |
|
T11 |
5 |
| auto[0] |
auto[1] |
96 |
1 |
|
|
T4 |
4 |
|
T67 |
4 |
|
T11 |
6 |
| auto[1] |
auto[0] |
111 |
1 |
|
|
T4 |
6 |
|
T67 |
4 |
|
T11 |
6 |
| auto[1] |
auto[1] |
107 |
1 |
|
|
T4 |
5 |
|
T67 |
7 |
|
T11 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
110 |
1 |
|
|
T4 |
6 |
|
T67 |
9 |
|
T11 |
6 |
| auto[0] |
auto[1] |
106 |
1 |
|
|
T4 |
3 |
|
T67 |
5 |
|
T11 |
7 |
| auto[1] |
auto[0] |
101 |
1 |
|
|
T4 |
7 |
|
T67 |
3 |
|
T11 |
5 |
| auto[1] |
auto[1] |
103 |
1 |
|
|
T4 |
4 |
|
T67 |
3 |
|
T11 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
102 |
1 |
|
|
T4 |
5 |
|
T67 |
1 |
|
T11 |
5 |
| auto[0] |
auto[1] |
111 |
1 |
|
|
T4 |
7 |
|
T67 |
8 |
|
T11 |
9 |
| auto[1] |
auto[0] |
98 |
1 |
|
|
T4 |
3 |
|
T67 |
4 |
|
T11 |
2 |
| auto[1] |
auto[1] |
109 |
1 |
|
|
T4 |
5 |
|
T67 |
7 |
|
T11 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T4 |
7 |
|
T67 |
1 |
|
T11 |
4 |
| auto[0] |
auto[1] |
102 |
1 |
|
|
T4 |
4 |
|
T67 |
3 |
|
T11 |
5 |
| auto[1] |
auto[0] |
107 |
1 |
|
|
T4 |
6 |
|
T67 |
9 |
|
T11 |
6 |
| auto[1] |
auto[1] |
108 |
1 |
|
|
T4 |
3 |
|
T67 |
7 |
|
T11 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
116 |
1 |
|
|
T4 |
3 |
|
T67 |
8 |
|
T11 |
7 |
| auto[0] |
auto[1] |
117 |
1 |
|
|
T4 |
8 |
|
T67 |
6 |
|
T11 |
5 |
| auto[1] |
auto[0] |
91 |
1 |
|
|
T4 |
4 |
|
T67 |
3 |
|
T11 |
3 |
| auto[1] |
auto[1] |
96 |
1 |
|
|
T4 |
5 |
|
T67 |
3 |
|
T11 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
220 |
1 |
|
|
T4 |
12 |
|
T67 |
8 |
|
T11 |
11 |
| auto[1] |
auto[1] |
200 |
1 |
|
|
T4 |
8 |
|
T67 |
12 |
|
T11 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
89 |
1 |
|
|
T4 |
3 |
|
T67 |
6 |
|
T11 |
2 |
| auto[0] |
auto[1] |
113 |
1 |
|
|
T4 |
5 |
|
T67 |
3 |
|
T11 |
3 |
| auto[1] |
auto[0] |
121 |
1 |
|
|
T4 |
6 |
|
T67 |
5 |
|
T11 |
11 |
| auto[1] |
auto[1] |
97 |
1 |
|
|
T4 |
6 |
|
T67 |
6 |
|
T11 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
216 |
1 |
|
|
T4 |
7 |
|
T67 |
9 |
|
T11 |
10 |
| auto[1] |
auto[1] |
204 |
1 |
|
|
T4 |
13 |
|
T67 |
11 |
|
T11 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |