Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T1 |
14 |
|
T5 |
15 |
|
T14 |
13 |
| auto[1] |
838 |
1 |
|
|
T1 |
6 |
|
T5 |
5 |
|
T14 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T1 |
4 |
|
T5 |
10 |
|
T14 |
7 |
| auto[1] |
871 |
1 |
|
|
T1 |
16 |
|
T5 |
10 |
|
T14 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
817 |
1 |
|
|
T1 |
6 |
|
T5 |
10 |
|
T14 |
12 |
| auto[1] |
903 |
1 |
|
|
T1 |
14 |
|
T5 |
10 |
|
T14 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T1 |
13 |
|
T5 |
8 |
|
T14 |
11 |
| auto[1] |
842 |
1 |
|
|
T1 |
7 |
|
T5 |
12 |
|
T14 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T1 |
11 |
|
T5 |
12 |
|
T14 |
13 |
| auto[1] |
822 |
1 |
|
|
T1 |
9 |
|
T5 |
8 |
|
T14 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T1 |
12 |
|
T5 |
11 |
|
T14 |
12 |
| auto[1] |
873 |
1 |
|
|
T1 |
8 |
|
T5 |
9 |
|
T14 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T1 |
11 |
|
T5 |
9 |
|
T14 |
12 |
| auto[1] |
811 |
1 |
|
|
T1 |
9 |
|
T5 |
11 |
|
T14 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T1 |
10 |
|
T5 |
14 |
|
T14 |
12 |
| auto[1] |
827 |
1 |
|
|
T1 |
10 |
|
T5 |
6 |
|
T14 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T1 |
9 |
|
T5 |
12 |
|
T14 |
6 |
| auto[1] |
844 |
1 |
|
|
T1 |
11 |
|
T5 |
8 |
|
T14 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T1 |
13 |
|
T5 |
10 |
|
T14 |
11 |
| auto[1] |
852 |
1 |
|
|
T1 |
7 |
|
T5 |
10 |
|
T14 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T1 |
10 |
|
T5 |
12 |
|
T14 |
10 |
| auto[1] |
886 |
1 |
|
|
T1 |
10 |
|
T5 |
8 |
|
T14 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T1 |
10 |
|
T5 |
7 |
|
T14 |
10 |
| auto[1] |
840 |
1 |
|
|
T1 |
10 |
|
T5 |
13 |
|
T14 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T1 |
11 |
|
T5 |
7 |
|
T14 |
6 |
| auto[1] |
879 |
1 |
|
|
T1 |
9 |
|
T5 |
13 |
|
T14 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T1 |
4 |
|
T5 |
10 |
|
T14 |
7 |
| auto[1] |
871 |
1 |
|
|
T1 |
16 |
|
T5 |
10 |
|
T14 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T1 |
13 |
|
T5 |
7 |
|
T14 |
14 |
| auto[1] |
853 |
1 |
|
|
T1 |
7 |
|
T5 |
13 |
|
T14 |
6 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
838 |
1 |
|
|
T1 |
12 |
|
T5 |
11 |
|
T14 |
9 |
| auto[1] |
882 |
1 |
|
|
T1 |
8 |
|
T5 |
9 |
|
T14 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
869 |
1 |
|
|
T1 |
8 |
|
T5 |
6 |
|
T14 |
8 |
| auto[1] |
851 |
1 |
|
|
T1 |
12 |
|
T5 |
14 |
|
T14 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T1 |
13 |
|
T5 |
13 |
|
T14 |
9 |
| auto[1] |
894 |
1 |
|
|
T1 |
7 |
|
T5 |
7 |
|
T14 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T1 |
9 |
|
T5 |
12 |
|
T14 |
11 |
| auto[1] |
880 |
1 |
|
|
T1 |
11 |
|
T5 |
8 |
|
T14 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
884 |
1 |
|
|
T1 |
10 |
|
T5 |
11 |
|
T14 |
11 |
| auto[1] |
836 |
1 |
|
|
T1 |
10 |
|
T5 |
9 |
|
T14 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
857 |
1 |
|
|
T1 |
11 |
|
T5 |
9 |
|
T14 |
11 |
| auto[1] |
863 |
1 |
|
|
T1 |
9 |
|
T5 |
11 |
|
T14 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T1 |
10 |
|
T5 |
14 |
|
T14 |
13 |
| auto[1] |
854 |
1 |
|
|
T1 |
10 |
|
T5 |
6 |
|
T14 |
7 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
870 |
1 |
|
|
T1 |
5 |
|
T5 |
10 |
|
T14 |
14 |
| auto[1] |
850 |
1 |
|
|
T1 |
15 |
|
T5 |
10 |
|
T14 |
6 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T1 |
10 |
|
T5 |
7 |
|
T14 |
10 |
| auto[1] |
840 |
1 |
|
|
T1 |
10 |
|
T5 |
13 |
|
T14 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
418 |
1 |
|
|
T1 |
3 |
|
T5 |
4 |
|
T14 |
8 |
| auto[0] |
auto[1] |
449 |
1 |
|
|
T1 |
10 |
|
T5 |
3 |
|
T14 |
6 |
| auto[1] |
auto[0] |
399 |
1 |
|
|
T1 |
3 |
|
T5 |
6 |
|
T14 |
4 |
| auto[1] |
auto[1] |
454 |
1 |
|
|
T1 |
4 |
|
T5 |
7 |
|
T14 |
2 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T1 |
6 |
|
T5 |
5 |
|
T14 |
5 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T1 |
6 |
|
T5 |
6 |
|
T14 |
4 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T1 |
7 |
|
T5 |
3 |
|
T14 |
6 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T1 |
1 |
|
T5 |
6 |
|
T14 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
448 |
1 |
|
|
T1 |
5 |
|
T5 |
3 |
|
T14 |
4 |
| auto[0] |
auto[1] |
421 |
1 |
|
|
T1 |
3 |
|
T5 |
3 |
|
T14 |
4 |
| auto[1] |
auto[0] |
450 |
1 |
|
|
T1 |
6 |
|
T5 |
9 |
|
T14 |
9 |
| auto[1] |
auto[1] |
401 |
1 |
|
|
T1 |
6 |
|
T5 |
5 |
|
T14 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
401 |
1 |
|
|
T1 |
8 |
|
T5 |
6 |
|
T14 |
4 |
| auto[0] |
auto[1] |
425 |
1 |
|
|
T1 |
5 |
|
T5 |
7 |
|
T14 |
5 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T1 |
4 |
|
T5 |
5 |
|
T14 |
8 |
| auto[1] |
auto[1] |
448 |
1 |
|
|
T1 |
3 |
|
T5 |
2 |
|
T14 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
445 |
1 |
|
|
T1 |
4 |
|
T5 |
6 |
|
T14 |
6 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T1 |
5 |
|
T5 |
6 |
|
T14 |
5 |
| auto[1] |
auto[0] |
464 |
1 |
|
|
T1 |
7 |
|
T5 |
3 |
|
T14 |
6 |
| auto[1] |
auto[1] |
416 |
1 |
|
|
T1 |
4 |
|
T5 |
5 |
|
T14 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
459 |
1 |
|
|
T1 |
4 |
|
T5 |
8 |
|
T14 |
6 |
| auto[0] |
auto[1] |
425 |
1 |
|
|
T1 |
6 |
|
T5 |
3 |
|
T14 |
5 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T1 |
6 |
|
T5 |
6 |
|
T14 |
6 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T1 |
4 |
|
T5 |
3 |
|
T14 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T1 |
6 |
|
T5 |
8 |
|
T14 |
8 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T1 |
4 |
|
T5 |
6 |
|
T14 |
5 |
| auto[1] |
auto[0] |
431 |
1 |
|
|
T1 |
7 |
|
T5 |
2 |
|
T14 |
3 |
| auto[1] |
auto[1] |
423 |
1 |
|
|
T1 |
3 |
|
T5 |
4 |
|
T14 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T1 |
2 |
|
T5 |
7 |
|
T14 |
8 |
| auto[0] |
auto[1] |
448 |
1 |
|
|
T1 |
3 |
|
T5 |
3 |
|
T14 |
6 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T1 |
8 |
|
T5 |
5 |
|
T14 |
2 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T1 |
7 |
|
T5 |
5 |
|
T14 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
444 |
1 |
|
|
T1 |
9 |
|
T5 |
6 |
|
T14 |
4 |
| auto[0] |
auto[1] |
397 |
1 |
|
|
T1 |
2 |
|
T5 |
1 |
|
T14 |
2 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T1 |
5 |
|
T5 |
9 |
|
T14 |
9 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T1 |
4 |
|
T5 |
4 |
|
T14 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
849 |
1 |
|
|
T1 |
4 |
|
T5 |
10 |
|
T14 |
7 |
| auto[1] |
auto[1] |
871 |
1 |
|
|
T1 |
16 |
|
T5 |
10 |
|
T14 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
454 |
1 |
|
|
T1 |
7 |
|
T5 |
6 |
|
T14 |
4 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T1 |
4 |
|
T5 |
3 |
|
T14 |
7 |
| auto[1] |
auto[0] |
422 |
1 |
|
|
T1 |
2 |
|
T5 |
6 |
|
T14 |
2 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T1 |
7 |
|
T5 |
5 |
|
T14 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
880 |
1 |
|
|
T1 |
10 |
|
T5 |
7 |
|
T14 |
10 |
| auto[1] |
auto[1] |
840 |
1 |
|
|
T1 |
10 |
|
T5 |
13 |
|
T14 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
214 |
1 |
|
|
T1 |
12 |
|
T28 |
6 |
|
T30 |
6 |
| auto[1] |
246 |
1 |
|
|
T1 |
8 |
|
T28 |
14 |
|
T30 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
229 |
1 |
|
|
T1 |
13 |
|
T28 |
7 |
|
T30 |
14 |
| auto[1] |
231 |
1 |
|
|
T1 |
7 |
|
T28 |
13 |
|
T30 |
6 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
224 |
1 |
|
|
T1 |
6 |
|
T28 |
9 |
|
T30 |
10 |
| auto[1] |
236 |
1 |
|
|
T1 |
14 |
|
T28 |
11 |
|
T30 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
226 |
1 |
|
|
T1 |
12 |
|
T28 |
10 |
|
T30 |
14 |
| auto[1] |
234 |
1 |
|
|
T1 |
8 |
|
T28 |
10 |
|
T30 |
6 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
235 |
1 |
|
|
T1 |
10 |
|
T28 |
11 |
|
T30 |
10 |
| auto[1] |
225 |
1 |
|
|
T1 |
10 |
|
T28 |
9 |
|
T30 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
239 |
1 |
|
|
T1 |
12 |
|
T28 |
9 |
|
T30 |
9 |
| auto[1] |
221 |
1 |
|
|
T1 |
8 |
|
T28 |
11 |
|
T30 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
228 |
1 |
|
|
T1 |
9 |
|
T28 |
10 |
|
T30 |
14 |
| auto[1] |
232 |
1 |
|
|
T1 |
11 |
|
T28 |
10 |
|
T30 |
6 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
224 |
1 |
|
|
T1 |
12 |
|
T28 |
7 |
|
T30 |
10 |
| auto[1] |
236 |
1 |
|
|
T1 |
8 |
|
T28 |
13 |
|
T30 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
227 |
1 |
|
|
T1 |
9 |
|
T28 |
11 |
|
T30 |
9 |
| auto[1] |
233 |
1 |
|
|
T1 |
11 |
|
T28 |
9 |
|
T30 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
223 |
1 |
|
|
T1 |
10 |
|
T28 |
11 |
|
T30 |
10 |
| auto[1] |
237 |
1 |
|
|
T1 |
10 |
|
T28 |
9 |
|
T30 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
227 |
1 |
|
|
T1 |
11 |
|
T28 |
7 |
|
T30 |
7 |
| auto[1] |
233 |
1 |
|
|
T1 |
9 |
|
T28 |
13 |
|
T30 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
226 |
1 |
|
|
T1 |
9 |
|
T28 |
8 |
|
T30 |
6 |
| auto[1] |
234 |
1 |
|
|
T1 |
11 |
|
T28 |
12 |
|
T30 |
14 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
225 |
1 |
|
|
T1 |
12 |
|
T28 |
14 |
|
T30 |
8 |
| auto[1] |
235 |
1 |
|
|
T1 |
8 |
|
T28 |
6 |
|
T30 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
229 |
1 |
|
|
T1 |
13 |
|
T28 |
7 |
|
T30 |
14 |
| auto[1] |
231 |
1 |
|
|
T1 |
7 |
|
T28 |
13 |
|
T30 |
6 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
221 |
1 |
|
|
T1 |
10 |
|
T28 |
10 |
|
T30 |
11 |
| auto[1] |
239 |
1 |
|
|
T1 |
10 |
|
T28 |
10 |
|
T30 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
237 |
1 |
|
|
T1 |
10 |
|
T28 |
9 |
|
T30 |
9 |
| auto[1] |
223 |
1 |
|
|
T1 |
10 |
|
T28 |
11 |
|
T30 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
225 |
1 |
|
|
T1 |
8 |
|
T28 |
11 |
|
T30 |
7 |
| auto[1] |
235 |
1 |
|
|
T1 |
12 |
|
T28 |
9 |
|
T30 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
217 |
1 |
|
|
T1 |
8 |
|
T28 |
7 |
|
T30 |
14 |
| auto[1] |
243 |
1 |
|
|
T1 |
12 |
|
T28 |
13 |
|
T30 |
6 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
224 |
1 |
|
|
T1 |
8 |
|
T28 |
10 |
|
T30 |
13 |
| auto[1] |
236 |
1 |
|
|
T1 |
12 |
|
T28 |
10 |
|
T30 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
228 |
1 |
|
|
T1 |
11 |
|
T28 |
7 |
|
T30 |
11 |
| auto[1] |
232 |
1 |
|
|
T1 |
9 |
|
T28 |
13 |
|
T30 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
244 |
1 |
|
|
T1 |
7 |
|
T28 |
10 |
|
T30 |
14 |
| auto[1] |
216 |
1 |
|
|
T1 |
13 |
|
T28 |
10 |
|
T30 |
6 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
255 |
1 |
|
|
T1 |
9 |
|
T28 |
9 |
|
T30 |
11 |
| auto[1] |
205 |
1 |
|
|
T1 |
11 |
|
T28 |
11 |
|
T30 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
249 |
1 |
|
|
T1 |
10 |
|
T28 |
11 |
|
T30 |
8 |
| auto[1] |
211 |
1 |
|
|
T1 |
10 |
|
T28 |
9 |
|
T30 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
226 |
1 |
|
|
T1 |
9 |
|
T28 |
8 |
|
T30 |
6 |
| auto[1] |
234 |
1 |
|
|
T1 |
11 |
|
T28 |
12 |
|
T30 |
14 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
99 |
1 |
|
|
T1 |
1 |
|
T28 |
3 |
|
T30 |
6 |
| auto[0] |
auto[1] |
122 |
1 |
|
|
T1 |
9 |
|
T28 |
7 |
|
T30 |
5 |
| auto[1] |
auto[0] |
125 |
1 |
|
|
T1 |
5 |
|
T28 |
6 |
|
T30 |
4 |
| auto[1] |
auto[1] |
114 |
1 |
|
|
T1 |
5 |
|
T28 |
4 |
|
T30 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
108 |
1 |
|
|
T1 |
4 |
|
T28 |
3 |
|
T30 |
7 |
| auto[0] |
auto[1] |
129 |
1 |
|
|
T1 |
6 |
|
T28 |
6 |
|
T30 |
2 |
| auto[1] |
auto[0] |
118 |
1 |
|
|
T1 |
8 |
|
T28 |
7 |
|
T30 |
7 |
| auto[1] |
auto[1] |
105 |
1 |
|
|
T1 |
2 |
|
T28 |
4 |
|
T30 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
119 |
1 |
|
|
T1 |
4 |
|
T28 |
6 |
|
T30 |
3 |
| auto[0] |
auto[1] |
106 |
1 |
|
|
T1 |
4 |
|
T28 |
5 |
|
T30 |
4 |
| auto[1] |
auto[0] |
116 |
1 |
|
|
T1 |
6 |
|
T28 |
5 |
|
T30 |
7 |
| auto[1] |
auto[1] |
119 |
1 |
|
|
T1 |
6 |
|
T28 |
4 |
|
T30 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
117 |
1 |
|
|
T1 |
5 |
|
T28 |
3 |
|
T30 |
6 |
| auto[0] |
auto[1] |
100 |
1 |
|
|
T1 |
3 |
|
T28 |
4 |
|
T30 |
8 |
| auto[1] |
auto[0] |
122 |
1 |
|
|
T1 |
7 |
|
T28 |
6 |
|
T30 |
3 |
| auto[1] |
auto[1] |
121 |
1 |
|
|
T1 |
5 |
|
T28 |
7 |
|
T30 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
123 |
1 |
|
|
T1 |
4 |
|
T28 |
7 |
|
T30 |
11 |
| auto[0] |
auto[1] |
101 |
1 |
|
|
T1 |
4 |
|
T28 |
3 |
|
T30 |
2 |
| auto[1] |
auto[0] |
105 |
1 |
|
|
T1 |
5 |
|
T28 |
3 |
|
T30 |
3 |
| auto[1] |
auto[1] |
131 |
1 |
|
|
T1 |
7 |
|
T28 |
7 |
|
T30 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
123 |
1 |
|
|
T1 |
7 |
|
T28 |
4 |
|
T30 |
8 |
| auto[0] |
auto[1] |
105 |
1 |
|
|
T1 |
4 |
|
T28 |
3 |
|
T30 |
3 |
| auto[1] |
auto[0] |
101 |
1 |
|
|
T1 |
5 |
|
T28 |
3 |
|
T30 |
2 |
| auto[1] |
auto[1] |
131 |
1 |
|
|
T1 |
4 |
|
T28 |
10 |
|
T30 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
123 |
1 |
|
|
T1 |
2 |
|
T28 |
6 |
|
T30 |
4 |
| auto[0] |
auto[1] |
132 |
1 |
|
|
T1 |
7 |
|
T28 |
3 |
|
T30 |
7 |
| auto[1] |
auto[0] |
100 |
1 |
|
|
T1 |
8 |
|
T28 |
5 |
|
T30 |
6 |
| auto[1] |
auto[1] |
105 |
1 |
|
|
T1 |
3 |
|
T28 |
6 |
|
T30 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
122 |
1 |
|
|
T1 |
3 |
|
T28 |
5 |
|
T30 |
1 |
| auto[0] |
auto[1] |
127 |
1 |
|
|
T1 |
7 |
|
T28 |
6 |
|
T30 |
7 |
| auto[1] |
auto[0] |
105 |
1 |
|
|
T1 |
8 |
|
T28 |
2 |
|
T30 |
6 |
| auto[1] |
auto[1] |
106 |
1 |
|
|
T1 |
2 |
|
T28 |
7 |
|
T30 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T1 |
6 |
|
T28 |
4 |
|
T30 |
3 |
| auto[0] |
auto[1] |
122 |
1 |
|
|
T1 |
6 |
|
T28 |
10 |
|
T30 |
5 |
| auto[1] |
auto[0] |
111 |
1 |
|
|
T1 |
6 |
|
T28 |
2 |
|
T30 |
3 |
| auto[1] |
auto[1] |
124 |
1 |
|
|
T1 |
2 |
|
T28 |
4 |
|
T30 |
9 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
229 |
1 |
|
|
T1 |
13 |
|
T28 |
7 |
|
T30 |
14 |
| auto[1] |
auto[1] |
231 |
1 |
|
|
T1 |
7 |
|
T28 |
13 |
|
T30 |
6 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
113 |
1 |
|
|
T1 |
3 |
|
T28 |
6 |
|
T30 |
7 |
| auto[0] |
auto[1] |
131 |
1 |
|
|
T1 |
4 |
|
T28 |
4 |
|
T30 |
7 |
| auto[1] |
auto[0] |
114 |
1 |
|
|
T1 |
6 |
|
T28 |
5 |
|
T30 |
2 |
| auto[1] |
auto[1] |
102 |
1 |
|
|
T1 |
7 |
|
T28 |
5 |
|
T30 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
226 |
1 |
|
|
T1 |
9 |
|
T28 |
8 |
|
T30 |
6 |
| auto[1] |
auto[1] |
234 |
1 |
|
|
T1 |
11 |
|
T28 |
12 |
|
T30 |
14 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T30 |
11 |
|
T66 |
8 |
|
T216 |
8 |
| auto[1] |
83 |
1 |
|
|
T30 |
9 |
|
T66 |
12 |
|
T216 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T30 |
12 |
|
T66 |
8 |
|
T216 |
10 |
| auto[1] |
83 |
1 |
|
|
T30 |
8 |
|
T66 |
12 |
|
T216 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T30 |
11 |
|
T66 |
11 |
|
T216 |
10 |
| auto[1] |
68 |
1 |
|
|
T30 |
9 |
|
T66 |
9 |
|
T216 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T30 |
7 |
|
T66 |
12 |
|
T216 |
12 |
| auto[1] |
72 |
1 |
|
|
T30 |
13 |
|
T66 |
8 |
|
T216 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T30 |
9 |
|
T66 |
12 |
|
T216 |
9 |
| auto[1] |
77 |
1 |
|
|
T30 |
11 |
|
T66 |
8 |
|
T216 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T30 |
9 |
|
T66 |
12 |
|
T216 |
9 |
| auto[1] |
76 |
1 |
|
|
T30 |
11 |
|
T66 |
8 |
|
T216 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T30 |
9 |
|
T66 |
11 |
|
T216 |
11 |
| auto[1] |
81 |
1 |
|
|
T30 |
11 |
|
T66 |
9 |
|
T216 |
9 |