Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1460

1

T9

10

T16

11

T30

15

auto[1]

2013

1

T9

13

T11

12

T16

9

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2897

1

T9

21

T11

11

T16

19

auto[1]

576

1

T9

2

T11

1

T16

1

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3274

1

T9

22

T11

12

T16

20

auto[1]

199

1

T9

1

T30

1

T31

4

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3318

1

T9

23

T11

12

T16

18

auto[1]

155

1

T16

2

T30

4

T32

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3249

1

T9

20

T11

12

T16

16

auto[1]

224

1

T9

3

T16

4

T32

2

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2240

1

T9

4

T11

4

T16

20

auto[1]

1233

1

T9

19

T11

8

T30

30

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1513

1

T9

9

T11

3

T16

16

auto[1]

1960

1

T9

14

T11

9

T16

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1387

1

T9

7

T11

6

T16

8

auto[1]

2086

1

T9

16

T11

6

T16

12

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1385

1

T9

11

T11

4

T16

5

auto[1]

2088

1

T9

12

T11

8

T16

15

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1456

1

T9

12

T11

12

T16

6

auto[1]

2017

1

T9

11

T16

14

T30

20

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T43

3

T45

1

T66

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T9

1

T106

2

T245

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T11

1

T32

1

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T9

1

T242

3

T248

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T16

3

T41

1

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T41

1

T106

1

T184

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

48

1

T66

1

T104

1

T234

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T44

1

T83

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

69

1

T31

2

T66

2

T243

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T41

2

T43

6

T83

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T43

2

T46

1

T66

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T43

1

T83

1

T110

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T66

4

T331

1

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T41

2

T66

2

T332

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

54

1

T16

1

T66

6

T267

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

30

1

T9

2

T41

2

T242

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T16

1

T43

1

T47

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T9

1

T83

2

T158

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T11

2

T47

2

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T9

1

T44

1

T248

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T31

1

T47

1

T331

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T41

1

T242

2

T248

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T16

1

T47

1

T243

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T9

1

T44

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T16

2

T43

1

T331

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T9

1

T43

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T16

2

T83

1

T243

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T9

1

T248

1

T287

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

81

1

T243

1

T158

1

T266

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T30

1

T242

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

108

1

T16

5

T243

2

T234

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

86

1

T242

1

T105

9

T266

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T32

1

T31

3

T331

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T9

1

T242

1

T177

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T11

1

T331

1

T104

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T41

1

T333

2

T177

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

61

1

T47

1

T331

1

T234

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T30

1

T45

1

T106

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T46

1

T243

2

T104

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T30

1

T32

1

T242

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T32

2

T31

1

T66

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T9

1

T30

2

T41

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T30

1

T331

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T11

3

T106

1

T248

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T16

4

T32

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T9

1

T32

2

T258

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T243

2

T331

1

T333

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

50

1

T46

8

T248

1

T333

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T31

4

T44

1

T104

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T30

1

T41

1

T242

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T31

1

T47

2

T243

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T9

1

T158

1

T266

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

63

1

T32

1

T31

2

T47

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T9

2

T30

1

T41

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

85

1

T9

1

T31

3

T243

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

47

1

T32

5

T242

1

T236

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T31

4

T47

2

T243

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T9

1

T106

1

T259

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

79

1

T331

1

T234

1

T277

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

54

1

T11

4

T30

1

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

73

1

T47

5

T331

2

T234

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

40

1

T9

1

T83

1

T158

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

312

1

T9

3

T41

6

T44

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T248

2

T258

2

T235

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T332

1

T146

1

T334

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T245

1

T332

2

T258

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T44

1

T245

1

T335

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T41

1

T44

1

T242

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T44

1

T332

2

T235

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T83

1

T242

1

T245

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T45

1

T66

1

T245

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T41

1

T45

1

T83

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

9

1

T30

1

T44

1

T332

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T44

2

T106

1

T235

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T30

2

T41

1

T44

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T30

1

T106

1

T245

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T43

1

T242

1

T245

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T332

1

T177

1

T250

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T30

1

T335

3

T239

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T44

2

T235

2

T121

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T30

1

T44

1

T245

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T45

1

T106

1

T333

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T32

1

T41

1

T242

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T30

1

T44

1

T245

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T30

2

T44

1

T245

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T11

1

T44

1

T245

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T177

1

T110

1

T151

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T46

1

T106

1

T235

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

9

1

T30

1

T41

1

T158

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T9

1

T336

2

T332

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T44

2

T248

1

T110

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T235

2

T111

1

T172

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T30

1

T41

1

T242

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T9

1

T44

1

T106

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T158

3

T332

1

T287

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

130

1

T30

11

T44

8

T45

3

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	25	71	73.96	25
Automatically Generated Cross Bins	96	25	71	73.96	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T43

3

T45

1

T66

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T9

1

T106

2

T245

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T11

1

T32

1

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T9

1

T242

3

T245

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T16

3

T41

1

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T41

1

T44

1

T106

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T66

1

T104

2

T234

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T41

1

T44

2

T83

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T31

2

T66

2

T243

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T41

2

T43

6

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T43

2

T46

1

T66

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T43

1

T83

2

T242

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T66

4

T331

2

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

29

1

T41

2

T45

1

T66

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T16

1

T66

6

T331

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T9

2

T41

3

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T16

1

T43

1

T47

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T9

1

T30

1

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T11

2

T47

2

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T9

1

T44

3

T106

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T31

1

T47

1

T331

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T30

2

T41

2

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

58

1

T16

1

T47

1

T243

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T9

1

T30

1

T44

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T16

3

T43

1

T331

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T9

1

T43

2

T242

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T16

2

T83

1

T243

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T9

1

T248

1

T332

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

82

1

T243

1

T331

2

T158

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T30

2

T242

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

110

1

T16

5

T243

2

T234

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

95

1

T44

2

T242

1

T105

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T32

1

T31

3

T331

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T9

1

T30

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T11

1

T331

1

T104

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T41

1

T45

1

T106

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

64

1

T47

1

T331

1

T234

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T30

1

T32

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T46

1

T243

2

T104

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T30

2

T32

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T32

2

T31

1

T66

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T9

1

T30

4

T41

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T30

1

T331

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T11

4

T44

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T16

4

T32

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T9

1

T32

2

T177

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

61

1

T243

2

T331

1

T277

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

65

1

T46

9

T106

1

T248

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T31

2

T44

1

T331

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T30

2

T41

2

T242

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T31

1

T47

2

T243

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T9

2

T158

1

T266

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

68

1

T32

1

T31

2

T47

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T9

2

T30

1

T41

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

80

1

T9

1

T31

3

T243

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

56

1

T32

5

T242

1

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T31

2

T47

2

T243

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T9

1

T30

1

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

88

1

T243

1

T331

1

T234

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T9

1

T11

4

T30

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

82

1

T47

5

T331

3

T104

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

59

1

T9

1

T83

1

T158

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

196

1

T9

2

T41

6

T44

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

123

1

T30

10

T44

7

T45

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T337

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T338

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

3

1

T339

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T333

2

T339

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T339

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T338

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

27

1

T30

1

T44

1

T45

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	24	72	75.00	24
Automatically Generated Cross Bins	96	24	72	75.00	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[0]]	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T43

3

T45

1

T66

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T9

1

T106

2

T245

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T11

1

T32

1

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T9

1

T242

3

T245

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T16

2

T41

1

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T41

1

T44

1

T106

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T66

1

T104

2

T234

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T41

1

T44

2

T83

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T31

1

T66

2

T243

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T41

2

T43

6

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T43

2

T46

1

T66

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T43

1

T83

2

T242

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T66

2

T331

2

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T41

2

T45

1

T66

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T16

1

T66

2

T331

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T9

2

T41

3

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T16

1

T43

1

T47

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T9

1

T30

1

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T11

2

T47

2

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T9

1

T44

3

T106

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T31

1

T47

1

T331

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T30

2

T41

2

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

57

1

T16

1

T47

1

T243

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T9

1

T30

1

T44

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T16

3

T43

1

T331

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T9

1

T43

2

T242

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T16

2

T83

1

T243

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T9

1

T248

1

T332

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

85

1

T243

1

T331

2

T158

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T30

2

T242

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

106

1

T16

5

T243

2

T234

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

95

1

T44

2

T242

1

T105

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T32

1

T31

3

T331

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T9

1

T30

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T11

1

T331

1

T104

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T41

1

T45

1

T106

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

64

1

T47

1

T331

1

T234

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T30

1

T41

1

T45

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T46

1

T243

2

T104

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T30

2

T32

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T32

2

T31

1

T66

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T9

1

T30

4

T41

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T30

1

T331

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T11

4

T44

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T16

3

T104

1

T106

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T9

1

T32

2

T177

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T243

2

T331

1

T277

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

64

1

T46

9

T106

1

T248

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T31

4

T44

1

T331

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T30

2

T41

2

T242

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T31

1

T47

2

T243

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

47

1

T9

2

T158

1

T266

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

68

1

T32

1

T31

2

T47

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T9

2

T30

1

T41

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

87

1

T9

1

T31

3

T243

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

56

1

T32

5

T242

1

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T31

4

T47

2

T243

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T9

1

T30

1

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

88

1

T243

1

T331

1

T234

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T9

1

T11

4

T30

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

80

1

T47

5

T331

3

T104

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

58

1

T9

1

T83

1

T158

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

244

1

T9

3

T41

6

T44

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

134

1

T30

7

T44

6

T45

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T335

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T66

1

T335

1

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T340

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T32

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T341

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T342

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T343

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T30

4

T44

2

T332

6

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T43

3

T45

1

T66

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T9

1

T106

2

T245

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T11

1

T32

1

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T9

1

T242

3

T245

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T16

3

T41

1

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T41

1

T44

1

T106

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T66

1

T104

2

T234

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T41

1

T44

2

T83

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

73

1

T31

2

T66

2

T243

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T41

2

T43

6

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T43

2

T46

1

T66

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T43

1

T83

2

T242

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T66

4

T331

2

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

29

1

T41

2

T45

1

T66

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T16

1

T66

6

T331

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T9

2

T41

3

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T16

1

T43

1

T47

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T9

1

T30

1

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T11

2

T47

2

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T9

1

T44

3

T106

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T31

1

T47

1

T331

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T30

2

T41

2

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

60

1

T16

1

T47

1

T243

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T9

1

T30

1

T44

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T16

2

T43

1

T331

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T9

1

T43

2

T242

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T16

2

T83

1

T243

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T9

1

T248

1

T332

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

86

1

T243

1

T331

2

T158

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T30

2

T242

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

104

1

T16

2

T243

2

T234

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

95

1

T44

2

T242

1

T105

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T32

1

T31

3

T331

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T9

1

T30

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T11

1

T331

1

T104

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T41

1

T45

1

T106

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T47

1

T331

1

T234

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T30

1

T41

1

T45

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T46

1

T243

2

T104

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T30

2

T32

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T32

2

T31

1

T66

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T9

1

T30

4

T41

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T30

1

T331

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T11

4

T44

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T16

4

T104

1

T106

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T9

1

T32

2

T177

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T243

2

T331

1

T277

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

65

1

T46

9

T106

1

T248

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T31

4

T44

1

T331

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T30

2

T41

2

T242

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T31

1

T47

2

T243

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T9

2

T158

1

T266

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

66

1

T32

1

T31

2

T47

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T9

2

T30

1

T41

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

81

1

T9

1

T31

3

T243

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

56

1

T32

5

T242

1

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T31

4

T47

2

T243

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T9

1

T30

1

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

86

1

T243

1

T331

1

T234

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T9

1

T11

4

T30

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

80

1

T47

5

T331

3

T104

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

59

1

T9

1

T83

1

T158

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

176

1

T44

4

T83

1

T36

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

126

1

T30

11

T44

8

T83

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T337

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T32

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T336

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

24

1

T45

3

T245

1

T235

1

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded