Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
777 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T57 |
13 |
| auto[1] |
803 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T57 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
779 |
1 |
|
|
T21 |
13 |
|
T22 |
10 |
|
T57 |
9 |
| auto[1] |
801 |
1 |
|
|
T21 |
7 |
|
T22 |
10 |
|
T57 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
758 |
1 |
|
|
T21 |
10 |
|
T22 |
7 |
|
T57 |
9 |
| auto[1] |
822 |
1 |
|
|
T21 |
10 |
|
T22 |
13 |
|
T57 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
768 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T57 |
12 |
| auto[1] |
812 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T57 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
794 |
1 |
|
|
T21 |
12 |
|
T22 |
7 |
|
T57 |
9 |
| auto[1] |
786 |
1 |
|
|
T21 |
8 |
|
T22 |
13 |
|
T57 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
778 |
1 |
|
|
T21 |
10 |
|
T22 |
9 |
|
T57 |
8 |
| auto[1] |
802 |
1 |
|
|
T21 |
10 |
|
T22 |
11 |
|
T57 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T21 |
6 |
|
T22 |
9 |
|
T57 |
13 |
| auto[1] |
762 |
1 |
|
|
T21 |
14 |
|
T22 |
11 |
|
T57 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T57 |
12 |
| auto[1] |
782 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T57 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T21 |
9 |
|
T22 |
9 |
|
T57 |
10 |
| auto[1] |
772 |
1 |
|
|
T21 |
11 |
|
T22 |
11 |
|
T57 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
776 |
1 |
|
|
T21 |
11 |
|
T22 |
8 |
|
T57 |
12 |
| auto[1] |
804 |
1 |
|
|
T21 |
9 |
|
T22 |
12 |
|
T57 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T21 |
14 |
|
T22 |
7 |
|
T57 |
14 |
| auto[1] |
727 |
1 |
|
|
T21 |
6 |
|
T22 |
13 |
|
T57 |
6 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
803 |
1 |
|
|
T21 |
11 |
|
T22 |
13 |
|
T57 |
11 |
| auto[1] |
777 |
1 |
|
|
T21 |
9 |
|
T22 |
7 |
|
T57 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
792 |
1 |
|
|
T21 |
14 |
|
T22 |
8 |
|
T57 |
8 |
| auto[1] |
788 |
1 |
|
|
T21 |
6 |
|
T22 |
12 |
|
T57 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
779 |
1 |
|
|
T21 |
13 |
|
T22 |
10 |
|
T57 |
9 |
| auto[1] |
801 |
1 |
|
|
T21 |
7 |
|
T22 |
10 |
|
T57 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
793 |
1 |
|
|
T21 |
11 |
|
T22 |
13 |
|
T57 |
10 |
| auto[1] |
787 |
1 |
|
|
T21 |
9 |
|
T22 |
7 |
|
T57 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
789 |
1 |
|
|
T21 |
11 |
|
T22 |
10 |
|
T57 |
13 |
| auto[1] |
791 |
1 |
|
|
T21 |
9 |
|
T22 |
10 |
|
T57 |
7 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T21 |
10 |
|
T22 |
13 |
|
T57 |
11 |
| auto[1] |
749 |
1 |
|
|
T21 |
10 |
|
T22 |
7 |
|
T57 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
783 |
1 |
|
|
T21 |
12 |
|
T22 |
13 |
|
T57 |
12 |
| auto[1] |
797 |
1 |
|
|
T21 |
8 |
|
T22 |
7 |
|
T57 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
786 |
1 |
|
|
T21 |
8 |
|
T22 |
13 |
|
T57 |
9 |
| auto[1] |
794 |
1 |
|
|
T21 |
12 |
|
T22 |
7 |
|
T57 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
804 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T57 |
8 |
| auto[1] |
776 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T57 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
791 |
1 |
|
|
T21 |
9 |
|
T22 |
9 |
|
T57 |
13 |
| auto[1] |
789 |
1 |
|
|
T21 |
11 |
|
T22 |
11 |
|
T57 |
7 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
777 |
1 |
|
|
T21 |
8 |
|
T22 |
10 |
|
T57 |
11 |
| auto[1] |
803 |
1 |
|
|
T21 |
12 |
|
T22 |
10 |
|
T57 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
810 |
1 |
|
|
T21 |
9 |
|
T22 |
13 |
|
T57 |
11 |
| auto[1] |
770 |
1 |
|
|
T21 |
11 |
|
T22 |
7 |
|
T57 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
803 |
1 |
|
|
T21 |
11 |
|
T22 |
13 |
|
T57 |
11 |
| auto[1] |
777 |
1 |
|
|
T21 |
9 |
|
T22 |
7 |
|
T57 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
382 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T57 |
6 |
| auto[0] |
auto[1] |
411 |
1 |
|
|
T21 |
7 |
|
T22 |
8 |
|
T57 |
4 |
| auto[1] |
auto[0] |
376 |
1 |
|
|
T21 |
6 |
|
T22 |
2 |
|
T57 |
3 |
| auto[1] |
auto[1] |
411 |
1 |
|
|
T21 |
3 |
|
T22 |
5 |
|
T57 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
385 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T57 |
9 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T21 |
7 |
|
T22 |
5 |
|
T57 |
4 |
| auto[1] |
auto[0] |
383 |
1 |
|
|
T21 |
6 |
|
T22 |
5 |
|
T57 |
3 |
| auto[1] |
auto[1] |
408 |
1 |
|
|
T21 |
3 |
|
T22 |
5 |
|
T57 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T21 |
7 |
|
T22 |
4 |
|
T57 |
4 |
| auto[0] |
auto[1] |
406 |
1 |
|
|
T21 |
3 |
|
T22 |
9 |
|
T57 |
7 |
| auto[1] |
auto[0] |
369 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T57 |
5 |
| auto[1] |
auto[1] |
380 |
1 |
|
|
T21 |
5 |
|
T22 |
4 |
|
T57 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
393 |
1 |
|
|
T21 |
7 |
|
T22 |
5 |
|
T57 |
4 |
| auto[0] |
auto[1] |
390 |
1 |
|
|
T21 |
5 |
|
T22 |
8 |
|
T57 |
8 |
| auto[1] |
auto[0] |
385 |
1 |
|
|
T21 |
3 |
|
T22 |
4 |
|
T57 |
4 |
| auto[1] |
auto[1] |
412 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T57 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
408 |
1 |
|
|
T21 |
4 |
|
T22 |
7 |
|
T57 |
7 |
| auto[0] |
auto[1] |
378 |
1 |
|
|
T21 |
4 |
|
T22 |
6 |
|
T57 |
2 |
| auto[1] |
auto[0] |
410 |
1 |
|
|
T21 |
2 |
|
T22 |
2 |
|
T57 |
6 |
| auto[1] |
auto[1] |
384 |
1 |
|
|
T21 |
10 |
|
T22 |
5 |
|
T57 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
407 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T57 |
6 |
| auto[0] |
auto[1] |
397 |
1 |
|
|
T21 |
3 |
|
T22 |
4 |
|
T57 |
2 |
| auto[1] |
auto[0] |
391 |
1 |
|
|
T21 |
3 |
|
T22 |
4 |
|
T57 |
6 |
| auto[1] |
auto[1] |
385 |
1 |
|
|
T21 |
8 |
|
T22 |
8 |
|
T57 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
385 |
1 |
|
|
T21 |
6 |
|
T22 |
3 |
|
T57 |
6 |
| auto[0] |
auto[1] |
392 |
1 |
|
|
T21 |
2 |
|
T22 |
7 |
|
T57 |
5 |
| auto[1] |
auto[0] |
391 |
1 |
|
|
T21 |
5 |
|
T22 |
5 |
|
T57 |
6 |
| auto[1] |
auto[1] |
412 |
1 |
|
|
T21 |
7 |
|
T22 |
5 |
|
T57 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
440 |
1 |
|
|
T21 |
8 |
|
T22 |
4 |
|
T57 |
7 |
| auto[0] |
auto[1] |
370 |
1 |
|
|
T21 |
1 |
|
T22 |
9 |
|
T57 |
4 |
| auto[1] |
auto[0] |
413 |
1 |
|
|
T21 |
6 |
|
T22 |
3 |
|
T57 |
7 |
| auto[1] |
auto[1] |
357 |
1 |
|
|
T21 |
5 |
|
T22 |
4 |
|
T57 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
399 |
1 |
|
|
T21 |
7 |
|
T22 |
2 |
|
T57 |
3 |
| auto[0] |
auto[1] |
393 |
1 |
|
|
T21 |
7 |
|
T22 |
6 |
|
T57 |
5 |
| auto[1] |
auto[0] |
378 |
1 |
|
|
T21 |
3 |
|
T22 |
8 |
|
T57 |
10 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T21 |
3 |
|
T22 |
4 |
|
T57 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
779 |
1 |
|
|
T21 |
13 |
|
T22 |
10 |
|
T57 |
9 |
| auto[1] |
auto[1] |
801 |
1 |
|
|
T21 |
7 |
|
T22 |
10 |
|
T57 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
400 |
1 |
|
|
T21 |
5 |
|
T22 |
5 |
|
T57 |
7 |
| auto[0] |
auto[1] |
391 |
1 |
|
|
T21 |
4 |
|
T22 |
4 |
|
T57 |
6 |
| auto[1] |
auto[0] |
408 |
1 |
|
|
T21 |
4 |
|
T22 |
4 |
|
T57 |
3 |
| auto[1] |
auto[1] |
381 |
1 |
|
|
T21 |
7 |
|
T22 |
7 |
|
T57 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
803 |
1 |
|
|
T21 |
11 |
|
T22 |
13 |
|
T57 |
11 |
| auto[1] |
auto[1] |
777 |
1 |
|
|
T21 |
9 |
|
T22 |
7 |
|
T57 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T6 |
12 |
|
T22 |
11 |
|
T35 |
11 |
| auto[1] |
131 |
1 |
|
|
T6 |
8 |
|
T22 |
9 |
|
T35 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T6 |
11 |
|
T22 |
9 |
|
T35 |
8 |
| auto[1] |
133 |
1 |
|
|
T6 |
9 |
|
T22 |
11 |
|
T35 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T6 |
14 |
|
T22 |
8 |
|
T35 |
14 |
| auto[1] |
114 |
1 |
|
|
T6 |
6 |
|
T22 |
12 |
|
T35 |
6 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T6 |
9 |
|
T22 |
11 |
|
T35 |
11 |
| auto[1] |
132 |
1 |
|
|
T6 |
11 |
|
T22 |
9 |
|
T35 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T6 |
6 |
|
T22 |
10 |
|
T35 |
5 |
| auto[1] |
152 |
1 |
|
|
T6 |
14 |
|
T22 |
10 |
|
T35 |
15 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T6 |
9 |
|
T22 |
9 |
|
T35 |
9 |
| auto[1] |
134 |
1 |
|
|
T6 |
11 |
|
T22 |
11 |
|
T35 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T6 |
8 |
|
T22 |
11 |
|
T35 |
8 |
| auto[1] |
133 |
1 |
|
|
T6 |
12 |
|
T22 |
9 |
|
T35 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T6 |
15 |
|
T22 |
12 |
|
T35 |
9 |
| auto[1] |
113 |
1 |
|
|
T6 |
5 |
|
T22 |
8 |
|
T35 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T6 |
14 |
|
T22 |
10 |
|
T35 |
12 |
| auto[1] |
129 |
1 |
|
|
T6 |
6 |
|
T22 |
10 |
|
T35 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T6 |
8 |
|
T22 |
10 |
|
T35 |
6 |
| auto[1] |
131 |
1 |
|
|
T6 |
12 |
|
T22 |
10 |
|
T35 |
14 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T6 |
10 |
|
T22 |
7 |
|
T35 |
7 |
| auto[1] |
135 |
1 |
|
|
T6 |
10 |
|
T22 |
13 |
|
T35 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T6 |
13 |
|
T22 |
10 |
|
T35 |
10 |
| auto[1] |
116 |
1 |
|
|
T6 |
7 |
|
T22 |
10 |
|
T35 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T6 |
5 |
|
T22 |
11 |
|
T35 |
11 |
| auto[1] |
134 |
1 |
|
|
T6 |
15 |
|
T22 |
9 |
|
T35 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T6 |
11 |
|
T22 |
9 |
|
T35 |
8 |
| auto[1] |
133 |
1 |
|
|
T6 |
9 |
|
T22 |
11 |
|
T35 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T6 |
10 |
|
T22 |
10 |
|
T35 |
14 |
| auto[1] |
128 |
1 |
|
|
T6 |
10 |
|
T22 |
10 |
|
T35 |
6 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T6 |
9 |
|
T22 |
9 |
|
T35 |
7 |
| auto[1] |
138 |
1 |
|
|
T6 |
11 |
|
T22 |
11 |
|
T35 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T6 |
11 |
|
T22 |
12 |
|
T35 |
10 |
| auto[1] |
129 |
1 |
|
|
T6 |
9 |
|
T22 |
8 |
|
T35 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T6 |
10 |
|
T22 |
9 |
|
T35 |
6 |
| auto[1] |
135 |
1 |
|
|
T6 |
10 |
|
T22 |
11 |
|
T35 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T6 |
6 |
|
T22 |
7 |
|
T35 |
6 |
| auto[1] |
143 |
1 |
|
|
T6 |
14 |
|
T22 |
13 |
|
T35 |
14 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T6 |
11 |
|
T22 |
12 |
|
T35 |
9 |
| auto[1] |
139 |
1 |
|
|
T6 |
9 |
|
T22 |
8 |
|
T35 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T6 |
5 |
|
T22 |
10 |
|
T35 |
8 |
| auto[1] |
146 |
1 |
|
|
T6 |
15 |
|
T22 |
10 |
|
T35 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T6 |
14 |
|
T22 |
9 |
|
T35 |
8 |
| auto[1] |
125 |
1 |
|
|
T6 |
6 |
|
T22 |
11 |
|
T35 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T6 |
10 |
|
T22 |
10 |
|
T35 |
13 |
| auto[1] |
121 |
1 |
|
|
T6 |
10 |
|
T22 |
10 |
|
T35 |
7 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T6 |
13 |
|
T22 |
10 |
|
T35 |
10 |
| auto[1] |
116 |
1 |
|
|
T6 |
7 |
|
T22 |
10 |
|
T35 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T6 |
6 |
|
T22 |
3 |
|
T35 |
9 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T6 |
4 |
|
T22 |
7 |
|
T35 |
5 |
| auto[1] |
auto[0] |
70 |
1 |
|
|
T6 |
8 |
|
T22 |
5 |
|
T35 |
5 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T6 |
2 |
|
T22 |
5 |
|
T35 |
1 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T6 |
3 |
|
T22 |
4 |
|
T35 |
4 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T6 |
6 |
|
T22 |
5 |
|
T35 |
3 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T6 |
6 |
|
T22 |
7 |
|
T35 |
7 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T6 |
5 |
|
T22 |
4 |
|
T35 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
54 |
1 |
|
|
T6 |
5 |
|
T22 |
5 |
|
T35 |
1 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T6 |
6 |
|
T22 |
7 |
|
T35 |
9 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T6 |
1 |
|
T22 |
5 |
|
T35 |
4 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T6 |
8 |
|
T22 |
3 |
|
T35 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T6 |
6 |
|
T22 |
3 |
|
T35 |
1 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T6 |
4 |
|
T22 |
6 |
|
T35 |
5 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T6 |
3 |
|
T22 |
6 |
|
T35 |
8 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T6 |
7 |
|
T22 |
5 |
|
T35 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T6 |
5 |
|
T22 |
5 |
|
T35 |
1 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T6 |
1 |
|
T22 |
2 |
|
T35 |
5 |
| auto[1] |
auto[0] |
68 |
1 |
|
|
T6 |
3 |
|
T22 |
6 |
|
T35 |
7 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T6 |
11 |
|
T22 |
7 |
|
T35 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T6 |
11 |
|
T22 |
8 |
|
T35 |
3 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T22 |
4 |
|
T35 |
6 |
|
T93 |
2 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T6 |
4 |
|
T22 |
4 |
|
T35 |
6 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T6 |
5 |
|
T22 |
4 |
|
T35 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T6 |
5 |
|
T22 |
6 |
|
T35 |
4 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T6 |
9 |
|
T22 |
3 |
|
T35 |
4 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T6 |
3 |
|
T22 |
4 |
|
T35 |
2 |
| auto[1] |
auto[1] |
65 |
1 |
|
|
T6 |
3 |
|
T22 |
7 |
|
T35 |
10 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T6 |
4 |
|
T22 |
5 |
|
T35 |
7 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T6 |
6 |
|
T22 |
5 |
|
T35 |
6 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T6 |
6 |
|
T22 |
2 |
|
T93 |
3 |
| auto[1] |
auto[1] |
65 |
1 |
|
|
T6 |
4 |
|
T22 |
8 |
|
T35 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T6 |
3 |
|
T22 |
6 |
|
T35 |
6 |
| auto[0] |
auto[1] |
64 |
1 |
|
|
T6 |
2 |
|
T22 |
5 |
|
T35 |
5 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T6 |
9 |
|
T22 |
5 |
|
T35 |
5 |
| auto[1] |
auto[1] |
67 |
1 |
|
|
T6 |
6 |
|
T22 |
4 |
|
T35 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
127 |
1 |
|
|
T6 |
11 |
|
T22 |
9 |
|
T35 |
8 |
| auto[1] |
auto[1] |
133 |
1 |
|
|
T6 |
9 |
|
T22 |
11 |
|
T35 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
55 |
1 |
|
|
T6 |
3 |
|
T22 |
5 |
|
T35 |
5 |
| auto[0] |
auto[1] |
59 |
1 |
|
|
T6 |
2 |
|
T22 |
5 |
|
T35 |
3 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T6 |
11 |
|
T22 |
5 |
|
T35 |
7 |
| auto[1] |
auto[1] |
70 |
1 |
|
|
T6 |
4 |
|
T22 |
5 |
|
T35 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
144 |
1 |
|
|
T6 |
13 |
|
T22 |
10 |
|
T35 |
10 |
| auto[1] |
auto[1] |
116 |
1 |
|
|
T6 |
7 |
|
T22 |
10 |
|
T35 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73 |
1 |
|
|
T6 |
13 |
|
T35 |
10 |
|
T183 |
7 |
| auto[1] |
87 |
1 |
|
|
T6 |
7 |
|
T35 |
10 |
|
T183 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T6 |
8 |
|
T35 |
7 |
|
T183 |
10 |
| auto[1] |
83 |
1 |
|
|
T6 |
12 |
|
T35 |
13 |
|
T183 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T6 |
8 |
|
T35 |
8 |
|
T183 |
9 |
| auto[1] |
84 |
1 |
|
|
T6 |
12 |
|
T35 |
12 |
|
T183 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T6 |
10 |
|
T35 |
10 |
|
T183 |
12 |
| auto[1] |
75 |
1 |
|
|
T6 |
10 |
|
T35 |
10 |
|
T183 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T6 |
11 |
|
T35 |
9 |
|
T183 |
10 |
| auto[1] |
77 |
1 |
|
|
T6 |
9 |
|
T35 |
11 |
|
T183 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T6 |
9 |
|
T35 |
11 |
|
T183 |
5 |
| auto[1] |
82 |
1 |
|
|
T6 |
11 |
|
T35 |
9 |
|
T183 |
15 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T6 |
10 |
|
T35 |
8 |
|
T183 |
8 |
| auto[1] |
86 |
1 |
|
|
T6 |
10 |
|
T35 |
12 |
|
T183 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T6 |
7 |
|
T35 |
14 |
|
T183 |
9 |
| auto[1] |
76 |
1 |
|
|
T6 |
13 |
|
T35 |
6 |
|
T183 |
11 |