Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.06	99.48	96.51	100.00	99.36	98.93	99.90	92.25

Total tests in report: 914

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
61.34	61.34	79.14	79.14	68.12	68.12	92.01	92.01	20.51	20.51	79.56	79.56	69.27	69.27	20.78	20.78	/workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1646147381
80.28	18.94	93.25	14.11	86.93	18.81	95.66	3.65	53.85	33.33	93.35	13.79	85.36	16.09	53.61	32.83	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4064898702
85.22	4.94	95.52	2.28	89.38	2.45	96.12	0.46	70.51	16.67	95.53	2.18	90.46	5.11	59.04	5.44	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2104214396
88.16	2.94	97.05	1.53	91.35	1.97	96.12	0.00	85.26	14.74	96.97	1.44	91.14	0.67	59.26	0.22	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.95106417
90.37	2.21	97.80	0.75	92.11	0.76	97.03	0.91	85.26	0.00	97.19	0.22	94.70	3.56	68.51	9.26	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2764753003
91.66	1.29	97.87	0.07	93.28	1.16	97.72	0.68	85.26	0.00	97.30	0.11	94.80	0.10	75.40	6.89	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1803310991
92.70	1.04	98.23	0.35	93.71	0.43	97.72	0.00	89.10	3.85	97.71	0.41	96.15	1.35	76.26	0.86	/workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1317941315
93.61	0.91	98.23	0.00	93.73	0.03	97.72	0.00	89.10	0.00	97.74	0.04	96.24	0.10	82.51	6.24	/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.4020431232
94.44	0.83	98.69	0.47	94.21	0.48	97.72	0.00	92.31	3.21	98.08	0.33	97.59	1.35	82.51	0.00	/workspace/coverage/default/20.sysrst_ctrl_edge_detect.3325779758
94.85	0.41	98.79	0.09	94.31	0.10	98.17	0.46	93.59	1.28	98.19	0.11	97.98	0.39	82.94	0.43	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2900909689
95.22	0.37	98.92	0.13	94.39	0.08	98.17	0.00	95.51	1.92	98.34	0.15	98.27	0.29	82.94	0.00	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.4022439755
95.58	0.36	99.03	0.11	94.46	0.08	98.17	0.00	97.44	1.92	98.45	0.11	98.55	0.29	82.94	0.00	/workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3292153074
95.87	0.29	99.07	0.04	94.46	0.00	98.17	0.00	97.44	0.00	98.45	0.00	98.55	0.00	84.93	1.99	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1146805070
96.15	0.28	99.07	0.00	94.49	0.03	99.77	1.60	97.44	0.00	98.45	0.00	98.65	0.10	85.20	0.27	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.349087872
96.32	0.17	99.09	0.02	94.49	0.00	99.77	0.00	97.44	0.00	98.45	0.00	98.65	0.00	86.38	1.18	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3688956011
96.48	0.16	99.14	0.06	94.59	0.10	99.77	0.00	98.08	0.64	98.52	0.07	98.75	0.10	86.54	0.16	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2235430359
96.64	0.16	99.14	0.00	94.72	0.13	99.77	0.00	98.08	0.00	98.52	0.00	99.52	0.77	86.76	0.22	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3625081127
96.78	0.14	99.14	0.00	94.72	0.00	99.77	0.00	98.08	0.00	98.52	0.00	99.52	0.00	87.73	0.97	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.1993854507
96.92	0.14	99.22	0.07	94.74	0.03	99.77	0.00	98.72	0.64	98.63	0.11	99.61	0.10	87.73	0.00	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.4278035547
97.04	0.13	99.25	0.04	94.77	0.03	99.77	0.00	99.36	0.64	98.67	0.04	99.71	0.10	87.78	0.05	/workspace/coverage/default/28.sysrst_ctrl_stress_all.3360921171
97.16	0.12	99.25	0.00	95.55	0.78	99.77	0.00	99.36	0.00	98.67	0.00	99.71	0.00	87.84	0.05	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1004801419
97.27	0.10	99.29	0.04	95.60	0.05	99.77	0.00	99.36	0.00	98.67	0.00	99.71	0.00	88.48	0.65	/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1826212231
97.35	0.08	99.29	0.00	95.65	0.05	99.77	0.00	99.36	0.00	98.67	0.00	99.90	0.19	88.81	0.32	/workspace/coverage/default/29.sysrst_ctrl_stress_all.2838652466
97.41	0.06	99.29	0.00	95.65	0.00	99.77	0.00	99.36	0.00	98.67	0.00	99.90	0.00	89.24	0.43	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3486235524
97.47	0.06	99.29	0.00	95.65	0.00	99.77	0.00	99.36	0.00	98.67	0.00	99.90	0.00	89.67	0.43	/workspace/coverage/default/6.sysrst_ctrl_stress_all.1527662131
97.53	0.06	99.33	0.04	95.75	0.10	99.77	0.00	99.36	0.00	98.74	0.07	99.90	0.00	89.88	0.22	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3055397624
97.59	0.05	99.38	0.06	95.83	0.08	100.00	0.23	99.36	0.00	98.74	0.00	99.90	0.00	89.88	0.00	/workspace/coverage/default/16.sysrst_ctrl_alert_test.1508444582
97.64	0.05	99.40	0.02	95.85	0.03	100.00	0.00	99.36	0.00	98.78	0.04	99.90	0.00	90.15	0.27	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2329516080
97.68	0.04	99.40	0.00	96.16	0.30	100.00	0.00	99.36	0.00	98.78	0.00	99.90	0.00	90.15	0.00	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3833047614
97.71	0.03	99.40	0.00	96.16	0.00	100.00	0.00	99.36	0.00	98.78	0.00	99.90	0.00	90.37	0.22	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3246202438
97.74	0.03	99.40	0.00	96.16	0.00	100.00	0.00	99.36	0.00	98.78	0.00	99.90	0.00	90.58	0.22	/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1429039254
97.77	0.03	99.40	0.00	96.33	0.18	100.00	0.00	99.36	0.00	98.78	0.00	99.90	0.00	90.58	0.00	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.144796078
97.79	0.02	99.40	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.78	0.00	99.90	0.00	90.74	0.16	/workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.451364920
97.81	0.02	99.40	0.00	96.36	0.03	100.00	0.00	99.36	0.00	98.78	0.00	99.90	0.00	90.85	0.11	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2760111551
97.82	0.02	99.44	0.04	96.36	0.00	100.00	0.00	99.36	0.00	98.85	0.07	99.90	0.00	90.85	0.00	/workspace/coverage/default/29.sysrst_ctrl_edge_detect.3311637064
97.84	0.02	99.44	0.00	96.36	0.00	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	90.96	0.11	/workspace/coverage/default/11.sysrst_ctrl_stress_all.4265099550
97.85	0.02	99.44	0.00	96.36	0.00	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	91.07	0.11	/workspace/coverage/default/18.sysrst_ctrl_combo_detect.1289172858
97.87	0.02	99.44	0.00	96.36	0.00	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	91.17	0.11	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1857921333
97.89	0.02	99.44	0.00	96.36	0.00	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	91.28	0.11	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3729519691
97.90	0.02	99.44	0.00	96.36	0.00	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	91.39	0.11	/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2868574056
97.92	0.02	99.44	0.00	96.36	0.00	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	91.50	0.11	/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2770611146
97.93	0.01	99.44	0.00	96.39	0.03	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	91.55	0.05	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2090026035
97.94	0.01	99.44	0.00	96.41	0.03	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	91.60	0.05	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.595695397
97.95	0.01	99.44	0.00	96.44	0.03	100.00	0.00	99.36	0.00	98.85	0.00	99.90	0.00	91.66	0.05	/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1223573379
97.96	0.01	99.46	0.02	96.44	0.00	100.00	0.00	99.36	0.00	98.89	0.04	99.90	0.00	91.66	0.00	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.3739417048
97.97	0.01	99.48	0.02	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.04	99.90	0.00	91.66	0.00	/workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1646302782
97.97	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	91.71	0.05	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4151782194
97.98	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	91.77	0.05	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.753396059
97.99	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	91.82	0.05	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1929976449
98.00	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	91.87	0.05	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2459795396
98.00	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	91.93	0.05	/workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.62817496
98.01	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	91.98	0.05	/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1713927023
98.02	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.03	0.05	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2016737208
98.03	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.09	0.05	/workspace/coverage/default/39.sysrst_ctrl_combo_detect.1579949954
98.04	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.14	0.05	/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.489197148
98.04	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.20	0.05	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.224117594
98.05	0.01	99.48	0.00	96.44	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.25	0.05	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.21546226
98.06	0.01	99.48	0.00	96.49	0.05	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.25	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.721003158

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2494950743
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1741243125
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1308071023
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2814111049
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2757177282
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2694390472
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2042701954
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4066419473
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.313426400
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1782138476
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1751855361
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.859753898
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4285117620
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2129652130
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2114955653
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.81206382
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1118517861
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1387198963
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.636419658
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.384136108
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3352744000
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.342851385
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1090955613
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2242078786
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2274093595
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.103392743
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2254900899
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2478733638
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.517845480
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2131878800
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2292096251
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2106981284
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3314101194
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.881689135
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3641723238
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1769519515
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1769483396
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3259021634
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.358890513
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.4239123102
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3810523562
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1762187500
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1924809115
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2893098795
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1970169512
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.233703098
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2154094979
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1857516837
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1212695308
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1742467356
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1771030308
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1782275895
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1174785175
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2836110111
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2180595095
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2849683924
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2294375003
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.155413772
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2945498682
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1291090802
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3577773843
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2900210706
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.822178825
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2369766133
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.390259742
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2049537576
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3900457905
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2362242007
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1607295142
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2790305890
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4219160897
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2167811428
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3131972442
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.4091570630
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.391203390
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/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.506009804
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.4214476054
/workspace/coverage/default/41.sysrst_ctrl_alert_test.1504220774
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2862644746
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.767734970
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.509190457
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3674761405
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2704743850
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.415392123
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2717368407
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.987614566
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.4197528305
/workspace/coverage/default/41.sysrst_ctrl_smoke.1788625227
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2209756799
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3801582292
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2496654607
/workspace/coverage/default/42.sysrst_ctrl_alert_test.749492081
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3707977841
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2394178765
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.557010198
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.174557283
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.1932487405
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.4120742631
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.747583601
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3848669000
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3838149367
/workspace/coverage/default/42.sysrst_ctrl_smoke.3008980016
/workspace/coverage/default/42.sysrst_ctrl_stress_all.2099014659
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.493411072
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.458111526
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2234751183
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1461532749
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3394549194
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3108068713
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.423064800
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.83170640
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3833772176
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3822459311
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1531045905
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3106203138
/workspace/coverage/default/43.sysrst_ctrl_smoke.2943116521
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2615010633
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.826705290
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1042804550
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3190665747
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1475745205
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3481570063
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3202730336
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4263671899
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1168426935
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2989410712
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2223279881
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1770112366
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.4049191515
/workspace/coverage/default/44.sysrst_ctrl_smoke.442351555
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2974937194
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3189448369
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.408974147
/workspace/coverage/default/45.sysrst_ctrl_alert_test.708289146
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.18987806
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3484687445
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2913396922
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3773869302
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2609708750
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4023644730
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.210122880
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1516613121
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1885079521
/workspace/coverage/default/45.sysrst_ctrl_smoke.2959054555
/workspace/coverage/default/45.sysrst_ctrl_stress_all.4101169059
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3999254225
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3924704467
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1123128843
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.4284052315
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2732951928
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2396865850
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3700556534
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.448358823
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1834167029
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2749338935
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.476938443
/workspace/coverage/default/46.sysrst_ctrl_smoke.3402730791
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3464402983
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2574327872
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2564287074
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2174841575
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.883117673
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.676159306
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.516122907
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.146406893
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.162382919
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.236616356
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1543430403
/workspace/coverage/default/47.sysrst_ctrl_smoke.2921209493
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1790930495
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.860339842
/workspace/coverage/default/48.sysrst_ctrl_alert_test.496916376
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3335639770
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3144042721
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4127696550
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1857283822
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2192703844
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2476605265
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2520473838
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3956841326
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3464915298
/workspace/coverage/default/48.sysrst_ctrl_smoke.1940455763
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3638917553
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3089018700
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3607773656
/workspace/coverage/default/49.sysrst_ctrl_alert_test.2602710168
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1928348771
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1159396918
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3813117095
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2166767542
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3119453121
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.770569531
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.707705208
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2643167022
/workspace/coverage/default/49.sysrst_ctrl_smoke.2997545580
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2207594121
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.263216095
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2414413992
/workspace/coverage/default/5.sysrst_ctrl_alert_test.2387276739
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3806823921
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.337830888
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3034276507
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3193580417
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1847898236
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2911350788
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3887585106
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.505798605
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2006557177
/workspace/coverage/default/5.sysrst_ctrl_smoke.3403902220
/workspace/coverage/default/5.sysrst_ctrl_stress_all.575026332
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1069680680
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1608430558
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.111800148
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.136432677
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2312368035
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.740458084
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.46588538
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.937369843
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1298528958
/workspace/coverage/default/6.sysrst_ctrl_alert_test.649561359
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.321056069
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1772749315
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.361254821
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.239156144
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.3342061218
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2800580725
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1106388247
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1450777107
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3459503272
/workspace/coverage/default/6.sysrst_ctrl_smoke.20290597
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.4187445977
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.804895926
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1501681986
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1461040833
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1454982991
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1641797644
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3175136154
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1069046245
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.621302838
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3105612351
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2879838529
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.880543743
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2941525906
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1257048808
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3875972642
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.4124685591
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3542236693
/workspace/coverage/default/7.sysrst_ctrl_smoke.299281611
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2273370133
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.834395509
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2609253648
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2073539627
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2561622331
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3445191006
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3628928926
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.684027113
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2620320630
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3905609791
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1485555460
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2424384539
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3772309395
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4012069959
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3368327779
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2937185171
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1823947210
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3596347558
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3633206268
/workspace/coverage/default/8.sysrst_ctrl_smoke.3678570969
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2244786462
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2475534496
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3891839252
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.4161465891
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2106912466
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2712159618
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3105335941
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2073592835
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1918993899
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3857064006
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2924888202
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1022672813
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2711764947
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.802893029
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.897664109
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.57938552
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2169530220
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3328685329
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.4148983209
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3746181759
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2688034670
/workspace/coverage/default/9.sysrst_ctrl_smoke.3270703302
/workspace/coverage/default/9.sysrst_ctrl_stress_all.4025953289
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1200184588
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2680734559
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1894153764
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1749031474
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1708397073
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.661654540
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3629139390
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2969655738
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1311032834

Total test records in report: 914

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1092763974	May 05 02:48:45 PM PDT 24	May 05 02:48:50 PM PDT 24	2546100340 ps
T2	/workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1646147381	May 05 02:49:01 PM PDT 24	May 05 02:55:27 PM PDT 24	151525665584 ps
T3	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.2794778289	May 05 02:49:52 PM PDT 24	May 05 02:52:44 PM PDT 24	62215685992 ps
T11	/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1123128843	May 05 02:50:44 PM PDT 24	May 05 02:50:47 PM PDT 24	3477895570 ps
T12	/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.8960452	May 05 02:49:51 PM PDT 24	May 05 02:51:54 PM PDT 24	90086865102 ps
T13	/workspace/coverage/default/22.sysrst_ctrl_pin_access_test.641118334	May 05 02:49:37 PM PDT 24	May 05 02:49:41 PM PDT 24	2103578901 ps
T14	/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3248790376	May 05 02:49:43 PM PDT 24	May 05 02:49:49 PM PDT 24	2969432166 ps
T15	/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3629139390	May 05 02:51:14 PM PDT 24	May 05 02:51:20 PM PDT 24	25706376641 ps
T4	/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2414413992	May 05 02:51:06 PM PDT 24	May 05 02:51:17 PM PDT 24	198137448287 ps
T5	/workspace/coverage/default/20.sysrst_ctrl_edge_detect.3325779758	May 05 02:49:29 PM PDT 24	May 05 02:49:38 PM PDT 24	3306123781 ps
T6	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2764753003	May 05 02:50:30 PM PDT 24	May 05 02:54:33 PM PDT 24	357865940209 ps
T23	/workspace/coverage/default/46.sysrst_ctrl_stress_all.3464402983	May 05 02:50:47 PM PDT 24	May 05 02:51:00 PM PDT 24	13129553931 ps
T25	/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.321056069	May 05 02:48:57 PM PDT 24	May 05 02:49:03 PM PDT 24	3054058118 ps
T24	/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.4131404895	May 05 02:49:51 PM PDT 24	May 05 02:49:55 PM PDT 24	2618462531 ps
T21	/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1106388247	May 05 02:49:04 PM PDT 24	May 05 02:49:07 PM PDT 24	2496639466 ps
T42	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3767962282	May 05 02:49:21 PM PDT 24	May 05 02:49:47 PM PDT 24	11530901746 ps
T49	/workspace/coverage/default/33.sysrst_ctrl_alert_test.1374237585	May 05 02:50:25 PM PDT 24	May 05 02:50:29 PM PDT 24	2015868814 ps
T7	/workspace/coverage/default/44.sysrst_ctrl_stress_all.2974937194	May 05 02:50:38 PM PDT 24	May 05 02:50:47 PM PDT 24	10543961325 ps
T50	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1450777107	May 05 02:48:55 PM PDT 24	May 05 02:48:59 PM PDT 24	2070102157 ps
T51	/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.278969586	May 05 02:48:59 PM PDT 24	May 05 02:49:02 PM PDT 24	2197951723 ps
T43	/workspace/coverage/default/15.sysrst_ctrl_stress_all.1341509352	May 05 02:49:17 PM PDT 24	May 05 02:49:47 PM PDT 24	36313268899 ps
T63	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.4049191515	May 05 02:50:34 PM PDT 24	May 05 02:50:37 PM PDT 24	2531989308 ps
T64	/workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.626921729	May 05 02:50:33 PM PDT 24	May 05 02:50:36 PM PDT 24	2624462068 ps
T8	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2348006324	May 05 02:48:47 PM PDT 24	May 05 02:48:50 PM PDT 24	2418753923 ps
T65	/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3838149367	May 05 02:50:37 PM PDT 24	May 05 02:50:40 PM PDT 24	2525964933 ps
T9	/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3028029021	May 05 02:49:05 PM PDT 24	May 05 02:49:14 PM PDT 24	7455692781 ps
T10	/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2704743850	May 05 02:50:34 PM PDT 24	May 05 02:51:57 PM PDT 24	133063243815 ps
T85	/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3956841326	May 05 02:50:59 PM PDT 24	May 05 02:51:00 PM PDT 24	2252003799 ps
T100	/workspace/coverage/default/42.sysrst_ctrl_smoke.3008980016	May 05 02:50:34 PM PDT 24	May 05 02:50:37 PM PDT 24	2131298384 ps
T101	/workspace/coverage/default/39.sysrst_ctrl_smoke.3994106540	May 05 02:50:32 PM PDT 24	May 05 02:50:34 PM PDT 24	2123853165 ps
T52	/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1857283822	May 05 02:51:02 PM PDT 24	May 05 02:51:06 PM PDT 24	3428550963 ps
T22	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4064898702	May 05 02:50:30 PM PDT 24	May 05 02:50:51 PM PDT 24	124300755947 ps
T44	/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1475745205	May 05 02:50:39 PM PDT 24	May 05 02:50:43 PM PDT 24	3395229171 ps
T45	/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2862644746	May 05 02:50:34 PM PDT 24	May 05 02:50:37 PM PDT 24	4104144320 ps
T46	/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3821969037	May 05 02:49:51 PM PDT 24	May 05 02:49:55 PM PDT 24	3099190538 ps
T147	/workspace/coverage/default/28.sysrst_ctrl_alert_test.3368299285	May 05 02:49:50 PM PDT 24	May 05 02:49:53 PM PDT 24	2021316175 ps
T47	/workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.836483449	May 05 02:49:45 PM PDT 24	May 05 02:49:56 PM PDT 24	3410884263 ps
T36	/workspace/coverage/default/43.sysrst_ctrl_edge_detect.83170640	May 05 02:50:33 PM PDT 24	May 05 02:50:42 PM PDT 24	3284493755 ps
T57	/workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.2804361597	May 05 02:49:22 PM PDT 24	May 05 02:49:24 PM PDT 24	2485790976 ps
T48	/workspace/coverage/default/29.sysrst_ctrl_stress_all.2838652466	May 05 02:49:49 PM PDT 24	May 05 02:52:28 PM PDT 24	129531766948 ps
T102	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.826705290	May 05 02:50:34 PM PDT 24	May 05 02:51:22 PM PDT 24	17631328865 ps
T28	/workspace/coverage/default/32.sysrst_ctrl_combo_detect.650028588	May 05 02:50:02 PM PDT 24	May 05 02:52:18 PM PDT 24	101109616164 ps
T39	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1027213697	May 05 02:48:47 PM PDT 24	May 05 02:51:27 PM PDT 24	59096703470 ps
T103	/workspace/coverage/default/26.sysrst_ctrl_smoke.998015111	May 05 02:49:46 PM PDT 24	May 05 02:49:50 PM PDT 24	2121617868 ps
T40	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.679958138	May 05 02:50:02 PM PDT 24	May 05 02:50:47 PM PDT 24	68598710344 ps
T34	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.427919290	May 05 02:49:22 PM PDT 24	May 05 02:50:00 PM PDT 24	580372976183 ps
T66	/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.448358823	May 05 02:50:46 PM PDT 24	May 05 02:50:48 PM PDT 24	2633193819 ps
T68	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.373221061	May 05 02:49:04 PM PDT 24	May 05 02:49:07 PM PDT 24	2290298005 ps
T31	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.21546226	May 05 02:51:07 PM PDT 24	May 05 02:53:38 PM PDT 24	66938775824 ps
T41	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3688956011	May 05 02:51:08 PM PDT 24	May 05 02:56:46 PM PDT 24	126221455751 ps
T206	/workspace/coverage/default/16.sysrst_ctrl_alert_test.1508444582	May 05 02:49:19 PM PDT 24	May 05 02:49:23 PM PDT 24	2018898423 ps
T207	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.395054980	May 05 02:50:00 PM PDT 24	May 05 02:50:52 PM PDT 24	36636165642 ps
T67	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.3778284276	May 05 02:49:22 PM PDT 24	May 05 02:49:26 PM PDT 24	3949200376 ps
T32	/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3700556534	May 05 02:50:50 PM PDT 24	May 05 02:51:01 PM PDT 24	5086236534 ps
T69	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1857921333	May 05 02:49:21 PM PDT 24	May 05 02:52:45 PM PDT 24	82607413841 ps
T53	/workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2847232959	May 05 02:49:44 PM PDT 24	May 05 02:49:47 PM PDT 24	7488346737 ps
T104	/workspace/coverage/default/11.sysrst_ctrl_stress_all.4265099550	May 05 02:49:02 PM PDT 24	May 05 02:55:40 PM PDT 24	148929378498 ps
T199	/workspace/coverage/default/22.sysrst_ctrl_stress_all.4133894038	May 05 02:49:34 PM PDT 24	May 05 02:49:37 PM PDT 24	7078013265 ps
T86	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.2067164687	May 05 02:49:34 PM PDT 24	May 05 02:49:57 PM PDT 24	45756055740 ps
T29	/workspace/coverage/default/6.sysrst_ctrl_stress_all.1527662131	May 05 02:48:56 PM PDT 24	May 05 02:50:47 PM PDT 24	145488802252 ps
T200	/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1247970244	May 05 02:49:18 PM PDT 24	May 05 02:49:22 PM PDT 24	2216364062 ps
T201	/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3501805724	May 05 02:49:42 PM PDT 24	May 05 02:49:50 PM PDT 24	3017722400 ps
T58	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.449729349	May 05 02:49:15 PM PDT 24	May 05 02:49:23 PM PDT 24	2445658738 ps
T367	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.1320896079	May 05 02:50:30 PM PDT 24	May 05 02:50:33 PM PDT 24	2548651387 ps
T278	/workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2185546632	May 05 02:50:28 PM PDT 24	May 05 02:50:32 PM PDT 24	4214556491 ps
T20	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2988179510	May 05 02:49:59 PM PDT 24	May 05 02:50:04 PM PDT 24	3599155124 ps
T37	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.3835111034	May 05 02:49:50 PM PDT 24	May 05 02:49:52 PM PDT 24	2591972429 ps
T125	/workspace/coverage/default/34.sysrst_ctrl_stress_all.3471825275	May 05 02:50:25 PM PDT 24	May 05 02:50:35 PM PDT 24	14767446183 ps
T70	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.307384423	May 05 02:48:50 PM PDT 24	May 05 02:49:08 PM PDT 24	26355508454 ps
T126	/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2911350788	May 05 02:48:56 PM PDT 24	May 05 02:49:00 PM PDT 24	2619448130 ps
T59	/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.801980236	May 05 02:49:47 PM PDT 24	May 05 02:49:49 PM PDT 24	2520645735 ps
T35	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2329516080	May 05 02:48:56 PM PDT 24	May 05 02:52:44 PM PDT 24	94421543209 ps
T127	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2800580725	May 05 02:48:52 PM PDT 24	May 05 02:49:00 PM PDT 24	2613299213 ps
T128	/workspace/coverage/default/31.sysrst_ctrl_edge_detect.2587497226	May 05 02:50:00 PM PDT 24	May 05 02:50:12 PM PDT 24	5397892181 ps
T129	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1928631195	May 05 02:49:44 PM PDT 24	May 05 02:49:47 PM PDT 24	2520296994 ps
T161	/workspace/coverage/default/40.sysrst_ctrl_edge_detect.2888653771	May 05 02:50:34 PM PDT 24	May 05 02:50:43 PM PDT 24	2844262870 ps
T162	/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3815308589	May 05 02:49:33 PM PDT 24	May 05 02:54:29 PM PDT 24	218752270459 ps
T163	/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2931435139	May 05 02:50:26 PM PDT 24	May 05 02:50:33 PM PDT 24	2163972345 ps
T164	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.388728722	May 05 02:49:51 PM PDT 24	May 05 02:50:03 PM PDT 24	3781385435 ps
T87	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.72636286	May 05 02:49:41 PM PDT 24	May 05 02:51:14 PM PDT 24	67985171650 ps
T165	/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2789750712	May 05 02:50:24 PM PDT 24	May 05 02:50:27 PM PDT 24	3355804601 ps
T30	/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1826212231	May 05 02:48:59 PM PDT 24	May 05 02:51:06 PM PDT 24	92834347979 ps
T369	/workspace/coverage/default/38.sysrst_ctrl_alert_test.1145114714	May 05 02:50:33 PM PDT 24	May 05 02:50:36 PM PDT 24	2040832071 ps
T284	/workspace/coverage/default/27.sysrst_ctrl_pin_override_test.4251752388	May 05 02:49:52 PM PDT 24	May 05 02:50:00 PM PDT 24	2514652688 ps
T370	/workspace/coverage/default/32.sysrst_ctrl_smoke.2422525214	May 05 02:50:01 PM PDT 24	May 05 02:50:07 PM PDT 24	2110166408 ps
T285	/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2688034670	May 05 02:48:59 PM PDT 24	May 05 02:49:02 PM PDT 24	2524212950 ps
T273	/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.795135447	May 05 02:49:58 PM PDT 24	May 05 02:50:04 PM PDT 24	3531391566 ps
T371	/workspace/coverage/default/9.sysrst_ctrl_stress_all.4025953289	May 05 02:49:00 PM PDT 24	May 05 02:49:06 PM PDT 24	7295265312 ps
T372	/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2874757645	May 05 02:49:05 PM PDT 24	May 05 02:49:08 PM PDT 24	2644547928 ps
T373	/workspace/coverage/default/44.sysrst_ctrl_smoke.442351555	May 05 02:50:38 PM PDT 24	May 05 02:50:40 PM PDT 24	2213669139 ps
T169	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1847898236	May 05 02:48:54 PM PDT 24	May 05 02:48:57 PM PDT 24	3807380251 ps
T374	/workspace/coverage/default/9.sysrst_ctrl_alert_test.1022672813	May 05 02:49:01 PM PDT 24	May 05 02:49:07 PM PDT 24	2012581740 ps
T235	/workspace/coverage/default/23.sysrst_ctrl_combo_detect.3326797393	May 05 02:49:42 PM PDT 24	May 05 02:55:35 PM PDT 24	141601604514 ps
T54	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3833047614	May 05 02:49:19 PM PDT 24	May 05 02:49:28 PM PDT 24	9029520450 ps
T116	/workspace/coverage/default/7.sysrst_ctrl_alert_test.1069046245	May 05 02:49:04 PM PDT 24	May 05 02:49:08 PM PDT 24	2015644062 ps
T117	/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2396865850	May 05 02:50:44 PM PDT 24	May 05 02:50:47 PM PDT 24	3540339623 ps
T118	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1637147982	May 05 02:48:47 PM PDT 24	May 05 02:48:55 PM PDT 24	2523284940 ps
T119	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2006557177	May 05 02:48:54 PM PDT 24	May 05 02:49:02 PM PDT 24	2510802080 ps
T120	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3276861568	May 05 02:49:45 PM PDT 24	May 05 02:50:32 PM PDT 24	18635821968 ps
T121	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4023644730	May 05 02:50:38 PM PDT 24	May 05 02:50:41 PM PDT 24	2627741226 ps
T55	/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2297736261	May 05 02:50:30 PM PDT 24	May 05 02:50:34 PM PDT 24	9158862898 ps
T122	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3671012366	May 05 02:49:06 PM PDT 24	May 05 02:51:19 PM PDT 24	50958972352 ps
T123	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3246202438	May 05 02:49:27 PM PDT 24	May 05 02:50:46 PM PDT 24	113950240108 ps
T88	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3202730336	May 05 02:50:35 PM PDT 24	May 05 02:56:23 PM PDT 24	141557566052 ps
T60	/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3822459311	May 05 02:50:35 PM PDT 24	May 05 02:50:39 PM PDT 24	2490843466 ps
T89	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2908984596	May 05 02:48:46 PM PDT 24	May 05 02:48:57 PM PDT 24	26503546992 ps
T56	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.95106417	May 05 02:48:44 PM PDT 24	May 05 02:50:17 PM PDT 24	33646256275 ps
T375	/workspace/coverage/default/31.sysrst_ctrl_alert_test.2293230023	May 05 02:49:58 PM PDT 24	May 05 02:50:01 PM PDT 24	2023243676 ps
T368	/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1885079521	May 05 02:50:38 PM PDT 24	May 05 02:50:46 PM PDT 24	2511942583 ps
T225	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2985421621	May 05 02:50:34 PM PDT 24	May 05 02:50:48 PM PDT 24	54504130780 ps
T228	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1894153764	May 05 02:51:16 PM PDT 24	May 05 02:53:46 PM PDT 24	111665559092 ps
T61	/workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1816810477	May 05 02:50:01 PM PDT 24	May 05 02:50:04 PM PDT 24	2473904255 ps
T239	/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2868574056	May 05 02:51:00 PM PDT 24	May 05 02:52:42 PM PDT 24	75138452640 ps
T234	/workspace/coverage/default/19.sysrst_ctrl_combo_detect.2272496813	May 05 02:49:26 PM PDT 24	May 05 02:50:13 PM PDT 24	93347467390 ps
T62	/workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.779279955	May 05 02:49:46 PM PDT 24	May 05 02:49:48 PM PDT 24	2506574617 ps
T33	/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2192703844	May 05 02:50:59 PM PDT 24	May 05 02:51:07 PM PDT 24	3724871705 ps
T376	/workspace/coverage/default/16.sysrst_ctrl_smoke.3480839466	May 05 02:49:17 PM PDT 24	May 05 02:49:19 PM PDT 24	2123998008 ps
T90	/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.4161465891	May 05 02:51:12 PM PDT 24	May 05 02:52:51 PM PDT 24	38621011604 ps
T38	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2104214396	May 05 02:49:25 PM PDT 24	May 05 02:50:49 PM PDT 24	141814598877 ps
T377	/workspace/coverage/default/17.sysrst_ctrl_stress_all.3393196720	May 05 02:49:23 PM PDT 24	May 05 02:49:27 PM PDT 24	6722846974 ps
T229	/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2620320630	May 05 02:51:15 PM PDT 24	May 05 03:02:29 PM PDT 24	250821161485 ps
T281	/workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.4190925705	May 05 02:49:17 PM PDT 24	May 05 02:49:21 PM PDT 24	2476354459 ps
T378	/workspace/coverage/default/0.sysrst_ctrl_smoke.889652195	May 05 02:48:46 PM PDT 24	May 05 02:48:49 PM PDT 24	2132557461 ps
T379	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2116128124	May 05 02:49:16 PM PDT 24	May 05 02:49:19 PM PDT 24	2624275523 ps
T237	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.361254821	May 05 02:49:04 PM PDT 24	May 05 02:49:48 PM PDT 24	60851502237 ps
T145	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.1902082927	May 05 02:48:44 PM PDT 24	May 05 02:48:54 PM PDT 24	4185012356 ps
T380	/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.552212913	May 05 02:49:26 PM PDT 24	May 05 02:49:30 PM PDT 24	2465058392 ps
T381	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.621302838	May 05 02:49:04 PM PDT 24	May 05 02:49:15 PM PDT 24	3716606317 ps
T382	/workspace/coverage/default/47.sysrst_ctrl_alert_test.2564287074	May 05 02:51:02 PM PDT 24	May 05 02:51:06 PM PDT 24	2013954025 ps
T230	/workspace/coverage/default/12.sysrst_ctrl_combo_detect.3293402252	May 05 02:49:04 PM PDT 24	May 05 02:55:00 PM PDT 24	137169674875 ps
T91	/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3806823921	May 05 02:48:56 PM PDT 24	May 05 02:54:41 PM PDT 24	143695245336 ps
T383	/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1304470527	May 05 02:49:00 PM PDT 24	May 05 02:49:05 PM PDT 24	2629668806 ps
T384	/workspace/coverage/default/25.sysrst_ctrl_stress_all.3346319939	May 05 02:49:45 PM PDT 24	May 05 02:56:41 PM PDT 24	653136779153 ps
T244	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.349087872	May 05 02:48:55 PM PDT 24	May 05 02:49:09 PM PDT 24	22151190491 ps
T143	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2169530220	May 05 02:48:59 PM PDT 24	May 05 02:49:01 PM PDT 24	5211517763 ps
T71	/workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.257995371	May 05 02:49:24 PM PDT 24	May 05 02:49:34 PM PDT 24	11506746328 ps
T72	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1857021568	May 05 02:49:58 PM PDT 24	May 05 02:50:06 PM PDT 24	33568184947 ps
T269	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.4031781242	May 05 02:49:20 PM PDT 24	May 05 02:56:09 PM PDT 24	159667033932 ps
T73	/workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3492304130	May 05 02:50:23 PM PDT 24	May 05 02:50:27 PM PDT 24	5599916251 ps
T270	/workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3991478263	May 05 02:50:33 PM PDT 24	May 05 02:50:39 PM PDT 24	5521074248 ps
T92	/workspace/coverage/default/23.sysrst_ctrl_stress_all.1698032112	May 05 02:49:42 PM PDT 24	May 05 02:50:13 PM PDT 24	89901296425 ps
T271	/workspace/coverage/default/30.sysrst_ctrl_stress_all.1566792987	May 05 02:49:59 PM PDT 24	May 05 02:52:36 PM PDT 24	134979698412 ps
T272	/workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1680288860	May 05 02:49:50 PM PDT 24	May 05 02:49:53 PM PDT 24	11220167755 ps
T385	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2711764947	May 05 02:49:00 PM PDT 24	May 05 02:50:22 PM PDT 24	31160223188 ps
T346	/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.937369843	May 05 02:51:11 PM PDT 24	May 05 02:51:29 PM PDT 24	61204740947 ps
T386	/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3542236693	May 05 02:48:52 PM PDT 24	May 05 02:48:57 PM PDT 24	2518628386 ps
T238	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1749031474	May 05 02:51:11 PM PDT 24	May 05 02:51:52 PM PDT 24	59647353825 ps
T387	/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.231760901	May 05 02:48:42 PM PDT 24	May 05 02:48:44 PM PDT 24	2167829593 ps
T329	/workspace/coverage/default/34.sysrst_ctrl_combo_detect.2409012539	May 05 02:50:23 PM PDT 24	May 05 02:55:49 PM PDT 24	120499500447 ps
T388	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.1520858716	May 05 02:49:41 PM PDT 24	May 05 02:49:49 PM PDT 24	2679073279 ps
T223	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1641797644	May 05 02:51:11 PM PDT 24	May 05 02:52:40 PM PDT 24	30831917620 ps
T389	/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.834504441	May 05 02:49:25 PM PDT 24	May 05 02:49:34 PM PDT 24	3159748273 ps
T105	/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3693574108	May 05 02:49:19 PM PDT 24	May 05 02:50:12 PM PDT 24	22412412159 ps
T144	/workspace/coverage/default/29.sysrst_ctrl_edge_detect.3311637064	May 05 02:49:51 PM PDT 24	May 05 02:49:55 PM PDT 24	5572631333 ps
T304	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.625377345	May 05 02:49:58 PM PDT 24	May 05 02:50:00 PM PDT 24	2137898149 ps
T305	/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1191665866	May 05 02:49:58 PM PDT 24	May 05 02:50:03 PM PDT 24	2459856316 ps
T274	/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1461532749	May 05 02:50:36 PM PDT 24	May 05 02:50:48 PM PDT 24	4108380596 ps
T306	/workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.304742751	May 05 02:50:34 PM PDT 24	May 05 02:50:39 PM PDT 24	2446813323 ps
T307	/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2717368407	May 05 02:50:33 PM PDT 24	May 05 02:50:41 PM PDT 24	2473187880 ps
T308	/workspace/coverage/default/9.sysrst_ctrl_combo_detect.802893029	May 05 02:49:01 PM PDT 24	May 05 02:51:07 PM PDT 24	180957581546 ps
T224	/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3628928926	May 05 02:51:07 PM PDT 24	May 05 02:53:47 PM PDT 24	63604181054 ps
T309	/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3722740514	May 05 02:49:29 PM PDT 24	May 05 02:49:37 PM PDT 24	2613492691 ps
T390	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.982682616	May 05 02:49:15 PM PDT 24	May 05 02:49:24 PM PDT 24	3257756298 ps
T391	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.910962941	May 05 02:49:28 PM PDT 24	May 05 02:49:32 PM PDT 24	2624384031 ps
T167	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3023685980	May 05 02:49:00 PM PDT 24	May 05 02:49:03 PM PDT 24	3840035257 ps
T392	/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.574113078	May 05 02:48:55 PM PDT 24	May 05 02:49:01 PM PDT 24	6252922556 ps
T106	/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1608430558	May 05 02:48:56 PM PDT 24	May 05 02:48:59 PM PDT 24	6153098896 ps
T393	/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.4148983209	May 05 02:49:01 PM PDT 24	May 05 02:49:06 PM PDT 24	2462559876 ps
T394	/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3119453121	May 05 02:51:03 PM PDT 24	May 05 02:51:11 PM PDT 24	2609861926 ps
T365	/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2680734559	May 05 02:49:01 PM PDT 24	May 05 02:49:44 PM PDT 24	734285723116 ps
T395	/workspace/coverage/default/30.sysrst_ctrl_pin_access_test.142693624	May 05 02:49:47 PM PDT 24	May 05 02:49:54 PM PDT 24	2105168837 ps
T93	/workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1646302782	May 05 02:49:42 PM PDT 24	May 05 02:50:56 PM PDT 24	122112840262 ps
T177	/workspace/coverage/default/42.sysrst_ctrl_alert_test.749492081	May 05 02:50:36 PM PDT 24	May 05 02:50:39 PM PDT 24	2042070117 ps
T178	/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.874258082	May 05 02:49:03 PM PDT 24	May 05 02:49:08 PM PDT 24	2454174419 ps
T179	/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2969655738	May 05 02:51:17 PM PDT 24	May 05 02:51:23 PM PDT 24	28490283502 ps
T180	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1146805070	May 05 02:51:05 PM PDT 24	May 05 02:55:02 PM PDT 24	128850667729 ps
T181	/workspace/coverage/default/6.sysrst_ctrl_alert_test.649561359	May 05 02:48:55 PM PDT 24	May 05 02:48:58 PM PDT 24	2034003330 ps
T182	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.4127738075	May 05 02:50:03 PM PDT 24	May 05 02:50:46 PM PDT 24	32367845762 ps
T142	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.4278035547	May 05 02:49:27 PM PDT 24	May 05 02:50:45 PM PDT 24	31247939849 ps
T94	/workspace/coverage/default/5.sysrst_ctrl_combo_detect.337830888	May 05 02:48:55 PM PDT 24	May 05 02:49:46 PM PDT 24	22983817993 ps
T148	/workspace/coverage/default/3.sysrst_ctrl_combo_detect.425441557	May 05 02:48:54 PM PDT 24	May 05 02:53:11 PM PDT 24	99183365410 ps
T149	/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1143263051	May 05 02:49:50 PM PDT 24	May 05 02:49:59 PM PDT 24	3340168718 ps
T150	/workspace/coverage/default/15.sysrst_ctrl_pin_override_test.3591215961	May 05 02:49:20 PM PDT 24	May 05 02:49:25 PM PDT 24	2517461333 ps
T151	/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.676159306	May 05 02:50:57 PM PDT 24	May 05 02:51:01 PM PDT 24	3771794279 ps
T152	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3729519691	May 05 02:50:28 PM PDT 24	May 05 02:51:19 PM PDT 24	92393379048 ps
T146	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2459795396	May 05 02:49:42 PM PDT 24	May 05 02:50:49 PM PDT 24	99580044421 ps
T153	/workspace/coverage/default/38.sysrst_ctrl_combo_detect.878762889	May 05 02:50:34 PM PDT 24	May 05 02:51:06 PM PDT 24	68967804641 ps
T154	/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.4076616878	May 05 02:50:30 PM PDT 24	May 05 02:50:38 PM PDT 24	2467399545 ps
T396	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3829311517	May 05 02:49:44 PM PDT 24	May 05 02:49:46 PM PDT 24	3898281051 ps
T397	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.505798605	May 05 02:49:00 PM PDT 24	May 05 02:49:03 PM PDT 24	2118783084 ps
T398	/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.88227793	May 05 02:49:58 PM PDT 24	May 05 02:53:02 PM PDT 24	73518132363 ps
T184	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.3271262960	May 05 02:49:21 PM PDT 24	May 05 02:49:30 PM PDT 24	3020032017 ps
T107	/workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1317941315	May 05 02:49:03 PM PDT 24	May 05 02:51:10 PM PDT 24	200328576668 ps
T95	/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.24516115	May 05 02:49:19 PM PDT 24	May 05 03:00:44 PM PDT 24	285323278000 ps
T83	/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3401442568	May 05 02:50:26 PM PDT 24	May 05 02:50:29 PM PDT 24	7604594078 ps
T170	/workspace/coverage/default/41.sysrst_ctrl_smoke.1788625227	May 05 02:50:34 PM PDT 24	May 05 02:50:42 PM PDT 24	2108088854 ps
T108	/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.408974147	May 05 02:50:35 PM PDT 24	May 05 02:50:44 PM PDT 24	4518213214 ps
T171	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2734602598	May 05 02:50:28 PM PDT 24	May 05 02:50:31 PM PDT 24	2535495601 ps
T172	/workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3406627757	May 05 02:48:43 PM PDT 24	May 05 02:48:46 PM PDT 24	2487554519 ps
T173	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2648936792	May 05 02:50:26 PM PDT 24	May 05 02:50:28 PM PDT 24	2108184546 ps
T109	/workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2979458473	May 05 02:48:47 PM PDT 24	May 05 02:48:50 PM PDT 24	4787625226 ps
T174	/workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3168609868	May 05 02:48:51 PM PDT 24	May 05 02:48:55 PM PDT 24	2517721276 ps
T302	/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1200184588	May 05 02:48:58 PM PDT 24	May 05 02:50:28 PM PDT 24	37189911515 ps
T328	/workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.451364920	May 05 02:50:00 PM PDT 24	May 05 02:51:11 PM PDT 24	105917794318 ps
T399	/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.712282241	May 05 02:49:20 PM PDT 24	May 05 02:49:23 PM PDT 24	2223913455 ps
T400	/workspace/coverage/default/4.sysrst_ctrl_alert_test.2353663577	May 05 02:48:53 PM PDT 24	May 05 02:48:59 PM PDT 24	2014649161 ps
T84	/workspace/coverage/default/43.sysrst_ctrl_stress_all.2615010633	May 05 02:50:39 PM PDT 24	May 05 02:50:57 PM PDT 24	14660239458 ps
T360	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1311032834	May 05 02:51:11 PM PDT 24	May 05 02:53:30 PM PDT 24	110144663100 ps
T282	/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.689016750	May 05 02:49:20 PM PDT 24	May 05 02:49:25 PM PDT 24	2481456382 ps
T401	/workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3212457956	May 05 02:50:33 PM PDT 24	May 05 02:50:41 PM PDT 24	2997037170 ps
T402	/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.4167037869	May 05 02:50:33 PM PDT 24	May 05 02:50:36 PM PDT 24	3570987007 ps
T403	/workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1772955548	May 05 02:49:42 PM PDT 24	May 05 02:49:48 PM PDT 24	3514758995 ps
T404	/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.783614673	May 05 02:50:27 PM PDT 24	May 05 02:50:52 PM PDT 24	8481640034 ps
T168	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.3739417048	May 05 02:49:13 PM PDT 24	May 05 02:49:27 PM PDT 24	5001728242 ps
T405	/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.4201589276	May 05 02:50:32 PM PDT 24	May 05 02:50:35 PM PDT 24	3236999241 ps
T406	/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2677010660	May 05 02:49:43 PM PDT 24	May 05 02:49:46 PM PDT 24	2453590840 ps
T407	/workspace/coverage/default/26.sysrst_ctrl_alert_test.3318504381	May 05 02:49:44 PM PDT 24	May 05 02:49:50 PM PDT 24	2009776224 ps
T408	/workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1551773358	May 05 02:48:45 PM PDT 24	May 05 02:56:51 PM PDT 24	175781392232 ps
T409	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.4175388900	May 05 02:50:30 PM PDT 24	May 05 02:50:33 PM PDT 24	2625234440 ps
T110	/workspace/coverage/default/27.sysrst_ctrl_stress_all.3119549444	May 05 02:49:45 PM PDT 24	May 05 02:52:11 PM PDT 24	111015252219 ps
T410	/workspace/coverage/default/1.sysrst_ctrl_smoke.2315184742	May 05 02:48:45 PM PDT 24	May 05 02:48:49 PM PDT 24	2137310688 ps
T411	/workspace/coverage/default/39.sysrst_ctrl_stress_all.3212162805	May 05 02:50:33 PM PDT 24	May 05 02:50:41 PM PDT 24	14124415629 ps
T245	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.660855799	May 05 02:48:48 PM PDT 24	May 05 02:49:48 PM PDT 24	22009269282 ps
T155	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3741882363	May 05 02:49:14 PM PDT 24	May 05 02:51:10 PM PDT 24	91440152488 ps
T412	/workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3709185854	May 05 02:50:26 PM PDT 24	May 05 02:50:34 PM PDT 24	2463337754 ps
T275	/workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.4130379329	May 05 02:48:59 PM PDT 24	May 05 02:49:02 PM PDT 24	3294003784 ps
T413	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4208950907	May 05 02:49:06 PM PDT 24	May 05 02:49:09 PM PDT 24	2524620812 ps
T330	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3484687445	May 05 02:50:39 PM PDT 24	May 05 02:54:53 PM PDT 24	104222103280 ps
T414	/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1685946460	May 05 02:49:51 PM PDT 24	May 05 02:49:56 PM PDT 24	2612303501 ps
T415	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3055707298	May 05 02:48:45 PM PDT 24	May 05 02:48:50 PM PDT 24	2412936102 ps
T416	/workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3559262116	May 05 02:50:28 PM PDT 24	May 05 02:50:30 PM PDT 24	3984640056 ps
T352	/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.408503810	May 05 02:50:35 PM PDT 24	May 05 02:53:46 PM PDT 24	77393307104 ps
T417	/workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2034027417	May 05 02:49:24 PM PDT 24	May 05 02:49:31 PM PDT 24	2045113182 ps
T418	/workspace/coverage/default/43.sysrst_ctrl_smoke.2943116521	May 05 02:50:35 PM PDT 24	May 05 02:50:42 PM PDT 24	2113055869 ps
T419	/workspace/coverage/default/8.sysrst_ctrl_stress_all.2244786462	May 05 02:49:04 PM PDT 24	May 05 02:49:21 PM PDT 24	11288710895 ps
T420	/workspace/coverage/default/40.sysrst_ctrl_smoke.1472202098	May 05 02:50:30 PM PDT 24	May 05 02:50:33 PM PDT 24	2141322919 ps
T347	/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3445191006	May 05 02:51:08 PM PDT 24	May 05 02:52:11 PM PDT 24	53732919251 ps
T421	/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1827891229	May 05 02:49:15 PM PDT 24	May 05 02:49:18 PM PDT 24	2487415988 ps
T422	/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3833772176	May 05 02:50:36 PM PDT 24	May 05 02:50:44 PM PDT 24	2612063504 ps
T195	/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3555553557	May 05 02:48:54 PM PDT 24	May 05 02:49:55 PM PDT 24	92798755753 ps
T423	/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1084856298	May 05 02:50:34 PM PDT 24	May 05 02:50:37 PM PDT 24	3051209271 ps
T424	/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2058366756	May 05 02:49:54 PM PDT 24	May 05 02:49:57 PM PDT 24	3425302840 ps
T283	/workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3582698467	May 05 02:48:47 PM PDT 24	May 05 02:48:50 PM PDT 24	2494019823 ps
T425	/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2193013676	May 05 02:49:19 PM PDT 24	May 05 02:52:35 PM PDT 24	71711931404 ps
T426	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2937185171	May 05 02:49:00 PM PDT 24	May 05 02:49:02 PM PDT 24	2735223746 ps
T427	/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3083007206	May 05 02:49:10 PM PDT 24	May 05 02:49:16 PM PDT 24	3846126063 ps
T428	/workspace/coverage/default/29.sysrst_ctrl_smoke.4268798063	May 05 02:49:48 PM PDT 24	May 05 02:49:52 PM PDT 24	2119038407 ps
T429	/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2138837150	May 05 02:48:57 PM PDT 24	May 05 02:49:00 PM PDT 24	2487750260 ps
T96	/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2949072337	May 05 02:50:30 PM PDT 24	May 05 02:50:56 PM PDT 24	32738245408 ps
T430	/workspace/coverage/default/23.sysrst_ctrl_alert_test.2668236121	May 05 02:49:44 PM PDT 24	May 05 02:49:51 PM PDT 24	2014410277 ps