Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.34 98.84 96.83 100.00 96.79 98.30 99.61 91.01


Total tests in report: 909
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.62 67.62 82.91 82.91 73.18 73.18 85.62 85.62 32.05 32.05 84.62 84.62 70.52 70.52 44.47 44.47 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3767288599
77.79 10.16 89.55 6.64 80.71 7.53 88.36 2.74 60.90 28.85 90.39 5.77 83.72 13.20 50.89 6.42 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2360513273
85.37 7.58 96.53 6.98 90.12 9.40 90.18 1.83 72.44 11.54 96.01 5.62 94.32 10.60 57.99 7.09 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1549655792
87.15 1.78 96.87 0.34 90.47 0.35 97.49 7.31 73.72 1.28 96.08 0.07 94.51 0.19 60.89 2.91 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3069467248
88.57 1.42 96.94 0.07 91.78 1.31 98.17 0.68 73.72 0.00 96.19 0.11 94.61 0.10 68.55 7.65 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3086098566
89.48 0.92 97.13 0.19 92.14 0.35 98.17 0.00 76.28 2.56 96.38 0.18 94.99 0.39 71.28 2.74 /workspace/coverage/default/28.sysrst_ctrl_stress_all.908329984
90.39 0.91 97.69 0.56 94.08 1.95 98.17 0.00 79.49 3.21 97.01 0.63 94.99 0.00 71.28 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.4251086169
91.14 0.75 97.78 0.09 94.14 0.05 98.17 0.00 81.41 1.92 97.12 0.11 96.72 1.73 72.63 1.34 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1777086445
91.71 0.58 97.85 0.07 94.19 0.05 98.17 0.00 83.33 1.92 97.23 0.11 96.92 0.19 74.30 1.68 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3158555483
92.27 0.56 98.00 0.15 94.26 0.08 98.17 0.00 86.54 3.21 97.41 0.18 97.21 0.29 74.30 0.00 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2458663516
92.77 0.50 98.06 0.06 94.31 0.05 98.17 0.00 87.18 0.64 97.45 0.04 97.30 0.10 76.93 2.63 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3063642276
93.21 0.44 98.10 0.04 94.31 0.00 98.17 0.00 89.74 2.56 97.52 0.07 97.30 0.00 77.32 0.39 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.227591593
93.58 0.37 98.10 0.00 94.34 0.03 98.17 0.00 89.74 0.00 97.56 0.04 97.40 0.10 79.72 2.40 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3155402418
93.86 0.29 98.10 0.00 94.36 0.03 99.77 1.60 89.74 0.00 97.56 0.00 97.50 0.10 80.00 0.28 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.866790298
94.14 0.28 98.21 0.11 94.36 0.00 99.77 0.00 89.74 0.00 97.56 0.00 97.50 0.00 81.84 1.84 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3897134164
94.41 0.27 98.26 0.06 94.54 0.18 99.77 0.00 90.38 0.64 97.67 0.11 97.69 0.19 82.57 0.73 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.495992882
94.68 0.27 98.38 0.11 94.62 0.08 99.77 0.00 91.67 1.28 97.74 0.07 97.98 0.29 82.63 0.06 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1209537670
94.93 0.25 98.45 0.07 94.64 0.03 99.77 0.00 92.95 1.28 97.86 0.11 98.07 0.10 82.79 0.17 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1236881595
95.17 0.24 98.45 0.00 94.69 0.05 99.77 0.00 92.95 0.00 97.86 0.00 98.36 0.29 84.13 1.34 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.112567796
95.35 0.18 98.49 0.04 94.89 0.20 99.77 0.00 92.95 0.00 97.93 0.07 99.04 0.67 84.41 0.28 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2520763278
95.52 0.16 98.49 0.00 95.58 0.68 99.77 0.00 92.95 0.00 97.93 0.00 99.04 0.00 84.86 0.45 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1671812608
95.67 0.15 98.53 0.04 95.63 0.05 99.77 0.00 93.59 0.64 98.00 0.07 99.13 0.10 85.03 0.17 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1647909611
95.80 0.14 98.56 0.04 95.70 0.08 99.77 0.00 93.59 0.00 98.00 0.00 99.13 0.00 85.87 0.84 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.2776489114
95.93 0.13 98.60 0.04 95.73 0.03 99.77 0.00 94.23 0.64 98.04 0.04 99.23 0.10 85.92 0.06 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.56886441
96.06 0.13 98.64 0.04 95.75 0.03 99.77 0.00 94.87 0.64 98.08 0.04 99.33 0.10 85.98 0.06 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2290781413
96.18 0.12 98.68 0.04 95.78 0.03 99.77 0.00 95.51 0.64 98.11 0.04 99.42 0.10 85.98 0.00 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.390201551
96.30 0.12 98.71 0.04 95.80 0.03 99.77 0.00 96.15 0.64 98.15 0.04 99.52 0.10 85.98 0.00 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.768690612
96.40 0.10 98.73 0.02 95.80 0.00 99.77 0.00 96.79 0.64 98.19 0.04 99.52 0.00 85.98 0.00 /workspace/coverage/default/29.sysrst_ctrl_stress_all.3594126151
96.48 0.08 98.73 0.00 95.80 0.00 99.77 0.00 96.79 0.00 98.19 0.00 99.52 0.00 86.54 0.56 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1471462797
96.56 0.08 98.73 0.00 95.80 0.00 99.77 0.00 96.79 0.00 98.19 0.00 99.52 0.00 87.09 0.56 /workspace/coverage/default/33.sysrst_ctrl_stress_all.3185587999
96.63 0.07 98.73 0.00 95.80 0.00 99.77 0.00 96.79 0.00 98.19 0.00 99.52 0.00 87.60 0.50 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.688431286
96.69 0.06 98.73 0.00 95.80 0.00 99.77 0.00 96.79 0.00 98.19 0.00 99.52 0.00 87.99 0.39 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.4033129092
96.74 0.05 98.73 0.00 95.83 0.03 99.77 0.00 96.79 0.00 98.19 0.00 99.52 0.00 88.32 0.34 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2872548930
96.79 0.05 98.79 0.06 95.90 0.08 100.00 0.23 96.79 0.00 98.19 0.00 99.52 0.00 88.32 0.00 /workspace/coverage/default/13.sysrst_ctrl_alert_test.4086431520
96.84 0.05 98.79 0.00 96.21 0.30 100.00 0.00 96.79 0.00 98.19 0.00 99.52 0.00 88.38 0.06 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.577011358
96.88 0.04 98.79 0.00 96.51 0.30 100.00 0.00 96.79 0.00 98.19 0.00 99.52 0.00 88.38 0.00 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.320570823
96.92 0.04 98.79 0.00 96.56 0.05 100.00 0.00 96.79 0.00 98.19 0.00 99.52 0.00 88.60 0.22 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.471774249
96.95 0.03 98.79 0.00 96.56 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.52 0.00 88.83 0.22 /workspace/coverage/default/34.sysrst_ctrl_stress_all.1028020077
96.98 0.03 98.79 0.00 96.59 0.03 100.00 0.00 96.79 0.00 98.19 0.00 99.52 0.00 88.99 0.17 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1323585349
97.01 0.02 98.79 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.52 0.00 89.16 0.17 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.1355521002
97.03 0.02 98.79 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.52 0.00 89.33 0.17 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.3028278902
97.05 0.02 98.79 0.00 96.64 0.05 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.10 89.33 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.108118663
97.07 0.02 98.79 0.00 96.66 0.03 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 89.44 0.11 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1204632817
97.09 0.02 98.79 0.00 96.69 0.03 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 89.55 0.11 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.108379527
97.11 0.02 98.79 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 89.66 0.11 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.736481322
97.12 0.02 98.79 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 89.78 0.11 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1605657670
97.14 0.02 98.79 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 89.89 0.11 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4140805292
97.15 0.02 98.79 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.00 0.11 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4189203602
97.17 0.02 98.79 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.11 0.11 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1587225661
97.19 0.02 98.79 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.22 0.11 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2680747352
97.20 0.02 98.79 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.34 0.11 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3466987867
97.22 0.01 98.79 0.00 96.79 0.10 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.34 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3050494161
97.22 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.39 0.06 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.278946296
97.23 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.45 0.06 /workspace/coverage/default/12.sysrst_ctrl_stress_all.3121283509
97.24 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.50 0.06 /workspace/coverage/default/17.sysrst_ctrl_combo_detect.404871322
97.25 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.56 0.06 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3754138376
97.26 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.61 0.06 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.282611120
97.26 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.67 0.06 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.533586425
97.27 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.73 0.06 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3228474674
97.28 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.78 0.06 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.191466643
97.29 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.84 0.06 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.187121867
97.30 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.89 0.06 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1620970000
97.30 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 90.95 0.06 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3931922754
97.31 0.01 98.79 0.00 96.79 0.00 100.00 0.00 96.79 0.00 98.19 0.00 99.61 0.00 91.01 0.06 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.4129990252
97.32 0.01 98.81 0.02 96.79 0.00 100.00 0.00 96.79 0.00 98.23 0.04 99.61 0.00 91.01 0.00 /workspace/coverage/default/12.sysrst_ctrl_edge_detect.4276952758
97.33 0.01 98.82 0.02 96.79 0.00 100.00 0.00 96.79 0.00 98.26 0.04 99.61 0.00 91.01 0.00 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.1248439014
97.34 0.01 98.84 0.02 96.79 0.00 100.00 0.00 96.79 0.00 98.30 0.04 99.61 0.00 91.01 0.00 /workspace/coverage/default/5.sysrst_ctrl_stress_all.1829064542
97.34 0.01 98.84 0.00 96.81 0.03 100.00 0.00 96.79 0.00 98.30 0.00 99.61 0.00 91.01 0.00 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2172589854


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.419583666
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.369768744
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.4198851458
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1087061137
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2864496004
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1651852085
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1634750440
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3781584314
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3096427348
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3465152274
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1081811809
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2517303261
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2160106975
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2649024522
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1355894694
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1604693945
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2804935028
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1287815845
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3203013142
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2384657327
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1852147638
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2176441875
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.979202139
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3890543358
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1432132532
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3483178840
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2507811362
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3814764762
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2290276585
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3818543358
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1010396595
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3813824509
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1485246504
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3910238134
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1508123623
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2611418866
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.882904706
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3526574661
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3395610154
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2444863702
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.828778381
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2513557649
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3841857353
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.124167406
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2134154054
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2574776464
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.387045617
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3711099417
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2670951215
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1327662476
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2238439814
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4010879755
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1565359686
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3631929101
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.4175523411
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.625310488
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3282803085
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.618290160
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.399193987
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1531367898
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.973356914
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.575978268
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.756748131
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2372507016
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3692500328
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3063315260
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2497147440
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2150815005
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1630178329
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1052034951
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1951801724
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1748842460
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2287037725
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1063434490
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3748827365
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.95683459
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2787038436
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3674403214
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.772715779
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2552299535
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2259760758
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/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1066171879
/workspace/coverage/default/42.sysrst_ctrl_alert_test.3445155050
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2792195565
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2815452112
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.322079377
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3001551181
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.363749433
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2633545538
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.2542533650
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3942102929
/workspace/coverage/default/42.sysrst_ctrl_smoke.3173269629
/workspace/coverage/default/42.sysrst_ctrl_stress_all.147396937
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2140503554
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.143199356
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2224340192
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1128420034
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.4175931049
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3779419528
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3512576677
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.1742586600
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3872644355
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2620339504
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.582693163
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3225726386
/workspace/coverage/default/43.sysrst_ctrl_smoke.2380023608
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3221619861
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2481283493
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1319967672
/workspace/coverage/default/44.sysrst_ctrl_alert_test.74143147
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3888537472
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1051107713
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2082233343
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1254506800
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3609855892
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2960062305
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2168436091
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.455600121
/workspace/coverage/default/44.sysrst_ctrl_smoke.3939622563
/workspace/coverage/default/44.sysrst_ctrl_stress_all.587209433
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2761742819
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4289526366
/workspace/coverage/default/45.sysrst_ctrl_alert_test.672831809
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3703161911
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3006555212
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2127413473
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.91885551
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.346977830
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2013823341
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1207361360
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2557501859
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2931891188
/workspace/coverage/default/45.sysrst_ctrl_smoke.3266887104
/workspace/coverage/default/45.sysrst_ctrl_stress_all.85701207
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1529600829
/workspace/coverage/default/46.sysrst_ctrl_alert_test.408933073
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2537539258
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.629052677
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2304977171
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.148972222
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2586137284
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2147701028
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2316385477
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3141190690
/workspace/coverage/default/46.sysrst_ctrl_smoke.1236559013
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1335484757
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.750295586
/workspace/coverage/default/47.sysrst_ctrl_alert_test.116925641
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2089015741
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2309040469
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1354527263
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3538880007
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.344016602
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2641976164
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1373479384
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3116422067
/workspace/coverage/default/47.sysrst_ctrl_smoke.3786433791
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2512557010
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.8092756
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3400431097
/workspace/coverage/default/48.sysrst_ctrl_alert_test.1879571713
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3425441313
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.1371339099
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.637163396
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2342902343
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2113948616
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.53036392
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2573555896
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2916332364
/workspace/coverage/default/48.sysrst_ctrl_smoke.59355914
/workspace/coverage/default/48.sysrst_ctrl_stress_all.1458655403
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1537399145
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2829826318
/workspace/coverage/default/49.sysrst_ctrl_alert_test.719900607
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.259204865
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3733672059
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3469386637
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1689063946
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.694593843
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.877672747
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.2133845163
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.985677334
/workspace/coverage/default/49.sysrst_ctrl_smoke.3634188372
/workspace/coverage/default/49.sysrst_ctrl_stress_all.3507188889
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.4286141391
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1746811619
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1239656349
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3657191375
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.703057837
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1129415514
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1376104777
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.4039914985
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1628081659
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.824887634
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.4012928843
/workspace/coverage/default/5.sysrst_ctrl_smoke.76957040
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1569733647
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3639956217
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1651048940
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3014114076
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1017425835
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3647654546
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2039680425
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2079282305
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.137889158
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1948837984
/workspace/coverage/default/6.sysrst_ctrl_alert_test.322247951
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2614492723
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3581072312
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1901181519
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3427184711
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1894273108
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3643954396
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3940540813
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.275525461
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1278831647
/workspace/coverage/default/6.sysrst_ctrl_smoke.3431386667
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3648519034
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3824629071
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3779404694
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2969126007
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.487803786
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3258761098
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1154214891
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4203828823
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1147344693
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3513721837
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.498457739
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1975913202
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3464573556
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2179943830
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.41124171
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.51368051
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2687621737
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.690562203
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2010152375
/workspace/coverage/default/7.sysrst_ctrl_smoke.1202083267
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1754315262
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2269443718
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3622529733
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3267360650
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.4227053831
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.4123302298
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2337203171
/workspace/coverage/default/8.sysrst_ctrl_alert_test.488951094
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3176753353
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1577145550
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3867575456
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3799834726
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.233648504
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.802303900
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.369085761
/workspace/coverage/default/8.sysrst_ctrl_smoke.2020639028
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3053636179
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3346396628
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2077894167
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.82618307
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3506193829
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2291092548
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2236200915
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1683623855
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.613974781
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2464020783
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1891974067
/workspace/coverage/default/9.sysrst_ctrl_alert_test.898797283
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.499868098
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.3752012325
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3249883689
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1880090462
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1309395501
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1682854741
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2619015848
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3919710282
/workspace/coverage/default/9.sysrst_ctrl_smoke.2283671980
/workspace/coverage/default/9.sysrst_ctrl_stress_all.815302842
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1615398201
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3052315899
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2165157371
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4112771555
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.995318915
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3920801997
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2681885354
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.308247981
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3718064820




Total test records in report: 909
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4216959300 May 09 12:29:59 PM PDT 24 May 09 12:30:08 PM PDT 24 2303986451 ps
T1 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3507587814 May 09 12:29:01 PM PDT 24 May 09 12:29:08 PM PDT 24 4595215558 ps
T5 /workspace/coverage/default/11.sysrst_ctrl_alert_test.791086504 May 09 12:30:00 PM PDT 24 May 09 12:30:08 PM PDT 24 2009255040 ps
T13 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.4184796478 May 09 12:29:55 PM PDT 24 May 09 12:29:59 PM PDT 24 2135712149 ps
T2 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.181296871 May 09 12:29:25 PM PDT 24 May 09 12:29:31 PM PDT 24 3409613232 ps
T14 /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.4136894015 May 09 12:30:40 PM PDT 24 May 09 12:30:47 PM PDT 24 2631922391 ps
T15 /workspace/coverage/default/43.sysrst_ctrl_alert_test.2224340192 May 09 12:30:34 PM PDT 24 May 09 12:30:45 PM PDT 24 2012934104 ps
T3 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.67827797 May 09 12:30:17 PM PDT 24 May 09 12:30:25 PM PDT 24 3352461916 ps
T6 /workspace/coverage/default/1.sysrst_ctrl_stress_all.2893169353 May 09 12:28:42 PM PDT 24 May 09 12:29:11 PM PDT 24 9725871211 ps
T7 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3767288599 May 09 12:27:53 PM PDT 24 May 09 12:30:51 PM PDT 24 72590349155 ps
T8 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.112567796 May 09 12:30:26 PM PDT 24 May 09 12:31:42 PM PDT 24 25660735963 ps
T9 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3069467248 May 09 12:29:57 PM PDT 24 May 09 12:30:41 PM PDT 24 74122107639 ps
T58 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2619015848 May 09 12:29:28 PM PDT 24 May 09 12:29:36 PM PDT 24 2047177668 ps
T24 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2586057099 May 09 12:27:16 PM PDT 24 May 09 12:27:19 PM PDT 24 2304527585 ps
T59 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.866790298 May 09 12:31:09 PM PDT 24 May 09 12:31:57 PM PDT 24 22012523936 ps
T25 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3718064820 May 09 12:31:27 PM PDT 24 May 09 12:31:49 PM PDT 24 23107098572 ps
T10 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.577011358 May 09 12:29:16 PM PDT 24 May 09 12:36:16 PM PDT 24 2788998667705 ps
T51 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1635289094 May 09 12:29:13 PM PDT 24 May 09 12:29:17 PM PDT 24 3166617691 ps
T11 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2479084178 May 09 12:27:30 PM PDT 24 May 09 12:27:38 PM PDT 24 2414212326 ps
T12 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3222462338 May 09 12:30:06 PM PDT 24 May 09 12:30:16 PM PDT 24 6030190062 ps
T41 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1985846059 May 09 12:29:17 PM PDT 24 May 09 12:29:23 PM PDT 24 2220558927 ps
T39 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.1334731539 May 09 12:30:48 PM PDT 24 May 09 12:30:56 PM PDT 24 2768632846 ps
T19 /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3940540813 May 09 12:30:23 PM PDT 24 May 09 12:30:34 PM PDT 24 2461575796 ps
T20 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1777086445 May 09 12:30:00 PM PDT 24 May 09 12:30:29 PM PDT 24 22041905248 ps
T60 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3116422067 May 09 12:32:03 PM PDT 24 May 09 12:32:18 PM PDT 24 2510618758 ps
T21 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1899227423 May 09 12:29:31 PM PDT 24 May 09 12:29:40 PM PDT 24 3087412317 ps
T38 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1647909611 May 09 12:30:38 PM PDT 24 May 09 12:31:03 PM PDT 24 34014161923 ps
T22 /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2792195565 May 09 12:32:02 PM PDT 24 May 09 12:32:19 PM PDT 24 3573666435 ps
T46 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.143199356 May 09 12:30:28 PM PDT 24 May 09 12:30:35 PM PDT 24 2932393181 ps
T33 /workspace/coverage/default/45.sysrst_ctrl_stress_all.85701207 May 09 12:30:48 PM PDT 24 May 09 12:33:31 PM PDT 24 1139176674583 ps
T26 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4026498084 May 09 12:30:28 PM PDT 24 May 09 12:30:48 PM PDT 24 21361008593 ps
T30 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.688431286 May 09 12:28:14 PM PDT 24 May 09 12:31:00 PM PDT 24 153218295385 ps
T47 /workspace/coverage/default/20.sysrst_ctrl_smoke.2429014982 May 09 12:30:39 PM PDT 24 May 09 12:30:45 PM PDT 24 2140252400 ps
T48 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3265607348 May 09 12:29:48 PM PDT 24 May 09 12:29:55 PM PDT 24 2516630892 ps
T34 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1549655792 May 09 12:28:48 PM PDT 24 May 09 12:30:14 PM PDT 24 118970149604 ps
T31 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.14851685 May 09 12:31:07 PM PDT 24 May 09 12:34:14 PM PDT 24 68830904770 ps
T99 /workspace/coverage/default/40.sysrst_ctrl_alert_test.61244213 May 09 12:30:24 PM PDT 24 May 09 12:30:30 PM PDT 24 2036209857 ps
T100 /workspace/coverage/default/33.sysrst_ctrl_smoke.3142160362 May 09 12:30:06 PM PDT 24 May 09 12:30:11 PM PDT 24 2118638362 ps
T61 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1801032959 May 09 12:31:34 PM PDT 24 May 09 12:31:48 PM PDT 24 2522500855 ps
T101 /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3068407948 May 09 12:30:12 PM PDT 24 May 09 12:30:23 PM PDT 24 3104490250 ps
T54 /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2687621737 May 09 12:29:58 PM PDT 24 May 09 12:30:02 PM PDT 24 2503437655 ps
T62 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3942102929 May 09 12:31:48 PM PDT 24 May 09 12:31:59 PM PDT 24 2529994579 ps
T63 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3908685283 May 09 12:30:24 PM PDT 24 May 09 12:30:36 PM PDT 24 2509040415 ps
T64 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3108836673 May 09 12:31:53 PM PDT 24 May 09 12:32:08 PM PDT 24 2612353140 ps
T23 /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3390582639 May 09 12:31:39 PM PDT 24 May 09 12:31:55 PM PDT 24 3246902058 ps
T32 /workspace/coverage/default/28.sysrst_ctrl_stress_all.908329984 May 09 12:31:51 PM PDT 24 May 09 12:33:07 PM PDT 24 132694442932 ps
T35 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2360513273 May 09 12:29:58 PM PDT 24 May 09 12:31:11 PM PDT 24 105944969833 ps
T151 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1549987077 May 09 12:30:16 PM PDT 24 May 09 12:30:23 PM PDT 24 2515406325 ps
T40 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2464020783 May 09 12:31:18 PM PDT 24 May 09 12:31:59 PM PDT 24 55330454388 ps
T42 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3657191375 May 09 12:30:24 PM PDT 24 May 09 12:30:32 PM PDT 24 3579308869 ps
T52 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3053539072 May 09 12:30:16 PM PDT 24 May 09 12:30:25 PM PDT 24 6813326787 ps
T37 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.719647529 May 09 12:30:12 PM PDT 24 May 09 12:33:30 PM PDT 24 185880053543 ps
T65 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.995318915 May 09 12:31:09 PM PDT 24 May 09 12:33:07 PM PDT 24 80479643988 ps
T118 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.4043913017 May 09 12:30:10 PM PDT 24 May 09 12:30:20 PM PDT 24 2512257931 ps
T36 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2713640364 May 09 12:30:48 PM PDT 24 May 09 12:30:55 PM PDT 24 3533424819 ps
T43 /workspace/coverage/default/40.sysrst_ctrl_stress_all.348000569 May 09 12:31:44 PM PDT 24 May 09 12:32:54 PM PDT 24 87311420559 ps
T119 /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2342902343 May 09 12:32:10 PM PDT 24 May 09 12:32:21 PM PDT 24 3691042029 ps
T44 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.4231584311 May 09 12:30:17 PM PDT 24 May 09 12:30:22 PM PDT 24 3730696693 ps
T55 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2641976164 May 09 12:30:57 PM PDT 24 May 09 12:31:05 PM PDT 24 2468715921 ps
T120 /workspace/coverage/default/8.sysrst_ctrl_smoke.2020639028 May 09 12:30:21 PM PDT 24 May 09 12:30:29 PM PDT 24 2115128025 ps
T83 /workspace/coverage/default/37.sysrst_ctrl_combo_detect.1517660190 May 09 12:32:03 PM PDT 24 May 09 12:34:19 PM PDT 24 95585497978 ps
T53 /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2829826318 May 09 12:30:45 PM PDT 24 May 09 12:30:54 PM PDT 24 10450458667 ps
T45 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1192067140 May 09 12:31:45 PM PDT 24 May 09 12:32:17 PM PDT 24 41709682379 ps
T56 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1946822462 May 09 12:28:48 PM PDT 24 May 09 12:28:55 PM PDT 24 2464038241 ps
T275 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.278946296 May 09 12:29:37 PM PDT 24 May 09 12:29:43 PM PDT 24 2527072753 ps
T66 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1414536421 May 09 12:29:50 PM PDT 24 May 09 12:30:10 PM PDT 24 25849054562 ps
T67 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3897134164 May 09 12:29:55 PM PDT 24 May 09 12:31:38 PM PDT 24 74333755397 ps
T351 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3193454513 May 09 12:29:39 PM PDT 24 May 09 12:29:45 PM PDT 24 2634016860 ps
T352 /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.337461867 May 09 12:28:05 PM PDT 24 May 09 12:28:12 PM PDT 24 2084759445 ps
T353 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.543620478 May 09 12:31:30 PM PDT 24 May 09 12:31:47 PM PDT 24 2609933500 ps
T57 /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3696795860 May 09 12:31:46 PM PDT 24 May 09 12:31:59 PM PDT 24 2483743442 ps
T354 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.37708329 May 09 12:28:17 PM PDT 24 May 09 12:28:22 PM PDT 24 2042706698 ps
T355 /workspace/coverage/default/11.sysrst_ctrl_smoke.3085991322 May 09 12:28:40 PM PDT 24 May 09 12:28:48 PM PDT 24 2112812994 ps
T356 /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1524094678 May 09 12:30:48 PM PDT 24 May 09 12:30:56 PM PDT 24 4241546351 ps
T273 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.86924106 May 09 12:31:35 PM PDT 24 May 09 12:31:51 PM PDT 24 2462945321 ps
T357 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2414635403 May 09 12:29:10 PM PDT 24 May 09 12:29:14 PM PDT 24 2629722079 ps
T81 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1765972342 May 09 12:31:54 PM PDT 24 May 09 12:32:10 PM PDT 24 2889049638 ps
T272 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.446862028 May 09 12:29:47 PM PDT 24 May 09 12:29:59 PM PDT 24 3577892786 ps
T358 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3216571083 May 09 12:28:43 PM PDT 24 May 09 12:28:48 PM PDT 24 2624754988 ps
T82 /workspace/coverage/default/6.sysrst_ctrl_stress_all.3648519034 May 09 12:30:22 PM PDT 24 May 09 12:34:43 PM PDT 24 93647061352 ps
T69 /workspace/coverage/default/34.sysrst_ctrl_stress_all.1028020077 May 09 12:30:48 PM PDT 24 May 09 12:33:48 PM PDT 24 73571709345 ps
T359 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.785511677 May 09 12:30:39 PM PDT 24 May 09 12:30:47 PM PDT 24 2473193303 ps
T360 /workspace/coverage/default/0.sysrst_ctrl_smoke.500497111 May 09 12:29:28 PM PDT 24 May 09 12:29:39 PM PDT 24 2111956014 ps
T259 /workspace/coverage/default/26.sysrst_ctrl_alert_test.3599862730 May 09 12:31:30 PM PDT 24 May 09 12:31:44 PM PDT 24 2014800023 ps
T127 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.668153034 May 09 12:32:02 PM PDT 24 May 09 12:32:14 PM PDT 24 5124232169 ps
T111 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1204632817 May 09 12:30:01 PM PDT 24 May 09 12:30:05 PM PDT 24 3147161033 ps
T149 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.3538880007 May 09 12:31:03 PM PDT 24 May 09 12:31:08 PM PDT 24 2505314566 ps
T68 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3622529733 May 09 12:31:21 PM PDT 24 May 09 12:33:10 PM PDT 24 39205574750 ps
T84 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.2415505226 May 09 12:30:11 PM PDT 24 May 09 12:31:30 PM PDT 24 113612159155 ps
T361 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.4117523151 May 09 12:30:33 PM PDT 24 May 09 12:30:44 PM PDT 24 2454285548 ps
T343 /workspace/coverage/default/47.sysrst_ctrl_stress_all.2512557010 May 09 12:32:03 PM PDT 24 May 09 12:32:18 PM PDT 24 8099181842 ps
T70 /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1670785988 May 09 12:30:18 PM PDT 24 May 09 12:30:31 PM PDT 24 9806194179 ps
T276 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.719394026 May 09 12:30:00 PM PDT 24 May 09 12:30:10 PM PDT 24 2513600347 ps
T362 /workspace/coverage/default/27.sysrst_ctrl_smoke.2874747560 May 09 12:29:49 PM PDT 24 May 09 12:29:54 PM PDT 24 2135983175 ps
T85 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1209537670 May 09 12:32:11 PM PDT 24 May 09 12:32:38 PM PDT 24 27859464155 ps
T112 /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.192595633 May 09 12:27:18 PM PDT 24 May 09 12:27:21 PM PDT 24 7101321562 ps
T265 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2278631662 May 09 12:31:35 PM PDT 24 May 09 12:31:58 PM PDT 24 3819937200 ps
T263 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1587336516 May 09 12:30:14 PM PDT 24 May 09 12:30:31 PM PDT 24 19750669213 ps
T363 /workspace/coverage/default/42.sysrst_ctrl_smoke.3173269629 May 09 12:31:48 PM PDT 24 May 09 12:31:57 PM PDT 24 2168692264 ps
T72 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.1880090462 May 09 12:30:49 PM PDT 24 May 09 12:56:33 PM PDT 24 1048827643417 ps
T201 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3176753353 May 09 12:29:29 PM PDT 24 May 09 12:29:35 PM PDT 24 3459791468 ps
T202 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.53036392 May 09 12:30:59 PM PDT 24 May 09 12:31:07 PM PDT 24 2459367815 ps
T203 /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2614492723 May 09 12:30:23 PM PDT 24 May 09 12:30:37 PM PDT 24 3441854566 ps
T204 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.1107907501 May 09 12:30:31 PM PDT 24 May 09 12:30:37 PM PDT 24 2248728349 ps
T205 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.107081928 May 09 12:30:07 PM PDT 24 May 09 12:31:22 PM PDT 24 35825762072 ps
T206 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2620339504 May 09 12:30:29 PM PDT 24 May 09 12:30:41 PM PDT 24 2468919364 ps
T78 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2404767997 May 09 12:31:14 PM PDT 24 May 09 12:31:23 PM PDT 24 6743381209 ps
T86 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2681885354 May 09 12:31:07 PM PDT 24 May 09 12:31:22 PM PDT 24 22658861891 ps
T207 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1848797520 May 09 12:30:21 PM PDT 24 May 09 12:30:33 PM PDT 24 2510675385 ps
T364 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3420688801 May 09 12:29:29 PM PDT 24 May 09 12:29:36 PM PDT 24 2475543253 ps
T365 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1590633162 May 09 12:31:51 PM PDT 24 May 09 12:32:01 PM PDT 24 2188688115 ps
T264 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2321094914 May 09 12:28:37 PM PDT 24 May 09 12:30:15 PM PDT 24 36258208562 ps
T227 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1616899649 May 09 12:30:16 PM PDT 24 May 09 12:31:46 PM PDT 24 151259667604 ps
T366 /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2115663990 May 09 12:31:45 PM PDT 24 May 09 12:31:55 PM PDT 24 2163383590 ps
T367 /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2471431832 May 09 12:29:18 PM PDT 24 May 09 12:29:28 PM PDT 24 2610552572 ps
T368 /workspace/coverage/default/18.sysrst_ctrl_smoke.3083476769 May 09 12:30:21 PM PDT 24 May 09 12:30:32 PM PDT 24 2112470219 ps
T369 /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.3004916529 May 09 12:31:23 PM PDT 24 May 09 12:31:27 PM PDT 24 2256157645 ps
T260 /workspace/coverage/default/13.sysrst_ctrl_alert_test.4086431520 May 09 12:28:45 PM PDT 24 May 09 12:28:49 PM PDT 24 2022562765 ps
T224 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3063642276 May 09 12:29:13 PM PDT 24 May 09 12:30:51 PM PDT 24 80119444798 ps
T150 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2140503554 May 09 12:32:20 PM PDT 24 May 09 12:32:53 PM PDT 24 115563007989 ps
T147 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.1689063946 May 09 12:32:03 PM PDT 24 May 09 12:32:19 PM PDT 24 2884547717 ps
T177 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2857904322 May 09 12:31:04 PM PDT 24 May 09 12:31:10 PM PDT 24 2059060766 ps
T113 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.495992882 May 09 12:30:18 PM PDT 24 May 09 12:32:11 PM PDT 24 87774002979 ps
T178 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1174533896 May 09 12:28:48 PM PDT 24 May 09 12:28:52 PM PDT 24 2335364455 ps
T114 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1343521696 May 09 12:30:49 PM PDT 24 May 09 12:31:31 PM PDT 24 124195035778 ps
T179 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3609855892 May 09 12:31:53 PM PDT 24 May 09 12:32:03 PM PDT 24 2632364965 ps
T152 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3001551181 May 09 12:30:32 PM PDT 24 May 09 12:30:47 PM PDT 24 3498282613 ps
T180 /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.4050502996 May 09 12:27:19 PM PDT 24 May 09 12:27:25 PM PDT 24 2178511623 ps
T181 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.824887634 May 09 12:28:52 PM PDT 24 May 09 12:28:57 PM PDT 24 2130157116 ps
T130 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1760512773 May 09 12:29:57 PM PDT 24 May 09 12:30:03 PM PDT 24 2852523390 ps
T213 /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1683623855 May 09 12:30:59 PM PDT 24 May 09 12:32:25 PM PDT 24 132604129140 ps
T153 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.8092756 May 09 12:32:11 PM PDT 24 May 09 12:33:05 PM PDT 24 22101053230 ps
T370 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.858109464 May 09 12:28:47 PM PDT 24 May 09 12:28:50 PM PDT 24 2126690762 ps
T266 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3933448920 May 09 12:29:40 PM PDT 24 May 09 12:29:53 PM PDT 24 3404331483 ps
T278 /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1746811619 May 09 12:30:56 PM PDT 24 May 09 12:31:02 PM PDT 24 5976292551 ps
T300 /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1378354112 May 09 12:29:20 PM PDT 24 May 09 12:30:23 PM PDT 24 91986699445 ps
T371 /workspace/coverage/default/7.sysrst_ctrl_alert_test.1975913202 May 09 12:30:21 PM PDT 24 May 09 12:30:29 PM PDT 24 2016388321 ps
T182 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1894273108 May 09 12:27:51 PM PDT 24 May 09 12:27:54 PM PDT 24 4683986743 ps
T372 /workspace/coverage/default/37.sysrst_ctrl_alert_test.1260871338 May 09 12:32:20 PM PDT 24 May 09 12:32:30 PM PDT 24 2026486719 ps
T373 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1412531672 May 09 12:29:49 PM PDT 24 May 09 12:29:52 PM PDT 24 5045955027 ps
T374 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2692944265 May 09 12:30:12 PM PDT 24 May 09 12:30:25 PM PDT 24 3447821958 ps
T375 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.615960136 May 09 12:30:49 PM PDT 24 May 09 12:30:56 PM PDT 24 2651328319 ps
T376 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.425297348 May 09 12:30:12 PM PDT 24 May 09 12:30:25 PM PDT 24 3996654275 ps
T74 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3754138376 May 09 12:30:21 PM PDT 24 May 09 12:32:44 PM PDT 24 51710436309 ps
T377 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3866459701 May 09 12:30:50 PM PDT 24 May 09 12:31:45 PM PDT 24 40503049554 ps
T378 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1598668296 May 09 12:29:57 PM PDT 24 May 09 12:30:07 PM PDT 24 3176994346 ps
T379 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2512016970 May 09 12:29:38 PM PDT 24 May 09 12:29:43 PM PDT 24 2497716912 ps
T157 /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1991605399 May 09 12:30:03 PM PDT 24 May 09 12:32:12 PM PDT 24 65542050288 ps
T243 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.973912153 May 09 12:29:40 PM PDT 24 May 09 12:30:00 PM PDT 24 749707815792 ps
T214 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1620970000 May 09 12:30:56 PM PDT 24 May 09 12:34:28 PM PDT 24 174144215072 ps
T380 /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2867329883 May 09 12:30:49 PM PDT 24 May 09 12:31:01 PM PDT 24 2734332452 ps
T381 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3693717977 May 09 12:30:01 PM PDT 24 May 09 12:30:05 PM PDT 24 3045440923 ps
T267 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2955450497 May 09 12:30:12 PM PDT 24 May 09 12:30:18 PM PDT 24 3896847356 ps
T382 /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2523257176 May 09 12:31:30 PM PDT 24 May 09 12:31:41 PM PDT 24 2627770838 ps
T268 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.335572151 May 09 12:29:53 PM PDT 24 May 09 12:35:59 PM PDT 24 129013816134 ps
T383 /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4289526366 May 09 12:30:53 PM PDT 24 May 09 12:31:02 PM PDT 24 3846353716 ps
T384 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3464573556 May 09 12:29:16 PM PDT 24 May 09 12:29:23 PM PDT 24 3566157183 ps
T385 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2742135738 May 09 12:30:33 PM PDT 24 May 09 12:30:39 PM PDT 24 10250940043 ps
T386 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2573555896 May 09 12:32:11 PM PDT 24 May 09 12:32:26 PM PDT 24 2109969397 ps
T387 /workspace/coverage/default/28.sysrst_ctrl_smoke.2447518663 May 09 12:31:34 PM PDT 24 May 09 12:31:48 PM PDT 24 2121362433 ps
T304 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.318751093 May 09 12:29:43 PM PDT 24 May 09 12:30:45 PM PDT 24 79246531831 ps
T388 /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.792951753 May 09 12:30:19 PM PDT 24 May 09 12:30:30 PM PDT 24 2509486717 ps
T389 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2112983331 May 09 12:31:30 PM PDT 24 May 09 12:31:43 PM PDT 24 3558308369 ps
T390 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3799834726 May 09 12:29:17 PM PDT 24 May 09 12:29:27 PM PDT 24 2612254786 ps
T391 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1375135101 May 09 12:32:08 PM PDT 24 May 09 12:32:21 PM PDT 24 2523084592 ps
T298 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.3028278902 May 09 12:30:18 PM PDT 24 May 09 12:31:08 PM PDT 24 174746707986 ps
T392 /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1529600829 May 09 12:30:48 PM PDT 24 May 09 12:30:58 PM PDT 24 5262191114 ps
T393 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.1462340317 May 09 12:28:23 PM PDT 24 May 09 12:28:26 PM PDT 24 3141933109 ps
T394 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1161269013 May 09 12:29:10 PM PDT 24 May 09 12:29:15 PM PDT 24 3158844093 ps
T395 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.715963467 May 09 12:30:03 PM PDT 24 May 09 12:30:07 PM PDT 24 8641021668 ps
T123 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.617801062 May 09 12:27:53 PM PDT 24 May 09 12:27:55 PM PDT 24 5944753925 ps
T396 /workspace/coverage/default/19.sysrst_ctrl_smoke.3240702162 May 09 12:29:07 PM PDT 24 May 09 12:29:10 PM PDT 24 2142948086 ps
T274 /workspace/coverage/default/42.sysrst_ctrl_stress_all.147396937 May 09 12:32:02 PM PDT 24 May 09 12:36:41 PM PDT 24 111017194774 ps
T397 /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2263144300 May 09 12:31:35 PM PDT 24 May 09 12:31:57 PM PDT 24 3464743477 ps
T398 /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.1695392524 May 09 12:30:17 PM PDT 24 May 09 12:30:25 PM PDT 24 2168200155 ps
T399 /workspace/coverage/default/36.sysrst_ctrl_alert_test.736000068 May 09 12:30:30 PM PDT 24 May 09 12:30:40 PM PDT 24 2012110385 ps
T400 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3425441313 May 09 12:30:50 PM PDT 24 May 09 12:31:05 PM PDT 24 3343352290 ps
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T279 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.666986161 May 09 12:28:49 PM PDT 24 May 09 12:28:53 PM PDT 24 3524311418 ps
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T277 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.867456628 May 09 12:31:30 PM PDT 24 May 09 12:31:46 PM PDT 24 2512732998 ps
T87 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2748050657 May 09 12:29:08 PM PDT 24 May 09 12:29:44 PM PDT 24 50840838325 ps
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T420 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.453995778 May 09 12:29:27 PM PDT 24 May 09 12:29:36 PM PDT 24 2613222660 ps
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T425 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2731352756 May 09 12:29:16 PM PDT 24 May 09 12:29:21 PM PDT 24 3381064419 ps
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T429 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3427009454 May 09 12:30:37 PM PDT 24 May 09 12:31:57 PM PDT 24 28039265041 ps
T430 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2899105439 May 09 12:30:11 PM PDT 24 May 09 12:30:20 PM PDT 24 2112923756 ps
T431 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3157503367 May 09 12:30:18 PM PDT 24 May 09 12:37:25 PM PDT 24 157016023395 ps
T432 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.1644894122 May 09 12:29:43 PM PDT 24 May 09 12:29:52 PM PDT 24 2254019314 ps
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