Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
886 |
1 |
|
|
T23 |
11 |
|
T24 |
10 |
|
T25 |
12 |
| auto[1] |
934 |
1 |
|
|
T23 |
9 |
|
T24 |
10 |
|
T25 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T23 |
6 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
952 |
1 |
|
|
T23 |
14 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
919 |
1 |
|
|
T23 |
12 |
|
T24 |
7 |
|
T25 |
8 |
| auto[1] |
901 |
1 |
|
|
T23 |
8 |
|
T24 |
13 |
|
T25 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
929 |
1 |
|
|
T23 |
11 |
|
T24 |
8 |
|
T25 |
10 |
| auto[1] |
891 |
1 |
|
|
T23 |
9 |
|
T24 |
12 |
|
T25 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
937 |
1 |
|
|
T23 |
14 |
|
T24 |
9 |
|
T25 |
11 |
| auto[1] |
883 |
1 |
|
|
T23 |
6 |
|
T24 |
11 |
|
T25 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
930 |
1 |
|
|
T23 |
8 |
|
T24 |
9 |
|
T25 |
13 |
| auto[1] |
890 |
1 |
|
|
T23 |
12 |
|
T24 |
11 |
|
T25 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
941 |
1 |
|
|
T23 |
14 |
|
T24 |
9 |
|
T25 |
13 |
| auto[1] |
879 |
1 |
|
|
T23 |
6 |
|
T24 |
11 |
|
T25 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T23 |
6 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
921 |
1 |
|
|
T23 |
14 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
936 |
1 |
|
|
T23 |
14 |
|
T24 |
6 |
|
T25 |
12 |
| auto[1] |
884 |
1 |
|
|
T23 |
6 |
|
T24 |
14 |
|
T25 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T23 |
13 |
|
T24 |
7 |
|
T25 |
9 |
| auto[1] |
911 |
1 |
|
|
T23 |
7 |
|
T24 |
13 |
|
T25 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
925 |
1 |
|
|
T23 |
12 |
|
T24 |
12 |
|
T25 |
7 |
| auto[1] |
895 |
1 |
|
|
T23 |
8 |
|
T24 |
8 |
|
T25 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
911 |
1 |
|
|
T23 |
12 |
|
T24 |
9 |
|
T25 |
12 |
| auto[1] |
909 |
1 |
|
|
T23 |
8 |
|
T24 |
11 |
|
T25 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
907 |
1 |
|
|
T23 |
9 |
|
T24 |
9 |
|
T25 |
10 |
| auto[1] |
913 |
1 |
|
|
T23 |
11 |
|
T24 |
11 |
|
T25 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T23 |
6 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
952 |
1 |
|
|
T23 |
14 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T23 |
9 |
|
T24 |
8 |
|
T25 |
8 |
| auto[1] |
926 |
1 |
|
|
T23 |
11 |
|
T24 |
12 |
|
T25 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T25 |
12 |
| auto[1] |
972 |
1 |
|
|
T23 |
10 |
|
T24 |
13 |
|
T25 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
884 |
1 |
|
|
T23 |
9 |
|
T24 |
7 |
|
T25 |
11 |
| auto[1] |
936 |
1 |
|
|
T23 |
11 |
|
T24 |
13 |
|
T25 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T23 |
9 |
|
T24 |
7 |
|
T25 |
15 |
| auto[1] |
921 |
1 |
|
|
T23 |
11 |
|
T24 |
13 |
|
T25 |
5 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
911 |
1 |
|
|
T23 |
14 |
|
T24 |
9 |
|
T25 |
8 |
| auto[1] |
909 |
1 |
|
|
T23 |
6 |
|
T24 |
11 |
|
T25 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T23 |
8 |
|
T24 |
12 |
|
T25 |
10 |
| auto[1] |
919 |
1 |
|
|
T23 |
12 |
|
T24 |
8 |
|
T25 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
931 |
1 |
|
|
T23 |
11 |
|
T24 |
9 |
|
T25 |
8 |
| auto[1] |
889 |
1 |
|
|
T23 |
9 |
|
T24 |
11 |
|
T25 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T23 |
7 |
|
T24 |
8 |
|
T25 |
12 |
| auto[1] |
914 |
1 |
|
|
T23 |
13 |
|
T24 |
12 |
|
T25 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T23 |
8 |
|
T24 |
11 |
|
T25 |
12 |
| auto[1] |
906 |
1 |
|
|
T23 |
12 |
|
T24 |
9 |
|
T25 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
911 |
1 |
|
|
T23 |
12 |
|
T24 |
9 |
|
T25 |
12 |
| auto[1] |
909 |
1 |
|
|
T23 |
8 |
|
T24 |
11 |
|
T25 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
451 |
1 |
|
|
T23 |
3 |
|
T24 |
3 |
|
T25 |
5 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T25 |
3 |
| auto[1] |
auto[0] |
468 |
1 |
|
|
T23 |
9 |
|
T24 |
4 |
|
T25 |
3 |
| auto[1] |
auto[1] |
458 |
1 |
|
|
T23 |
2 |
|
T24 |
8 |
|
T25 |
9 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T23 |
3 |
|
T24 |
3 |
|
T25 |
8 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T23 |
7 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[0] |
496 |
1 |
|
|
T23 |
8 |
|
T24 |
5 |
|
T25 |
2 |
| auto[1] |
auto[1] |
476 |
1 |
|
|
T23 |
2 |
|
T24 |
8 |
|
T25 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
464 |
1 |
|
|
T23 |
7 |
|
T24 |
4 |
|
T25 |
6 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T25 |
5 |
| auto[1] |
auto[0] |
473 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
5 |
| auto[1] |
auto[1] |
463 |
1 |
|
|
T23 |
4 |
|
T24 |
8 |
|
T25 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
468 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T25 |
9 |
| auto[0] |
auto[1] |
431 |
1 |
|
|
T23 |
5 |
|
T24 |
3 |
|
T25 |
6 |
| auto[1] |
auto[0] |
462 |
1 |
|
|
T23 |
4 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
auto[1] |
459 |
1 |
|
|
T23 |
7 |
|
T24 |
8 |
|
T25 |
1 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
471 |
1 |
|
|
T23 |
11 |
|
T24 |
4 |
|
T25 |
6 |
| auto[0] |
auto[1] |
440 |
1 |
|
|
T23 |
3 |
|
T24 |
5 |
|
T25 |
2 |
| auto[1] |
auto[0] |
470 |
1 |
|
|
T23 |
3 |
|
T24 |
5 |
|
T25 |
7 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T23 |
3 |
|
T24 |
6 |
|
T25 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
445 |
1 |
|
|
T23 |
4 |
|
T24 |
6 |
|
T25 |
6 |
| auto[0] |
auto[1] |
456 |
1 |
|
|
T23 |
4 |
|
T24 |
6 |
|
T25 |
4 |
| auto[1] |
auto[0] |
454 |
1 |
|
|
T23 |
2 |
|
T24 |
4 |
|
T25 |
5 |
| auto[1] |
auto[1] |
465 |
1 |
|
|
T23 |
10 |
|
T24 |
4 |
|
T25 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T23 |
4 |
|
T24 |
3 |
|
T25 |
5 |
| auto[0] |
auto[1] |
475 |
1 |
|
|
T23 |
3 |
|
T24 |
5 |
|
T25 |
7 |
| auto[1] |
auto[0] |
478 |
1 |
|
|
T23 |
9 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
436 |
1 |
|
|
T23 |
4 |
|
T24 |
8 |
|
T25 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
443 |
1 |
|
|
T23 |
4 |
|
T24 |
7 |
|
T25 |
4 |
| auto[0] |
auto[1] |
471 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T25 |
8 |
| auto[1] |
auto[0] |
482 |
1 |
|
|
T23 |
8 |
|
T24 |
5 |
|
T25 |
3 |
| auto[1] |
auto[1] |
424 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T25 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
418 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T25 |
6 |
| auto[0] |
auto[1] |
489 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[0] |
468 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[1] |
445 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
868 |
1 |
|
|
T23 |
6 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
auto[1] |
952 |
1 |
|
|
T23 |
14 |
|
T24 |
10 |
|
T25 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
472 |
1 |
|
|
T23 |
10 |
|
T24 |
3 |
|
T25 |
4 |
| auto[0] |
auto[1] |
459 |
1 |
|
|
T23 |
1 |
|
T24 |
6 |
|
T25 |
4 |
| auto[1] |
auto[0] |
464 |
1 |
|
|
T23 |
4 |
|
T24 |
3 |
|
T25 |
8 |
| auto[1] |
auto[1] |
425 |
1 |
|
|
T23 |
5 |
|
T24 |
8 |
|
T25 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
911 |
1 |
|
|
T23 |
12 |
|
T24 |
9 |
|
T25 |
12 |
| auto[1] |
auto[1] |
909 |
1 |
|
|
T23 |
8 |
|
T24 |
11 |
|
T25 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T25 |
9 |
|
T46 |
13 |
|
T89 |
8 |
| auto[1] |
92 |
1 |
|
|
T25 |
11 |
|
T46 |
7 |
|
T89 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T25 |
7 |
|
T46 |
8 |
|
T89 |
12 |
| auto[1] |
99 |
1 |
|
|
T25 |
13 |
|
T46 |
12 |
|
T89 |
4 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
89 |
1 |
|
|
T25 |
9 |
|
T46 |
8 |
|
T89 |
5 |
| auto[1] |
107 |
1 |
|
|
T25 |
11 |
|
T46 |
12 |
|
T89 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T25 |
13 |
|
T46 |
11 |
|
T89 |
5 |
| auto[1] |
95 |
1 |
|
|
T25 |
7 |
|
T46 |
9 |
|
T89 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T25 |
8 |
|
T46 |
9 |
|
T89 |
7 |
| auto[1] |
97 |
1 |
|
|
T25 |
12 |
|
T46 |
11 |
|
T89 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
93 |
1 |
|
|
T25 |
9 |
|
T46 |
9 |
|
T89 |
7 |
| auto[1] |
103 |
1 |
|
|
T25 |
11 |
|
T46 |
11 |
|
T89 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
106 |
1 |
|
|
T25 |
13 |
|
T46 |
12 |
|
T89 |
7 |
| auto[1] |
90 |
1 |
|
|
T25 |
7 |
|
T46 |
8 |
|
T89 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T25 |
10 |
|
T46 |
11 |
|
T89 |
6 |
| auto[1] |
95 |
1 |
|
|
T25 |
10 |
|
T46 |
9 |
|
T89 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T25 |
10 |
|
T46 |
12 |
|
T89 |
9 |
| auto[1] |
102 |
1 |
|
|
T25 |
10 |
|
T46 |
8 |
|
T89 |
7 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T25 |
10 |
|
T46 |
12 |
|
T89 |
11 |
| auto[1] |
93 |
1 |
|
|
T25 |
10 |
|
T46 |
8 |
|
T89 |
5 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T25 |
10 |
|
T46 |
11 |
|
T89 |
8 |
| auto[1] |
99 |
1 |
|
|
T25 |
10 |
|
T46 |
9 |
|
T89 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
98 |
1 |
|
|
T25 |
9 |
|
T46 |
11 |
|
T89 |
11 |
| auto[1] |
98 |
1 |
|
|
T25 |
11 |
|
T46 |
9 |
|
T89 |
5 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T25 |
11 |
|
T46 |
10 |
|
T89 |
12 |
| auto[1] |
88 |
1 |
|
|
T25 |
9 |
|
T46 |
10 |
|
T89 |
4 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
96 |
1 |
|
|
T25 |
7 |
|
T46 |
8 |
|
T89 |
11 |
| auto[1] |
100 |
1 |
|
|
T25 |
13 |
|
T46 |
12 |
|
T89 |
5 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T25 |
8 |
|
T46 |
7 |
|
T89 |
14 |
| auto[1] |
93 |
1 |
|
|
T25 |
12 |
|
T46 |
13 |
|
T89 |
2 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T25 |
8 |
|
T46 |
10 |
|
T89 |
14 |
| auto[1] |
97 |
1 |
|
|
T25 |
12 |
|
T46 |
10 |
|
T89 |
2 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
107 |
1 |
|
|
T25 |
7 |
|
T46 |
5 |
|
T89 |
13 |
| auto[1] |
89 |
1 |
|
|
T25 |
13 |
|
T46 |
15 |
|
T89 |
3 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T25 |
10 |
|
T46 |
9 |
|
T89 |
13 |
| auto[1] |
85 |
1 |
|
|
T25 |
10 |
|
T46 |
11 |
|
T89 |
3 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T25 |
8 |
|
T46 |
11 |
|
T89 |
12 |
| auto[1] |
92 |
1 |
|
|
T25 |
12 |
|
T46 |
9 |
|
T89 |
4 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
93 |
1 |
|
|
T25 |
7 |
|
T46 |
10 |
|
T89 |
11 |
| auto[1] |
103 |
1 |
|
|
T25 |
13 |
|
T46 |
10 |
|
T89 |
5 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
107 |
1 |
|
|
T25 |
12 |
|
T46 |
11 |
|
T89 |
14 |
| auto[1] |
89 |
1 |
|
|
T25 |
8 |
|
T46 |
9 |
|
T89 |
2 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T25 |
13 |
|
T46 |
9 |
|
T89 |
13 |
| auto[1] |
97 |
1 |
|
|
T25 |
7 |
|
T46 |
11 |
|
T89 |
3 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T25 |
9 |
|
T46 |
10 |
|
T89 |
12 |
| auto[1] |
93 |
1 |
|
|
T25 |
11 |
|
T46 |
10 |
|
T89 |
4 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T25 |
9 |
|
T46 |
11 |
|
T89 |
10 |
| auto[1] |
99 |
1 |
|
|
T25 |
11 |
|
T46 |
9 |
|
T89 |
6 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T25 |
3 |
|
T46 |
4 |
|
T89 |
4 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T25 |
5 |
|
T46 |
3 |
|
T89 |
10 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T25 |
6 |
|
T46 |
4 |
|
T89 |
1 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T25 |
6 |
|
T46 |
9 |
|
T89 |
1 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
49 |
1 |
|
|
T25 |
5 |
|
T46 |
7 |
|
T89 |
4 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T25 |
3 |
|
T46 |
3 |
|
T89 |
10 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T25 |
8 |
|
T46 |
4 |
|
T89 |
1 |
| auto[1] |
auto[1] |
45 |
1 |
|
|
T25 |
4 |
|
T46 |
6 |
|
T89 |
1 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
54 |
1 |
|
|
T25 |
4 |
|
T46 |
3 |
|
T89 |
4 |
| auto[0] |
auto[1] |
53 |
1 |
|
|
T25 |
3 |
|
T46 |
2 |
|
T89 |
9 |
| auto[1] |
auto[0] |
45 |
1 |
|
|
T25 |
4 |
|
T46 |
6 |
|
T89 |
3 |
| auto[1] |
auto[1] |
44 |
1 |
|
|
T25 |
9 |
|
T46 |
9 |
|
T203 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T25 |
6 |
|
T46 |
5 |
|
T89 |
4 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T25 |
4 |
|
T46 |
4 |
|
T89 |
9 |
| auto[1] |
auto[0] |
40 |
1 |
|
|
T25 |
3 |
|
T46 |
4 |
|
T89 |
3 |
| auto[1] |
auto[1] |
45 |
1 |
|
|
T25 |
7 |
|
T46 |
7 |
|
T203 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T25 |
7 |
|
T46 |
6 |
|
T89 |
5 |
| auto[0] |
auto[1] |
51 |
1 |
|
|
T25 |
1 |
|
T46 |
5 |
|
T89 |
7 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T25 |
6 |
|
T46 |
6 |
|
T89 |
2 |
| auto[1] |
auto[1] |
39 |
1 |
|
|
T25 |
6 |
|
T46 |
3 |
|
T89 |
2 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T25 |
5 |
|
T46 |
5 |
|
T89 |
4 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T25 |
2 |
|
T46 |
5 |
|
T89 |
7 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T25 |
5 |
|
T46 |
6 |
|
T89 |
2 |
| auto[1] |
auto[1] |
47 |
1 |
|
|
T25 |
8 |
|
T46 |
4 |
|
T89 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
54 |
1 |
|
|
T25 |
6 |
|
T46 |
5 |
|
T89 |
9 |
| auto[0] |
auto[1] |
45 |
1 |
|
|
T25 |
7 |
|
T46 |
4 |
|
T89 |
4 |
| auto[1] |
auto[0] |
49 |
1 |
|
|
T25 |
4 |
|
T46 |
7 |
|
T89 |
2 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T25 |
3 |
|
T46 |
4 |
|
T89 |
1 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T25 |
4 |
|
T46 |
5 |
|
T89 |
7 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T25 |
5 |
|
T46 |
5 |
|
T89 |
5 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T25 |
6 |
|
T46 |
6 |
|
T89 |
1 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T25 |
5 |
|
T46 |
4 |
|
T89 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
54 |
1 |
|
|
T25 |
5 |
|
T46 |
6 |
|
T89 |
6 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T25 |
6 |
|
T46 |
4 |
|
T89 |
6 |
| auto[1] |
auto[0] |
50 |
1 |
|
|
T25 |
4 |
|
T46 |
7 |
|
T89 |
2 |
| auto[1] |
auto[1] |
38 |
1 |
|
|
T25 |
5 |
|
T46 |
3 |
|
T89 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
96 |
1 |
|
|
T25 |
7 |
|
T46 |
8 |
|
T89 |
11 |
| auto[1] |
auto[1] |
99 |
1 |
|
|
T25 |
13 |
|
T46 |
12 |
|
T89 |
4 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
44 |
1 |
|
|
T25 |
4 |
|
T46 |
7 |
|
T89 |
8 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T25 |
8 |
|
T46 |
4 |
|
T89 |
6 |
| auto[1] |
auto[0] |
50 |
1 |
|
|
T25 |
6 |
|
T46 |
5 |
|
T89 |
1 |
| auto[1] |
auto[1] |
39 |
1 |
|
|
T25 |
2 |
|
T46 |
4 |
|
T89 |
1 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
97 |
1 |
|
|
T25 |
9 |
|
T46 |
11 |
|
T89 |
10 |
| auto[1] |
auto[1] |
98 |
1 |
|
|
T25 |
11 |
|
T46 |
9 |
|
T89 |
5 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
25 |
1 |
|
|
T181 |
11 |
|
T310 |
7 |
|
T311 |
7 |
| auto[1] |
35 |
1 |
|
|
T181 |
9 |
|
T310 |
13 |
|
T311 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
32 |
1 |
|
|
T181 |
11 |
|
T310 |
10 |
|
T311 |
11 |
| auto[1] |
28 |
1 |
|
|
T181 |
9 |
|
T310 |
10 |
|
T311 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T181 |
11 |
|
T310 |
11 |
|
T311 |
7 |
| auto[1] |
31 |
1 |
|
|
T181 |
9 |
|
T310 |
9 |
|
T311 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
26 |
1 |
|
|
T181 |
12 |
|
T310 |
7 |
|
T311 |
7 |
| auto[1] |
34 |
1 |
|
|
T181 |
8 |
|
T310 |
13 |
|
T311 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
32 |
1 |
|
|
T181 |
12 |
|
T310 |
13 |
|
T311 |
7 |
| auto[1] |
28 |
1 |
|
|
T181 |
8 |
|
T310 |
7 |
|
T311 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
27 |
1 |
|
|
T181 |
10 |
|
T310 |
12 |
|
T311 |
5 |
| auto[1] |
33 |
1 |
|
|
T181 |
10 |
|
T310 |
8 |
|
T311 |
15 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T181 |
7 |
|
T310 |
7 |
|
T311 |
15 |
| auto[1] |
31 |
1 |
|
|
T181 |
13 |
|
T310 |
13 |
|
T311 |
5 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T181 |
13 |
|
T310 |
10 |
|
T311 |
10 |
| auto[1] |
27 |
1 |
|
|
T181 |
7 |
|
T310 |
10 |
|
T311 |
10 |