Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.14	99.48	96.86	100.00	99.36	98.93	99.71	92.63

Total tests in report: 910

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
53.51	53.51	71.86	71.86	58.82	58.82	90.30	90.30	5.77	5.77	73.38	73.38	58.96	58.96	15.47	15.47	/workspace/coverage/default/27.sysrst_ctrl_combo_detect.2094350304
70.50	16.99	83.22	11.36	72.35	13.52	92.81	2.51	48.72	42.95	84.66	11.28	76.88	17.92	34.86	19.39	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1140683482
78.81	8.31	90.74	7.52	82.08	9.73	94.86	2.05	63.46	14.74	90.79	6.14	86.80	9.92	42.91	8.04	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4078520819
83.43	4.62	92.76	2.02	84.50	2.43	95.78	0.91	70.51	7.05	92.35	1.55	94.03	7.23	54.08	11.17	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.184748575
86.39	2.96	96.40	3.64	89.94	5.43	97.49	1.71	70.51	0.00	95.93	3.59	95.38	1.35	59.11	5.03	/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2148349953
89.05	2.66	97.70	1.31	91.76	1.82	97.49	0.00	84.62	14.10	97.23	1.29	95.47	0.10	59.11	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.3787144862
90.37	1.32	97.78	0.07	92.92	1.16	98.17	0.68	84.62	0.00	97.34	0.11	95.57	0.10	66.20	7.09	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2937405978
91.53	1.16	98.19	0.41	93.43	0.51	98.17	0.00	88.46	3.85	97.67	0.33	96.53	0.96	68.27	2.07	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1543348218
92.44	0.90	98.25	0.06	93.63	0.20	98.17	0.00	89.10	0.64	97.71	0.04	96.72	0.19	73.46	5.20	/workspace/coverage/default/16.sysrst_ctrl_stress_all.318887142
93.20	0.77	98.26	0.02	93.66	0.03	98.17	0.00	89.10	0.00	97.74	0.04	96.82	0.10	78.66	5.20	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2646667759
93.88	0.68	98.54	0.28	93.93	0.28	98.17	0.00	90.38	1.28	97.86	0.11	97.40	0.58	80.89	2.23	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3408516880
94.36	0.48	98.71	0.17	94.36	0.43	98.17	0.00	92.95	2.56	98.04	0.18	97.40	0.00	80.89	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.731876084
94.66	0.30	98.79	0.07	94.54	0.18	98.17	0.00	92.95	0.00	98.15	0.11	97.40	0.00	82.63	1.73	/workspace/coverage/default/24.sysrst_ctrl_combo_detect.760794343
94.95	0.29	98.79	0.00	94.57	0.03	99.77	1.60	92.95	0.00	98.15	0.00	97.50	0.10	82.91	0.28	/workspace/coverage/default/2.sysrst_ctrl_sec_cm.1349339678
95.21	0.26	98.79	0.00	94.57	0.00	99.77	0.00	92.95	0.00	98.15	0.00	97.50	0.00	84.75	1.84	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.340712906
95.47	0.26	98.86	0.07	94.64	0.08	99.77	0.00	94.23	1.28	98.23	0.07	97.78	0.29	84.75	0.00	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.1032405355
95.72	0.26	98.99	0.13	94.69	0.05	99.77	0.00	95.51	1.28	98.30	0.07	97.98	0.19	84.80	0.06	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.566920138
95.97	0.25	99.07	0.07	94.74	0.05	99.77	0.00	96.79	1.28	98.37	0.07	98.17	0.19	84.86	0.06	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.456719953
96.15	0.18	99.10	0.04	94.84	0.10	99.77	0.00	97.44	0.64	98.41	0.04	98.36	0.19	85.14	0.28	/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.956830866
96.31	0.16	99.14	0.04	94.84	0.00	99.77	0.00	97.44	0.00	98.48	0.07	98.36	0.00	86.15	1.01	/workspace/coverage/default/25.sysrst_ctrl_stress_all.198021956
96.46	0.14	99.14	0.00	94.94	0.10	99.77	0.00	97.44	0.00	98.48	0.00	98.94	0.58	86.48	0.34	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.418992450
96.60	0.14	99.14	0.00	95.88	0.94	99.77	0.00	97.44	0.00	98.48	0.00	98.94	0.00	86.54	0.06	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4250319807
96.74	0.14	99.18	0.04	95.96	0.08	99.77	0.00	98.08	0.64	98.52	0.04	99.13	0.19	86.54	0.00	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.4073724305
96.87	0.13	99.23	0.06	95.98	0.03	99.77	0.00	98.72	0.64	98.60	0.07	99.23	0.10	86.54	0.00	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.4050962110
96.99	0.12	99.27	0.04	96.01	0.03	99.77	0.00	99.36	0.64	98.63	0.04	99.33	0.10	86.54	0.00	/workspace/coverage/default/8.sysrst_ctrl_stress_all.2640044178
97.10	0.12	99.29	0.02	96.03	0.03	99.77	0.00	99.36	0.00	98.63	0.00	99.33	0.00	87.32	0.78	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1522369818
97.20	0.10	99.29	0.00	96.03	0.00	99.77	0.00	99.36	0.00	98.63	0.00	99.33	0.00	87.99	0.67	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.541511514
97.28	0.08	99.29	0.00	96.03	0.00	99.77	0.00	99.36	0.00	98.63	0.00	99.33	0.00	88.55	0.56	/workspace/coverage/default/15.sysrst_ctrl_combo_detect.1390829816
97.35	0.07	99.29	0.00	96.33	0.30	99.77	0.00	99.36	0.00	98.63	0.00	99.42	0.10	88.66	0.11	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1040910023
97.42	0.07	99.33	0.04	96.49	0.15	99.77	0.00	99.36	0.00	98.71	0.07	99.61	0.19	88.66	0.00	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.527160246
97.48	0.06	99.33	0.00	96.49	0.00	99.77	0.00	99.36	0.00	98.71	0.00	99.61	0.00	89.11	0.45	/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.4089047827
97.54	0.06	99.38	0.06	96.56	0.08	100.00	0.23	99.36	0.00	98.74	0.04	99.61	0.00	89.11	0.00	/workspace/coverage/default/8.sysrst_ctrl_alert_test.1754378026
97.59	0.05	99.40	0.02	96.59	0.03	100.00	0.00	99.36	0.00	98.78	0.04	99.61	0.00	89.39	0.28	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.643386054
97.63	0.04	99.40	0.00	96.59	0.00	100.00	0.00	99.36	0.00	98.78	0.00	99.61	0.00	89.66	0.28	/workspace/coverage/default/11.sysrst_ctrl_combo_detect.388550890
97.67	0.04	99.40	0.00	96.59	0.00	100.00	0.00	99.36	0.00	98.78	0.00	99.61	0.00	89.94	0.28	/workspace/coverage/default/41.sysrst_ctrl_combo_detect.150588874
97.70	0.03	99.40	0.00	96.71	0.13	100.00	0.00	99.36	0.00	98.78	0.00	99.61	0.00	90.06	0.11	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1987516754
97.74	0.03	99.40	0.00	96.71	0.00	100.00	0.00	99.36	0.00	98.78	0.00	99.61	0.00	90.28	0.22	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.4258273412
97.77	0.03	99.40	0.00	96.71	0.00	100.00	0.00	99.36	0.00	98.78	0.00	99.61	0.00	90.50	0.22	/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.287432342
97.79	0.03	99.42	0.02	96.74	0.03	100.00	0.00	99.36	0.00	98.82	0.04	99.71	0.10	90.50	0.00	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2833571735
97.82	0.02	99.42	0.00	96.74	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	90.67	0.17	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2747341397
97.84	0.02	99.42	0.00	96.74	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	90.84	0.17	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2185060320
97.86	0.02	99.42	0.00	96.74	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.01	0.17	/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3597723706
97.88	0.02	99.42	0.00	96.81	0.08	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.06	0.06	/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1029721250
97.90	0.02	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.17	0.11	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2481099888
97.92	0.02	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.28	0.11	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2744857125
97.93	0.02	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.40	0.11	/workspace/coverage/default/28.sysrst_ctrl_combo_detect.3806576451
97.95	0.02	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.51	0.11	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.976825843
97.96	0.02	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.62	0.11	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.3798384178
97.98	0.02	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.73	0.11	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1833393234
98.00	0.02	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.84	0.11	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.1004534574
98.01	0.02	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	91.96	0.11	/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.743370494
98.02	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.01	0.06	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3211071522
98.03	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.07	0.06	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2628588879
98.04	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.12	0.06	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.2783031787
98.04	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.18	0.06	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2300832650
98.05	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.23	0.06	/workspace/coverage/default/19.sysrst_ctrl_combo_detect.318948028
98.06	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.29	0.06	/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3303558683
98.07	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.35	0.06	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3259712034
98.08	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.40	0.06	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3166764636
98.08	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.46	0.06	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.420021460
98.09	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.51	0.06	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2897718971
98.10	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.57	0.06	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3226591715
98.11	0.01	99.42	0.00	96.81	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.71	0.00	92.63	0.06	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.4054404491
98.11	0.01	99.44	0.02	96.81	0.00	100.00	0.00	99.36	0.00	98.85	0.04	99.71	0.00	92.63	0.00	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2320063378
98.12	0.01	99.46	0.02	96.81	0.00	100.00	0.00	99.36	0.00	98.89	0.04	99.71	0.00	92.63	0.00	/workspace/coverage/default/2.sysrst_ctrl_edge_detect.3936269690
98.13	0.01	99.48	0.02	96.81	0.00	100.00	0.00	99.36	0.00	98.93	0.04	99.71	0.00	92.63	0.00	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.3805231221
98.13	0.01	99.48	0.00	96.84	0.03	100.00	0.00	99.36	0.00	98.93	0.00	99.71	0.00	92.63	0.00	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.224945641

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2055723117
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4101860067
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3417014442
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1412357445
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2301503240
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1110759564
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2888600436
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3583289990
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2606251749
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1885071976
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2507008833
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3680052522
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3392461327
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2118607150
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1927924088
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.664600951
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2349432397
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2066098883
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2832809671
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2587806065
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2676685809
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.160958960
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.535224083
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1932486387
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3105004066
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.454852517
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1695662814
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2446979468
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1021492215
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2744568066
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3499411423
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2003261760
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3486430312
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2539804585
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2260892629
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.546081074
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.4191026856
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2473738446
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2389149941
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3081860696
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2142538515
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3469575070
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3445611521
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3023904815
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4285844188
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1217619727
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1101267725
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1185461394
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3210380039
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2849470880
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/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2042820423
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.617389300
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1954603123
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1124506451
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.2606939879
/workspace/coverage/default/4.sysrst_ctrl_smoke.218606515
/workspace/coverage/default/4.sysrst_ctrl_stress_all.3624865622
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1485311635
/workspace/coverage/default/40.sysrst_ctrl_alert_test.2709086870
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1507077507
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.2107794235
/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1354682672
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3489065868
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.1052866614
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.339601852
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1298376308
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.22095753
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1167071143
/workspace/coverage/default/40.sysrst_ctrl_smoke.2912500427
/workspace/coverage/default/40.sysrst_ctrl_stress_all.3899619763
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1553904505
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2417924526
/workspace/coverage/default/41.sysrst_ctrl_alert_test.1948028171
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.13648866
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1638547581
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1077891470
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.654155160
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2313418505
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.549761924
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1833417828
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.635357483
/workspace/coverage/default/41.sysrst_ctrl_smoke.2567790748
/workspace/coverage/default/41.sysrst_ctrl_stress_all.593322298
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2353233272
/workspace/coverage/default/42.sysrst_ctrl_alert_test.1827388215
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.53075893
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.3994818365
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3389759038
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2568015880
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.69512444
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.330477592
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.514602472
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3374306682
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2058725926
/workspace/coverage/default/42.sysrst_ctrl_smoke.2962868462
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1239981069
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.4005911318
/workspace/coverage/default/43.sysrst_ctrl_alert_test.515508877
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.563246781
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.800372518
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3534817640
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.597113114
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2951021449
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.324357263
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3923791368
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2100981688
/workspace/coverage/default/43.sysrst_ctrl_smoke.410107040
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1955984677
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.697969091
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.740050213
/workspace/coverage/default/44.sysrst_ctrl_alert_test.338245607
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1470827449
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2198740446
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1777311616
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4193546805
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2573276131
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2269221884
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3279977686
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.976722869
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.298001321
/workspace/coverage/default/44.sysrst_ctrl_smoke.2970040406
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2955174683
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.680517993
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2744507368
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4096044831
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1472318452
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3551169018
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2239748997
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.799708022
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3387275222
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.177880365
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3906476588
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1118775986
/workspace/coverage/default/45.sysrst_ctrl_smoke.3416702427
/workspace/coverage/default/45.sysrst_ctrl_stress_all.3080836185
/workspace/coverage/default/46.sysrst_ctrl_alert_test.2493709853
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.4143851723
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.930164408
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2582026760
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.695284534
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2459463799
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2572552018
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1548246877
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1403045405
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.590668072
/workspace/coverage/default/46.sysrst_ctrl_smoke.3785734928
/workspace/coverage/default/46.sysrst_ctrl_stress_all.944480897
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1207163220
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1677010463
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1346313982
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2779005263
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2591358596
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3985879501
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1861490338
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.844206872
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3631543449
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1963173389
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1118146660
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1192221593
/workspace/coverage/default/47.sysrst_ctrl_smoke.1741103232
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2861582433
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3669550629
/workspace/coverage/default/48.sysrst_ctrl_alert_test.4055190036
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2143998842
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.42207315
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1693427066
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.144176905
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1375542234
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3627652695
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2638615528
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3448032958
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1706877116
/workspace/coverage/default/48.sysrst_ctrl_smoke.32365820
/workspace/coverage/default/48.sysrst_ctrl_stress_all.446356608
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.107758329
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1795803355
/workspace/coverage/default/49.sysrst_ctrl_alert_test.4037680509
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.693385483
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.292217668
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3020583436
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.430991486
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3613544537
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2223601736
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1597849907
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1035589129
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1130424128
/workspace/coverage/default/49.sysrst_ctrl_smoke.333099658
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2163565423
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3363400392
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.76203703
/workspace/coverage/default/5.sysrst_ctrl_alert_test.3152025197
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.769225048
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.1764707140
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2659398858
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1858499896
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1731194074
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.4035318646
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3714012335
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.532813247
/workspace/coverage/default/5.sysrst_ctrl_smoke.904756016
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3755294553
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3712477593
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.148127876
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.279199906
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1914005275
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1203781497
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.760735090
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.332459113
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3451150989
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1537740682
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2954944125
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1087752491
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2491273240
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1712673098
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1371133326
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1474169212
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2857400183
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3959267838
/workspace/coverage/default/6.sysrst_ctrl_smoke.697223051
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1111098334
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.944591315
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1218734664
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.616768939
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3199044647
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.544066559
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3733373928
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2392865207
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1561067264
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.940910878
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2448568975
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.258911579
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.2459959162
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2392849705
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1958633053
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.349911078
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1019505376
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.4012950396
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.100036545
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2523069626
/workspace/coverage/default/7.sysrst_ctrl_smoke.136945407
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2242466895
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.892942033
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1028537262
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1573707535
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.4058628483
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3450292481
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2504654413
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1123277525
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.480295417
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.201410348
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2228831662
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3803257531
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.415777132
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2057725197
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3552977330
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2389331
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3704554040
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1701323636
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2709129086
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3838966194
/workspace/coverage/default/8.sysrst_ctrl_smoke.4128556120
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2388328185
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3674035095
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.270198355
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2534142671
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.205749780
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1217957437
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3924682843
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3296481463
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.242531270
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2045525915
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2375290431
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.597040094
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.4097910096
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2683761105
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.442072287
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1619103698
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3749282176
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1405310580
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.35756424
/workspace/coverage/default/9.sysrst_ctrl_smoke.2126942344
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2716437369
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3525998048
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2037023815
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3052780299
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2979746111
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.176106435
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2998611150
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3222255669
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.4012810698
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1331961772
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.977737823

Total test records in report: 910

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/27.sysrst_ctrl_combo_detect.2094350304	May 12 01:42:29 PM PDT 24	May 12 01:47:53 PM PDT 24	129159444490 ps
T5	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1187962723	May 12 01:41:51 PM PDT 24	May 12 01:42:42 PM PDT 24	22088271681 ps
T6	/workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.472894609	May 12 01:42:49 PM PDT 24	May 12 01:42:55 PM PDT 24	3260844321 ps
T13	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.104683672	May 12 01:42:16 PM PDT 24	May 12 01:43:22 PM PDT 24	25337258802 ps
T2	/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3208698997	May 12 01:42:34 PM PDT 24	May 12 01:42:37 PM PDT 24	5493596576 ps
T14	/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.1474259000	May 12 01:42:26 PM PDT 24	May 12 01:42:27 PM PDT 24	2140238533 ps
T15	/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.4243877751	May 12 01:42:40 PM PDT 24	May 12 01:42:42 PM PDT 24	2543621407 ps
T16	/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2148349953	May 12 01:41:54 PM PDT 24	May 12 01:42:01 PM PDT 24	2511234303 ps
T17	/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1914005275	May 12 01:43:23 PM PDT 24	May 12 01:44:00 PM PDT 24	26840151062 ps
T18	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2959810840	May 12 01:41:44 PM PDT 24	May 12 01:41:51 PM PDT 24	2511240606 ps
T48	/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2245468978	May 12 01:42:44 PM PDT 24	May 12 01:42:47 PM PDT 24	2524182944 ps
T3	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.456719953	May 12 01:41:08 PM PDT 24	May 12 01:41:18 PM PDT 24	2983161689 ps
T70	/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2849675115	May 12 01:42:36 PM PDT 24	May 12 01:42:44 PM PDT 24	2514578434 ps
T72	/workspace/coverage/default/8.sysrst_ctrl_alert_test.1754378026	May 12 01:41:40 PM PDT 24	May 12 01:41:47 PM PDT 24	2015947251 ps
T4	/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.467727119	May 12 01:41:43 PM PDT 24	May 12 01:41:51 PM PDT 24	9685622866 ps
T73	/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.363344160	May 12 01:41:18 PM PDT 24	May 12 01:41:25 PM PDT 24	2201858012 ps
T59	/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1774359407	May 12 01:41:55 PM PDT 24	May 12 01:42:03 PM PDT 24	7786882167 ps
T7	/workspace/coverage/default/27.sysrst_ctrl_edge_detect.4090051825	May 12 01:42:28 PM PDT 24	May 12 01:42:30 PM PDT 24	4250686833 ps
T55	/workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2234361183	May 12 01:42:16 PM PDT 24	May 12 01:42:17 PM PDT 24	3079322990 ps
T71	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.635120930	May 12 01:42:23 PM PDT 24	May 12 01:42:31 PM PDT 24	2515737508 ps
T56	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2938107581	May 12 01:41:57 PM PDT 24	May 12 01:42:03 PM PDT 24	3702777666 ps
T8	/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1375542234	May 12 01:43:17 PM PDT 24	May 12 01:43:23 PM PDT 24	3011015513 ps
T60	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1040910023	May 12 01:42:04 PM PDT 24	May 12 01:42:11 PM PDT 24	7088396745 ps
T57	/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.434227582	May 12 01:41:49 PM PDT 24	May 12 01:41:50 PM PDT 24	3199353116 ps
T26	/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.480628172	May 12 01:41:43 PM PDT 24	May 12 01:41:46 PM PDT 24	2659174844 ps
T9	/workspace/coverage/default/38.sysrst_ctrl_edge_detect.2472716569	May 12 01:43:00 PM PDT 24	May 12 01:43:07 PM PDT 24	3643234786 ps
T58	/workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2931018112	May 12 01:42:42 PM PDT 24	May 12 01:42:46 PM PDT 24	2782816203 ps
T23	/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.4012950396	May 12 01:41:32 PM PDT 24	May 12 01:41:39 PM PDT 24	2472192992 ps
T66	/workspace/coverage/default/12.sysrst_ctrl_alert_test.1373130371	May 12 01:41:52 PM PDT 24	May 12 01:41:54 PM PDT 24	2045885663 ps
T10	/workspace/coverage/default/41.sysrst_ctrl_edge_detect.654155160	May 12 01:43:02 PM PDT 24	May 12 01:45:36 PM PDT 24	621135644065 ps
T67	/workspace/coverage/default/39.sysrst_ctrl_smoke.2249918051	May 12 01:42:56 PM PDT 24	May 12 01:43:02 PM PDT 24	2110874927 ps
T11	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.272552896	May 12 01:42:44 PM PDT 24	May 12 01:45:36 PM PDT 24	62372898132 ps
T12	/workspace/coverage/default/24.sysrst_ctrl_combo_detect.760794343	May 12 01:42:21 PM PDT 24	May 12 01:47:06 PM PDT 24	113383939034 ps
T30	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4078520819	May 12 01:43:29 PM PDT 24	May 12 01:44:40 PM PDT 24	102431377758 ps
T68	/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1028601787	May 12 01:42:26 PM PDT 24	May 12 01:42:29 PM PDT 24	2633368797 ps
T69	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.976722869	May 12 01:43:10 PM PDT 24	May 12 01:43:16 PM PDT 24	2046164233 ps
T27	/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1507077507	May 12 01:43:03 PM PDT 24	May 12 01:43:07 PM PDT 24	3830892848 ps
T43	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.292217668	May 12 01:43:24 PM PDT 24	May 12 01:45:43 PM PDT 24	104929492206 ps
T49	/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2683761105	May 12 01:41:39 PM PDT 24	May 12 01:41:49 PM PDT 24	3123475530 ps
T50	/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1218734664	May 12 01:41:29 PM PDT 24	May 12 01:43:47 PM PDT 24	1526781482777 ps
T51	/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3303558683	May 12 01:42:20 PM PDT 24	May 12 01:43:51 PM PDT 24	2073353879454 ps
T31	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.89305632	May 12 01:41:15 PM PDT 24	May 12 01:41:22 PM PDT 24	2355754765 ps
T28	/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1029721250	May 12 01:42:47 PM PDT 24	May 12 01:45:01 PM PDT 24	60274545706 ps
T52	/workspace/coverage/default/13.sysrst_ctrl_smoke.4218893930	May 12 01:41:50 PM PDT 24	May 12 01:41:57 PM PDT 24	2110954004 ps
T32	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.388039039	May 12 01:41:50 PM PDT 24	May 12 01:42:39 PM PDT 24	65186960049 ps
T37	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2582026760	May 12 01:43:15 PM PDT 24	May 12 01:46:42 PM PDT 24	77777088886 ps
T96	/workspace/coverage/default/16.sysrst_ctrl_alert_test.3422926172	May 12 01:42:00 PM PDT 24	May 12 01:42:02 PM PDT 24	2089780015 ps
T29	/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2607291131	May 12 01:42:36 PM PDT 24	May 12 01:42:42 PM PDT 24	3878656335 ps
T130	/workspace/coverage/default/24.sysrst_ctrl_alert_test.3779465874	May 12 01:42:24 PM PDT 24	May 12 01:42:26 PM PDT 24	2040765802 ps
T131	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.984821336	May 12 01:42:05 PM PDT 24	May 12 01:42:08 PM PDT 24	2523780372 ps
T132	/workspace/coverage/default/48.sysrst_ctrl_alert_test.4055190036	May 12 01:43:22 PM PDT 24	May 12 01:43:24 PM PDT 24	2053366314 ps
T133	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.298001321	May 12 01:43:13 PM PDT 24	May 12 01:43:18 PM PDT 24	2515486765 ps
T261	/workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1357318064	May 12 01:41:13 PM PDT 24	May 12 02:05:38 PM PDT 24	1090865759107 ps
T262	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.970331592	May 12 01:42:25 PM PDT 24	May 12 01:42:33 PM PDT 24	2508154474 ps
T389	/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3909627084	May 12 01:42:25 PM PDT 24	May 12 01:42:28 PM PDT 24	2080639552 ps
T390	/workspace/coverage/default/45.sysrst_ctrl_alert_test.2744507368	May 12 01:43:14 PM PDT 24	May 12 01:43:16 PM PDT 24	2092967866 ps
T54	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.420021460	May 12 01:43:06 PM PDT 24	May 12 01:43:30 PM PDT 24	31813405225 ps
T36	/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.4089047827	May 12 01:43:26 PM PDT 24	May 12 01:43:41 PM PDT 24	83339008498 ps
T74	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.566920138	May 12 01:42:08 PM PDT 24	May 12 01:42:26 PM PDT 24	27350662777 ps
T24	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.4067241695	May 12 01:42:26 PM PDT 24	May 12 01:42:28 PM PDT 24	2499281594 ps
T391	/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2042820423	May 12 01:41:19 PM PDT 24	May 12 01:41:26 PM PDT 24	2611887055 ps
T40	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.3484026557	May 12 01:42:36 PM PDT 24	May 12 01:42:39 PM PDT 24	4253771113 ps
T44	/workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.979332034	May 12 01:41:01 PM PDT 24	May 12 01:41:04 PM PDT 24	3217051997 ps
T25	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.184748575	May 12 01:41:56 PM PDT 24	May 12 01:42:41 PM PDT 24	66469213699 ps
T45	/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3498540954	May 12 01:41:57 PM PDT 24	May 12 01:42:07 PM PDT 24	3399162566 ps
T39	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.643386054	May 12 01:43:11 PM PDT 24	May 12 01:45:01 PM PDT 24	43816667344 ps
T22	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1140683482	May 12 01:43:06 PM PDT 24	May 12 01:45:28 PM PDT 24	831073417971 ps
T160	/workspace/coverage/default/44.sysrst_ctrl_smoke.2970040406	May 12 01:43:11 PM PDT 24	May 12 01:43:13 PM PDT 24	2152212677 ps
T42	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2481099888	May 12 01:42:06 PM PDT 24	May 12 01:45:33 PM PDT 24	77355696698 ps
T161	/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1322703322	May 12 01:42:17 PM PDT 24	May 12 01:42:20 PM PDT 24	3082650364 ps
T61	/workspace/coverage/default/15.sysrst_ctrl_stress_all.436684918	May 12 01:41:57 PM PDT 24	May 12 01:42:09 PM PDT 24	17259481610 ps
T162	/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3262591127	May 12 01:42:23 PM PDT 24	May 12 01:42:25 PM PDT 24	2607266739 ps
T163	/workspace/coverage/default/49.sysrst_ctrl_smoke.333099658	May 12 01:43:20 PM PDT 24	May 12 01:43:23 PM PDT 24	2125916221 ps
T107	/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2954944125	May 12 01:41:33 PM PDT 24	May 12 01:43:48 PM PDT 24	161799033184 ps
T134	/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2185217712	May 12 01:42:31 PM PDT 24	May 12 01:42:33 PM PDT 24	2646006174 ps
T135	/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1118775986	May 12 01:43:15 PM PDT 24	May 12 01:43:18 PM PDT 24	2535852644 ps
T75	/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2392865207	May 12 01:43:25 PM PDT 24	May 12 01:44:30 PM PDT 24	24330867166 ps
T76	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.279199906	May 12 01:43:21 PM PDT 24	May 12 01:48:21 PM PDT 24	118888523107 ps
T62	/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1848286546	May 12 01:41:55 PM PDT 24	May 12 01:42:03 PM PDT 24	2459223630 ps
T136	/workspace/coverage/default/30.sysrst_ctrl_alert_test.393252687	May 12 01:42:38 PM PDT 24	May 12 01:42:41 PM PDT 24	2032298848 ps
T46	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2897718971	May 12 01:41:27 PM PDT 24	May 12 01:42:46 PM PDT 24	34805307132 ps
T116	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1087752491	May 12 01:41:33 PM PDT 24	May 12 01:42:38 PM PDT 24	24584389763 ps
T137	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.350487271	May 12 01:42:17 PM PDT 24	May 12 01:42:20 PM PDT 24	2940211993 ps
T392	/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.4267507432	May 12 01:41:24 PM PDT 24	May 12 01:41:29 PM PDT 24	2842809313 ps
T77	/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.680517993	May 12 01:43:10 PM PDT 24	May 12 01:43:14 PM PDT 24	5955588103 ps
T119	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1833393234	May 12 01:42:52 PM PDT 24	May 12 01:51:52 PM PDT 24	190790563849 ps
T138	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3408516880	May 12 01:43:21 PM PDT 24	May 12 01:44:54 PM PDT 24	70679226229 ps
T393	/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1118146660	May 12 01:43:12 PM PDT 24	May 12 01:43:16 PM PDT 24	2229082409 ps
T47	/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.53075893	May 12 01:43:04 PM PDT 24	May 12 01:43:08 PM PDT 24	3374174913 ps
T38	/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2459463799	May 12 01:43:13 PM PDT 24	May 12 01:43:16 PM PDT 24	3660610363 ps
T394	/workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.821579746	May 12 01:41:13 PM PDT 24	May 12 01:41:16 PM PDT 24	2635715566 ps
T395	/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.4196979653	May 12 01:42:48 PM PDT 24	May 12 01:42:52 PM PDT 24	2049047418 ps
T396	/workspace/coverage/default/44.sysrst_ctrl_alert_test.338245607	May 12 01:43:08 PM PDT 24	May 12 01:43:11 PM PDT 24	2022456416 ps
T84	/workspace/coverage/default/2.sysrst_ctrl_sec_cm.1349339678	May 12 01:41:16 PM PDT 24	May 12 01:43:06 PM PDT 24	42014480677 ps
T288	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1371133326	May 12 01:41:28 PM PDT 24	May 12 01:41:29 PM PDT 24	2733853980 ps
T111	/workspace/coverage/default/40.sysrst_ctrl_edge_detect.1052866614	May 12 01:42:58 PM PDT 24	May 12 01:43:03 PM PDT 24	2739544330 ps
T186	/workspace/coverage/default/37.sysrst_ctrl_alert_test.1589104037	May 12 01:42:55 PM PDT 24	May 12 01:42:58 PM PDT 24	2029997011 ps
T187	/workspace/coverage/default/30.sysrst_ctrl_pin_access_test.2965753584	May 12 01:42:36 PM PDT 24	May 12 01:42:43 PM PDT 24	2055754186 ps
T41	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1543348218	May 12 01:41:03 PM PDT 24	May 12 01:45:32 PM PDT 24	1316952878013 ps
T188	/workspace/coverage/default/16.sysrst_ctrl_smoke.3292696892	May 12 01:41:58 PM PDT 24	May 12 01:42:04 PM PDT 24	2112182072 ps
T139	/workspace/coverage/default/16.sysrst_ctrl_combo_detect.367395483	May 12 01:42:00 PM PDT 24	May 12 01:42:40 PM PDT 24	55641187079 ps
T189	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.4054404491	May 12 01:43:25 PM PDT 24	May 12 01:46:50 PM PDT 24	146912719909 ps
T190	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.760735090	May 12 01:43:25 PM PDT 24	May 12 01:44:38 PM PDT 24	110461105880 ps
T141	/workspace/coverage/default/36.sysrst_ctrl_combo_detect.1912239917	May 12 01:42:52 PM PDT 24	May 12 01:46:23 PM PDT 24	163016024357 ps
T191	/workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1005068550	May 12 01:42:45 PM PDT 24	May 12 01:42:48 PM PDT 24	2529797583 ps
T199	/workspace/coverage/default/19.sysrst_ctrl_combo_detect.318948028	May 12 01:42:07 PM PDT 24	May 12 01:44:11 PM PDT 24	200399870591 ps
T200	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3817559166	May 12 01:41:12 PM PDT 24	May 12 01:41:31 PM PDT 24	26611318241 ps
T201	/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1124506451	May 12 01:41:18 PM PDT 24	May 12 01:41:22 PM PDT 24	2516479212 ps
T397	/workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1157176640	May 12 01:42:29 PM PDT 24	May 12 01:42:35 PM PDT 24	2022853762 ps
T398	/workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1806371697	May 12 01:41:09 PM PDT 24	May 12 01:41:18 PM PDT 24	2510437746 ps
T78	/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.320312602	May 12 01:43:00 PM PDT 24	May 12 01:43:02 PM PDT 24	5192648310 ps
T117	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3626430571	May 12 01:41:56 PM PDT 24	May 12 01:43:54 PM PDT 24	294371021197 ps
T399	/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2223601736	May 12 01:43:20 PM PDT 24	May 12 01:43:23 PM PDT 24	2627971474 ps
T79	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1326061291	May 12 01:42:43 PM PDT 24	May 12 01:42:49 PM PDT 24	5768842989 ps
T400	/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1019505376	May 12 01:41:31 PM PDT 24	May 12 01:41:33 PM PDT 24	2638121385 ps
T401	/workspace/coverage/default/15.sysrst_ctrl_alert_test.3030828617	May 12 01:41:57 PM PDT 24	May 12 01:42:03 PM PDT 24	2011304091 ps
T402	/workspace/coverage/default/5.sysrst_ctrl_alert_test.3152025197	May 12 01:41:30 PM PDT 24	May 12 01:41:36 PM PDT 24	2013554240 ps
T254	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.4283074206	May 12 01:42:39 PM PDT 24	May 12 01:42:54 PM PDT 24	21602978657 ps
T63	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.822032549	May 12 01:41:54 PM PDT 24	May 12 01:41:58 PM PDT 24	2462826984 ps
T64	/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2802714685	May 12 01:41:46 PM PDT 24	May 12 01:41:49 PM PDT 24	2470502274 ps
T403	/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.635357483	May 12 01:43:05 PM PDT 24	May 12 01:43:08 PM PDT 24	2527837481 ps
T256	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.332459113	May 12 01:43:26 PM PDT 24	May 12 01:43:44 PM PDT 24	25864133492 ps
T258	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4205106359	May 12 01:41:07 PM PDT 24	May 12 01:41:09 PM PDT 24	2263988264 ps
T404	/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.22095753	May 12 01:42:59 PM PDT 24	May 12 01:43:01 PM PDT 24	2251850546 ps
T304	/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3428676702	May 12 01:42:45 PM PDT 24	May 12 01:42:50 PM PDT 24	2518204445 ps
T405	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.258911579	May 12 01:41:35 PM PDT 24	May 12 01:41:39 PM PDT 24	3520019443 ps
T80	/workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.965738056	May 12 01:41:09 PM PDT 24	May 12 01:41:11 PM PDT 24	11624993181 ps
T406	/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3798176603	May 12 01:42:46 PM PDT 24	May 12 01:42:49 PM PDT 24	2061241334 ps
T407	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3400771457	May 12 01:42:14 PM PDT 24	May 12 01:42:21 PM PDT 24	2510663892 ps
T168	/workspace/coverage/default/15.sysrst_ctrl_edge_detect.2974545057	May 12 01:41:57 PM PDT 24	May 12 01:54:04 PM PDT 24	1209720561661 ps
T291	/workspace/coverage/default/28.sysrst_ctrl_stress_all.3701232015	May 12 01:42:31 PM PDT 24	May 12 01:48:00 PM PDT 24	122679688315 ps
T408	/workspace/coverage/default/0.sysrst_ctrl_smoke.4124988298	May 12 01:40:59 PM PDT 24	May 12 01:41:06 PM PDT 24	2108263175 ps
T169	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.4194571789	May 12 01:42:26 PM PDT 24	May 12 01:42:29 PM PDT 24	4417272034 ps
T307	/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1677010463	May 12 01:43:17 PM PDT 24	May 12 01:43:20 PM PDT 24	7292256033 ps
T305	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3037852269	May 12 01:42:59 PM PDT 24	May 12 01:43:03 PM PDT 24	2518332617 ps
T409	/workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3367651754	May 12 01:42:36 PM PDT 24	May 12 01:42:39 PM PDT 24	3128647081 ps
T65	/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.617389300	May 12 01:41:19 PM PDT 24	May 12 01:41:22 PM PDT 24	2492433556 ps
T81	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2320063378	May 12 01:42:09 PM PDT 24	May 12 01:42:54 PM PDT 24	65634232864 ps
T410	/workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2221669677	May 12 01:41:53 PM PDT 24	May 12 01:42:01 PM PDT 24	2512220419 ps
T411	/workspace/coverage/default/28.sysrst_ctrl_alert_test.2515783925	May 12 01:42:31 PM PDT 24	May 12 01:42:37 PM PDT 24	2009416534 ps
T412	/workspace/coverage/default/4.sysrst_ctrl_smoke.218606515	May 12 01:41:18 PM PDT 24	May 12 01:41:25 PM PDT 24	2114077811 ps
T142	/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4064524488	May 12 01:41:46 PM PDT 24	May 12 01:41:49 PM PDT 24	3623659104 ps
T120	/workspace/coverage/default/16.sysrst_ctrl_stress_all.318887142	May 12 01:41:58 PM PDT 24	May 12 01:49:36 PM PDT 24	165013051634 ps
T275	/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.778365106	May 12 01:42:59 PM PDT 24	May 12 01:43:04 PM PDT 24	2454511537 ps
T276	/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.4231091747	May 12 01:41:01 PM PDT 24	May 12 01:41:09 PM PDT 24	2608223976 ps
T118	/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2163782655	May 12 01:41:52 PM PDT 24	May 12 01:42:02 PM PDT 24	3631126404 ps
T140	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.340712906	May 12 01:42:37 PM PDT 24	May 12 01:43:38 PM PDT 24	243304253933 ps
T277	/workspace/coverage/default/44.sysrst_ctrl_stress_all.2955174683	May 12 01:43:11 PM PDT 24	May 12 01:43:28 PM PDT 24	8502949631 ps
T278	/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3925747213	May 12 01:42:11 PM PDT 24	May 12 01:42:13 PM PDT 24	2538985368 ps
T279	/workspace/coverage/default/31.sysrst_ctrl_smoke.1146294864	May 12 01:42:39 PM PDT 24	May 12 01:42:45 PM PDT 24	2113005610 ps
T280	/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.696506464	May 12 01:41:13 PM PDT 24	May 12 01:41:15 PM PDT 24	3390752050 ps
T281	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3820036361	May 12 01:41:55 PM PDT 24	May 12 01:41:58 PM PDT 24	2626003011 ps
T242	/workspace/coverage/default/42.sysrst_ctrl_stress_all.1239981069	May 12 01:43:06 PM PDT 24	May 12 01:43:16 PM PDT 24	9245699778 ps
T413	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.4091035080	May 12 01:41:11 PM PDT 24	May 12 01:41:18 PM PDT 24	2389913277 ps
T143	/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.884658685	May 12 01:42:45 PM PDT 24	May 12 01:42:49 PM PDT 24	3522363645 ps
T170	/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3916966801	May 12 01:42:46 PM PDT 24	May 12 01:43:34 PM PDT 24	82403655300 ps
T259	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1203781497	May 12 01:43:24 PM PDT 24	May 12 01:47:44 PM PDT 24	105276429983 ps
T306	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.532813247	May 12 01:41:24 PM PDT 24	May 12 01:41:26 PM PDT 24	2542265853 ps
T414	/workspace/coverage/default/47.sysrst_ctrl_alert_test.1346313982	May 12 01:43:17 PM PDT 24	May 12 01:43:24 PM PDT 24	2013655376 ps
T415	/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2577199376	May 12 01:42:10 PM PDT 24	May 12 01:42:18 PM PDT 24	2611201833 ps
T416	/workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3200130922	May 12 01:41:53 PM PDT 24	May 12 01:42:01 PM PDT 24	2839775646 ps
T260	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3226591715	May 12 01:43:23 PM PDT 24	May 12 01:45:57 PM PDT 24	58281487740 ps
T289	/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.769225048	May 12 01:41:27 PM PDT 24	May 12 01:41:37 PM PDT 24	3654704506 ps
T266	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.2459959162	May 12 01:41:39 PM PDT 24	May 12 01:45:12 PM PDT 24	165547395986 ps
T417	/workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.850560875	May 12 01:42:34 PM PDT 24	May 12 01:42:39 PM PDT 24	2616426082 ps
T290	/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2304922256	May 12 01:41:40 PM PDT 24	May 12 01:41:44 PM PDT 24	3519275527 ps
T418	/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2735431234	May 12 01:42:35 PM PDT 24	May 12 01:42:39 PM PDT 24	3854693983 ps
T419	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2857400183	May 12 01:41:29 PM PDT 24	May 12 01:41:31 PM PDT 24	2276014054 ps
T257	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3886932793	May 12 01:41:24 PM PDT 24	May 12 01:41:35 PM PDT 24	23612094494 ps
T420	/workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3090259011	May 12 01:42:11 PM PDT 24	May 12 01:42:22 PM PDT 24	3829853323 ps
T171	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.2290462928	May 12 01:42:08 PM PDT 24	May 12 01:42:11 PM PDT 24	5193343401 ps
T421	/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2572552018	May 12 01:43:12 PM PDT 24	May 12 01:43:15 PM PDT 24	2623625634 ps
T422	/workspace/coverage/default/47.sysrst_ctrl_smoke.1741103232	May 12 01:43:12 PM PDT 24	May 12 01:43:14 PM PDT 24	2185828417 ps
T423	/workspace/coverage/default/22.sysrst_ctrl_smoke.777567772	May 12 01:42:18 PM PDT 24	May 12 01:42:25 PM PDT 24	2112441323 ps
T424	/workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.4273386003	May 12 01:42:32 PM PDT 24	May 12 01:42:33 PM PDT 24	2541398282 ps
T114	/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3669550629	May 12 01:43:13 PM PDT 24	May 12 01:43:15 PM PDT 24	3598268882 ps
T148	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.338992977	May 12 01:41:45 PM PDT 24	May 12 01:42:11 PM PDT 24	20205635593 ps
T149	/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1062236887	May 12 01:42:31 PM PDT 24	May 12 01:42:37 PM PDT 24	2023100682 ps
T150	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.510983329	May 12 01:41:55 PM PDT 24	May 12 01:43:30 PM PDT 24	71700048231 ps
T151	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3197109241	May 12 01:41:57 PM PDT 24	May 12 01:42:03 PM PDT 24	4092352755 ps
T152	/workspace/coverage/default/48.sysrst_ctrl_stress_all.446356608	May 12 01:43:19 PM PDT 24	May 12 01:43:36 PM PDT 24	12872265593 ps
T153	/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1035589129	May 12 01:43:23 PM PDT 24	May 12 01:43:25 PM PDT 24	2149061597 ps
T154	/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2779005263	May 12 01:43:14 PM PDT 24	May 12 01:43:18 PM PDT 24	3377335533 ps
T155	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1285508392	May 12 01:41:54 PM PDT 24	May 12 01:42:02 PM PDT 24	2610335408 ps
T156	/workspace/coverage/default/42.sysrst_ctrl_smoke.2962868462	May 12 01:43:01 PM PDT 24	May 12 01:43:04 PM PDT 24	2133091908 ps
T425	/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.2737489781	May 12 01:41:41 PM PDT 24	May 12 01:41:47 PM PDT 24	2039571097 ps
T264	/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2228831662	May 12 01:43:24 PM PDT 24	May 12 01:45:01 PM PDT 24	85590777811 ps
T180	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.4050962110	May 12 01:41:52 PM PDT 24	May 12 01:42:04 PM PDT 24	3856970743 ps
T245	/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.4133866088	May 12 01:41:55 PM PDT 24	May 12 01:41:57 PM PDT 24	2309843255 ps
T246	/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1174157584	May 12 01:42:42 PM PDT 24	May 12 01:42:44 PM PDT 24	2177574480 ps
T247	/workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.738821087	May 12 01:42:58 PM PDT 24	May 12 01:43:03 PM PDT 24	4936869563 ps
T248	/workspace/coverage/default/31.sysrst_ctrl_alert_test.1264397806	May 12 01:42:44 PM PDT 24	May 12 01:42:48 PM PDT 24	2025764676 ps
T249	/workspace/coverage/default/24.sysrst_ctrl_stress_all.3545101218	May 12 01:42:24 PM PDT 24	May 12 01:43:08 PM PDT 24	99001082402 ps
T250	/workspace/coverage/default/23.sysrst_ctrl_smoke.978470897	May 12 01:42:20 PM PDT 24	May 12 01:42:26 PM PDT 24	2113038267 ps
T251	/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3906476588	May 12 01:43:15 PM PDT 24	May 12 01:43:18 PM PDT 24	2240506614 ps
T121	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.2455103398	May 12 01:42:37 PM PDT 24	May 12 01:43:39 PM PDT 24	140882587891 ps
T252	/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2057725197	May 12 01:41:36 PM PDT 24	May 12 01:42:24 PM PDT 24	65588789935 ps
T426	/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.852524199	May 12 01:42:45 PM PDT 24	May 12 01:42:48 PM PDT 24	2481806771 ps
T427	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.339601852	May 12 01:43:01 PM PDT 24	May 12 01:43:05 PM PDT 24	2616356483 ps
T428	/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2779972755	May 12 01:42:38 PM PDT 24	May 12 01:42:43 PM PDT 24	3518508944 ps
T301	/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.4288619575	May 12 01:42:19 PM PDT 24	May 12 01:42:22 PM PDT 24	2486746487 ps
T429	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3387275222	May 12 01:43:15 PM PDT 24	May 12 01:43:25 PM PDT 24	2610896040 ps
T302	/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3203777331	May 12 01:42:08 PM PDT 24	May 12 01:42:11 PM PDT 24	2497591140 ps
T430	/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1130424128	May 12 01:43:24 PM PDT 24	May 12 01:43:27 PM PDT 24	2530970935 ps
T431	/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.616770358	May 12 01:42:31 PM PDT 24	May 12 01:42:39 PM PDT 24	2509843559 ps
T303	/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1200004983	May 12 01:42:36 PM PDT 24	May 12 01:42:39 PM PDT 24	2492750532 ps
T432	/workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.845431252	May 12 01:42:54 PM PDT 24	May 12 01:42:57 PM PDT 24	4144941035 ps
T433	/workspace/coverage/default/42.sysrst_ctrl_alert_test.1827388215	May 12 01:43:05 PM PDT 24	May 12 01:43:07 PM PDT 24	2026679050 ps
T157	/workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.500439235	May 12 01:42:09 PM PDT 24	May 12 01:42:16 PM PDT 24	5354670754 ps
T198	/workspace/coverage/default/37.sysrst_ctrl_edge_detect.1167692048	May 12 01:42:56 PM PDT 24	May 12 01:42:59 PM PDT 24	2432632366 ps
T208	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.892942033	May 12 01:41:40 PM PDT 24	May 12 01:41:56 PM PDT 24	28104001288 ps
T255	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.715858740	May 12 01:42:30 PM PDT 24	May 12 01:45:11 PM PDT 24	60080508547 ps
T312	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3246486001	May 12 01:42:07 PM PDT 24	May 12 01:42:16 PM PDT 24	2512510733 ps
T313	/workspace/coverage/default/27.sysrst_ctrl_alert_test.2694763751	May 12 01:42:28 PM PDT 24	May 12 01:42:30 PM PDT 24	2034554910 ps
T314	/workspace/coverage/default/38.sysrst_ctrl_stress_all.3945158431	May 12 01:42:58 PM PDT 24	May 12 01:43:04 PM PDT 24	6643415410 ps
T204	/workspace/coverage/default/7.sysrst_ctrl_edge_detect.349911078	May 12 01:41:39 PM PDT 24	May 12 01:41:43 PM PDT 24	3026509841 ps
T315	/workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2910131525	May 12 01:42:07 PM PDT 24	May 12 01:42:11 PM PDT 24	4012070708 ps
T316	/workspace/coverage/default/19.sysrst_ctrl_smoke.2628889186	May 12 01:42:09 PM PDT 24	May 12 01:42:11 PM PDT 24	2130606063 ps
T122	/workspace/coverage/default/25.sysrst_ctrl_combo_detect.2653745302	May 12 01:42:25 PM PDT 24	May 12 01:43:05 PM PDT 24	29640539393 ps
T317	/workspace/coverage/default/46.sysrst_ctrl_alert_test.2493709853	May 12 01:43:14 PM PDT 24	May 12 01:43:17 PM PDT 24	2039151866 ps
T434	/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1674167941	May 12 01:42:04 PM PDT 24	May 12 01:42:14 PM PDT 24	3654267375 ps
T108	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.3787144862	May 12 01:41:02 PM PDT 24	May 12 01:42:25 PM PDT 24	33783694564 ps
T435	/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1192221593	May 12 01:43:14 PM PDT 24	May 12 01:43:17 PM PDT 24	2539430764 ps
T267	/workspace/coverage/default/23.sysrst_ctrl_combo_detect.3697120462	May 12 01:42:21 PM PDT 24	May 12 01:42:59 PM PDT 24	65131601343 ps
T436	/workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1218253626	May 12 01:42:29 PM PDT 24	May 12 01:42:41 PM PDT 24	4475393296 ps
T385	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.977737823	May 12 01:43:28 PM PDT 24	May 12 01:43:59 PM PDT 24	72244096471 ps
T231	/workspace/coverage/default/34.sysrst_ctrl_edge_detect.66760003	May 12 01:42:47 PM PDT 24	May 12 01:42:50 PM PDT 24	2955890979 ps
T437	/workspace/coverage/default/32.sysrst_ctrl_alert_test.4116150335	May 12 01:42:44 PM PDT 24	May 12 01:42:51 PM PDT 24	2010016914 ps
T109	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1522369818	May 12 01:41:11 PM PDT 24	May 12 01:45:02 PM PDT 24	88752396561 ps
T438	/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2643709960	May 12 01:42:03 PM PDT 24	May 12 01:42:05 PM PDT 24	2491758820 ps
T439	/workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3810494990	May 12 01:41:53 PM PDT 24	May 12 01:41:58 PM PDT 24	2620414752 ps
T440	/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1298376308	May 12 01:42:58 PM PDT 24	May 12 01:43:02 PM PDT 24	2466715193 ps
T115	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2095096996	May 12 01:42:14 PM PDT 24	May 12 01:42:22 PM PDT 24	5650516423 ps
T441	/workspace/coverage/default/21.sysrst_ctrl_pin_access_test.4235292407	May 12 01:42:15 PM PDT 24	May 12 01:42:21 PM PDT 24	2049800855 ps
T123	/workspace/coverage/default/21.sysrst_ctrl_stress_all.2723221197	May 12 01:42:14 PM PDT 24	May 12 01:43:10 PM PDT 24	130387408545 ps
T442	/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2239748997	May 12 01:43:13 PM PDT 24	May 12 01:43:17 PM PDT 24	4481945538 ps
T443	/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1420945572	May 12 01:41:39 PM PDT 24	May 12 01:41:42 PM PDT 24	2451525036 ps
T444	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.701213508	May 12 01:42:56 PM PDT 24	May 12 01:42:59 PM PDT 24	2538910415 ps
T445	/workspace/coverage/default/43.sysrst_ctrl_stress_all.1955984677	May 12 01:43:04 PM PDT 24	May 12 01:43:11 PM PDT 24	8845902538 ps
T192	/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1059461796	May 12 01:42:06 PM PDT 24	May 12 01:43:27 PM PDT 24	57833142897 ps
T446	/workspace/coverage/default/41.sysrst_ctrl_smoke.2567790748	May 12 01:43:05 PM PDT 24	May 12 01:43:09 PM PDT 24	2117114021 ps
T447	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.2669631919	May 12 01:42:01 PM PDT 24	May 12 01:42:05 PM PDT 24	2433193396 ps
T448	/workspace/coverage/default/35.sysrst_ctrl_alert_test.1790277203	May 12 01:42:55 PM PDT 24	May 12 01:43:02 PM PDT 24	2012681582 ps
T449	/workspace/coverage/default/20.sysrst_ctrl_alert_test.4106772585	May 12 01:42:13 PM PDT 24	May 12 01:42:19 PM PDT 24	2011822941 ps
T450	/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1215303887	May 12 01:41:22 PM PDT 24	May 12 01:41:25 PM PDT 24	3655136009 ps
T451	/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2951021449	May 12 01:43:05 PM PDT 24	May 12 01:43:13 PM PDT 24	2614180150 ps
T194	/workspace/coverage/default/32.sysrst_ctrl_edge_detect.3500500490	May 12 01:42:43 PM PDT 24	May 12 01:42:45 PM PDT 24	3156273711 ps
T211	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.3681313671	May 12 01:42:18 PM PDT 24	May 12 01:42:22 PM PDT 24	2635712301 ps
T452	/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.423050792	May 12 01:42:44 PM PDT 24	May 12 01:42:57 PM PDT 24	93861828814 ps
T453	/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3423147210	May 12 01:41:56 PM PDT 24	May 12 01:42:00 PM PDT 24	2187271967 ps