00fe426038
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | sysrst_ctrl_smoke | 6.520s | 2.112ms | 50 | 50 | 100.00 |
V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 8.390s | 2.452ms | 50 | 50 | 100.00 |
V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 6.630s | 2.221ms | 5 | 5 | 100.00 |
V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 7.150s | 2.510ms | 5 | 5 | 100.00 |
V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 14.240s | 6.021ms | 5 | 5 | 100.00 |
V1 | csr_rw | sysrst_ctrl_csr_rw | 6.450s | 2.046ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 2.996m | 74.134ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 12.440s | 3.139ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 6.610s | 2.047ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 6.450s | 2.046ms | 20 | 20 | 100.00 |
sysrst_ctrl_csr_aliasing | 12.440s | 3.139ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 165 | 165 | 100.00 | |||
V2 | combo_detect | sysrst_ctrl_combo_detect | 7.737m | 171.218ms | 50 | 50 | 100.00 |
V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 8.459m | 200.736ms | 93 | 100 | 93.00 |
V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 13.069m | 325.434ms | 50 | 50 | 100.00 |
V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 41.720s | 960.593ms | 50 | 50 | 100.00 |
V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 7.790s | 2.513ms | 50 | 50 | 100.00 |
V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 6.950s | 2.256ms | 50 | 50 | 100.00 |
V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 6.013m | 820.278ms | 50 | 50 | 100.00 |
V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 7.920s | 2.610ms | 50 | 50 | 100.00 |
V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 10.792m | 2.122s | 46 | 50 | 92.00 |
V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 22.800s | 37.114ms | 2 | 2 | 100.00 |
V2 | stress_all | sysrst_ctrl_stress_all | 7.982m | 209.175ms | 50 | 50 | 100.00 |
V2 | alert_test | sysrst_ctrl_alert_test | 6.060s | 2.016ms | 50 | 50 | 100.00 |
V2 | intr_test | sysrst_ctrl_intr_test | 6.160s | 2.013ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 8.420s | 2.148ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 8.420s | 2.148ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 14.240s | 6.021ms | 5 | 5 | 100.00 |
sysrst_ctrl_csr_rw | 6.450s | 2.046ms | 20 | 20 | 100.00 | ||
sysrst_ctrl_csr_aliasing | 12.440s | 3.139ms | 5 | 5 | 100.00 | ||
sysrst_ctrl_same_csr_outstanding | 29.020s | 7.767ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 14.240s | 6.021ms | 5 | 5 | 100.00 |
sysrst_ctrl_csr_rw | 6.450s | 2.046ms | 20 | 20 | 100.00 | ||
sysrst_ctrl_csr_aliasing | 12.440s | 3.139ms | 5 | 5 | 100.00 | ||
sysrst_ctrl_same_csr_outstanding | 29.020s | 7.767ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 681 | 692 | 98.41 | |||
V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.799m | 42.011ms | 5 | 5 | 100.00 |
sysrst_ctrl_tl_intg_err | 1.937m | 42.453ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.937m | 42.453ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 3.242m | 300.875ms | 44 | 50 | 88.00 |
V3 | TOTAL | 44 | 50 | 88.00 | |||
TOTAL | 915 | 932 | 98.18 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 9 | 100.00 |
V2 | 15 | 15 | 13 | 86.67 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.73 | 99.33 | 96.38 | 100.00 | 96.15 | 98.82 | 99.42 | 94.03 |
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
has 5 failures:
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
2.sysrst_ctrl_stress_all_with_rand_reset.57600477650487445084143247302931630441106259558170869036323801896681906663342
Line 608, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 343776036591 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 345643536591 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 345643536591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_ultra_low_pwr has 4 failures.
3.sysrst_ctrl_ultra_low_pwr.46298184305690322114351462311699776188288780129747864347192183915708886398511
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2697752194 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 3530252194 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3530252194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.sysrst_ctrl_ultra_low_pwr.35198972960926765972504228951243361904218117493662119717222803285449311330699
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 6209880431 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 6277380431 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 8197380431 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 8215619676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])
has 3 failures:
51.sysrst_ctrl_combo_detect_with_pre_cond.101257274530410082524554584256312380117854325952406776428203603775345912131009
Line 589, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 40566354919 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 40566354919 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 40566354919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
97.sysrst_ctrl_combo_detect_with_pre_cond.64657118628844174102538775527474874138343011659561985790522103294443804193954
Line 639, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 110549065657 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 110549065657 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 110549065657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])
has 2 failures:
5.sysrst_ctrl_combo_detect_with_pre_cond.110701050474016578073963938527739221235031730678570966821385161458814515556934
Line 579, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 25119927067 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25189927067 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 25209927067 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 35415815898 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2b
UVM_INFO @ 35415857564 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x19
85.sysrst_ctrl_combo_detect_with_pre_cond.40479481325785984370560713395938790327382972227350010712448095029476735493070
Line 583, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 26215099625 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 26215099625 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 26215099625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (* [*] vs * [*])
has 1 failures:
4.sysrst_ctrl_stress_all_with_rand_reset.11012541441582745060649450642820160473241828662631866740112094043774137089614
Line 615, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26646792005 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 26767058144 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 5d
UVM_INFO @ 27311792005 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:95
UVM_INFO @ 27431900563 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 5a
UVM_INFO @ 27996792005 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:91
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *
has 1 failures:
18.sysrst_ctrl_stress_all_with_rand_reset.41119173495853357500099524069280587274251689180132133275309100741940522097230
Line 621, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 28226387503 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 28226387503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:124) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at Key2Idx
has 1 failures:
26.sysrst_ctrl_stress_all_with_rand_reset.53527108475531055256013057647413884787272089283955730011559771256462575977315
Line 608, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16803219546 ps: (sysrst_ctrl_edge_detect_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 16803219546 ps: (sysrst_ctrl_edge_detect_vseq.sv:132) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_INFO @ 16803219546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*])
has 1 failures:
28.sysrst_ctrl_stress_all_with_rand_reset.7018733132600486263291657360963795982139036083096771793297367038838321741624
Line 662, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55241789453 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 55241789453 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 55241789453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*
has 1 failures:
42.sysrst_ctrl_combo_detect_with_pre_cond.28041912775174397765291291745141900480432588901396112006025953838130796126522
Line 573, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13525712518 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4
UVM_ERROR @ 13525712518 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
UVM_INFO @ 13525712518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:75) [sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*])
has 1 failures:
43.sysrst_ctrl_stress_all_with_rand_reset.62198325988449397834902772337024931439172068093596040226033330746876104916482
Line 638, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 117537870149 ps: (sysrst_ctrl_combo_detect_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 117537870149 ps: (sysrst_ctrl_combo_detect_vseq.sv:234) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 117537870149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-*
has 1 failures:
53.sysrst_ctrl_combo_detect_with_pre_cond.90684053653112909293792219174602629918433772394313720593527618367432566815916
Line 572, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 22629235393 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-4
UVM_INFO @ 22634235393 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
UVM_INFO @ 22714235393 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 22734235393 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 32762985700 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x14