SYSRST_CTRL Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.520s 2.112ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 8.390s 2.452ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.630s 2.221ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.150s 2.510ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 14.240s 6.021ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.450s 2.046ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 2.996m 74.134ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 12.440s 3.139ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.610s 2.047ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.450s 2.046ms 20 20 100.00
sysrst_ctrl_csr_aliasing 12.440s 3.139ms 5 5 100.00
V1 TOTAL 165 165 100.00
V2 combo_detect sysrst_ctrl_combo_detect 7.737m 171.218ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 8.459m 200.736ms 93 100 93.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 13.069m 325.434ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 41.720s 960.593ms 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.790s 2.513ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.950s 2.256ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 6.013m 820.278ms 50 50 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.920s 2.610ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 10.792m 2.122s 46 50 92.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 22.800s 37.114ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 7.982m 209.175ms 50 50 100.00
V2 alert_test sysrst_ctrl_alert_test 6.060s 2.016ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 6.160s 2.013ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 8.420s 2.148ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 8.420s 2.148ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 14.240s 6.021ms 5 5 100.00
sysrst_ctrl_csr_rw 6.450s 2.046ms 20 20 100.00
sysrst_ctrl_csr_aliasing 12.440s 3.139ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 29.020s 7.767ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 14.240s 6.021ms 5 5 100.00
sysrst_ctrl_csr_rw 6.450s 2.046ms 20 20 100.00
sysrst_ctrl_csr_aliasing 12.440s 3.139ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 29.020s 7.767ms 20 20 100.00
V2 TOTAL 681 692 98.41
V2S tl_intg_err sysrst_ctrl_sec_cm 1.799m 42.011ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.937m 42.453ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.937m 42.453ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 3.242m 300.875ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 915 932 98.18

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 13 86.67
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.73 99.33 96.38 100.00 96.15 98.82 99.42 94.03

Failure Buckets

Past Results