Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2095

1

T2

24

T4

15

T11

2

auto[1]

621

1

T1

8

T2

8

T4

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2119

1

T1

1

T2

32

T4

18

auto[1]

597

1

T1

7

T4

2

T11

5

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2176

1

T1

7

T2

24

T4

20

auto[1]

540

1

T1

1

T2

8

T11

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2054

1

T1

5

T2

30

T4

20

auto[1]

662

1

T1

3

T2

2

T11

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2496

1

T1

8

T2

25

T4

18

auto[1]

220

1

T2

7

T4

2

T49

8

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2504

1

T1

8

T2

15

T4

15

auto[1]

212

1

T2

17

T4

5

T48

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2481

1

T1

8

T2

32

T4

18

auto[1]

235

1

T4

2

T50

5

T264

7

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2483

1

T1

8

T2

32

T4

20

auto[1]

233

1

T49

6

T50

3

T264

9

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2494

1

T1

8

T2

30

T4

20

auto[1]

222

1

T2

2

T49

2

T278

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2170

1

T2

25

T4

13

T11

3

auto[1]

546

1

T1

8

T2

7

T4

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

873

1

T1

8

T11

7

T35

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

70

1

T264

4

T279

4

T112

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

73

1

T278

1

T282

1

T364

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

48

1

T49

2

T359

18

T365

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T264

9

T112

2

T283

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T342

1

T354

6

T366

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T255

2

T177

7

T359

15

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T280

4

T367

5

T368

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

73

1

T50

5

T264

7

T341

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T4

2

T177

5

T369

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

14

1

T367

2

T370

8

T354

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T279

2

T371

4

T370

24

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T280

1

T365

1

T372

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T368

1

T373

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

86

1

T2

8

T4

5

T48

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T2

7

T280

2

T299

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

13

1

T2

2

T279

3

T345

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T352

2

T353

5

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

14

1

T50

3

T374

2

T375

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T281

5

T353

6

T354

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T366

2

T365

1

T372

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T368

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

35

1

T34

8

T255

5

T351

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T255

3

T109

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T281

4

T369

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T359

2

T376

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

166

1

T281

4

T122

8

T147

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

94

1

T2

7

T50

3

T343

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

70

1

T4

5

T264

9

T112

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

181

1

T2

2

T27

12

T49

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

60

1

T48

1

T279

3

T345

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T280

2

T377

6

T355

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T36

2

T346

1

T220

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

161

1

T280

4

T378

7

T364

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

50

1

T2

8

T36

5

T284

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

37

1

T281

5

T343

5

T124

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T11

2

T287

2

T279

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T37

2

T299

2

T348

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T287

1

T364

8

T118

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40

1

T36

4

T144

5

T282

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T1

1

T35

1

T154

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

87

1

T145

15

T279

4

T352

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

36

1

T283

4

T341

4

T255

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

79

1

T4

2

T35

5

T280

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T1

5

T279

2

T232

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

102

1

T264

7

T367

2

T344

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

44

1

T35

2

T27

4

T145

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

34

1

T11

2

T367

9

T154

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T1

2

T36

1

T350

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T145

8

T282

1

T367

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T11

3

T343

1

T284

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

14

1

T145

5

T112

1

T147

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T147

1

T216

1

T220

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T124

2

T216

2

T379

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T147

2

T344

2

T196

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T264

4

T348

2

T380

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T381

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded