Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T14

11

T58

12

T76

9

auto[1]

1046

1

T14

9

T58

8

T76

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T14

4

T58

5

T76

5

from_0to1

491

1

T14

5

T58

5

T76

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T14

9

T58

10

T76

8

auto[1]

1032

1

T14

11

T58

10

T76

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T14

11

T58

9

T76

8

auto[1]

999

1

T14

9

T58

11

T76

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T14

1

T82

1

T27

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T14

1

T82

1

T27

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T58

1

T76

2

T11

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T76

1

T11

1

T133

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T208

2

T65

2

T37

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T76

1

T27

1

T42

2

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T14

3

T58

2

T11

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T14

1

T58

1

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T14

1

T58

2

T76

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T76

1

T11

1

T27

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T14

1

T58

1

T133

1

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T58

1

T11

1

T82

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T58

1

T42

2

T65

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T14

1

T76

2

T82

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T76

1

T27

1

T133

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T58

1

T76

1

T11

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T14

12

T58

9

T76

14

auto[1]

993

1

T14

8

T58

11

T76

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

490

1

T14

4

T58

5

T76

5

from_0to1

489

1

T14

5

T58

4

T76

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T14

7

T58

8

T76

11

auto[1]

1032

1

T14

13

T58

12

T76

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014

1

T14

9

T58

10

T76

9

auto[1]

1026

1

T14

11

T58

10

T76

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T14

1

T58

1

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T14

2

T76

1

T208

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T27

1

T133

1

T42

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T58

3

T76

1

T42

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T76

1

T133

1

T208

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T58

1

T76

1

T82

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T11

2

T27

2

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T14

1

T76

1

T82

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T76

1

T82

2

T27

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T11

1

T42

2

T208

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T14

1

T11

1

T82

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T58

1

T76

1

T11

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T76

1

T11

2

T82

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T14

2

T58

1

T11

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T14

1

T133

1

T42

4

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T14

1

T58

2

T82

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T14

10

T58

13

T76

11

auto[1]

975

1

T14

10

T58

7

T76

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

475

1

T14

4

T58

5

T76

5

from_0to1

478

1

T14

5

T58

6

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T14

11

T58

11

T76

9

auto[1]

1032

1

T14

9

T58

9

T76

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T14

9

T58

7

T76

11

auto[1]

998

1

T14

11

T58

13

T76

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T14

2

T58

1

T82

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T14

1

T11

2

T82

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T76

1

T27

1

T133

2

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T58

3

T76

2

T11

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T58

1

T76

1

T11

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T58

2

T11

1

T82

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T14

1

T58

1

T76

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T14

1

T58

1

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T14

1

T76

2

T11

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T58

1

T27

1

T37

3

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T82

1

T42

2

T260

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T42

1

T208

4

T143

2

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T133

1

T42

1

T65

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T76

2

T208

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T11

1

T27

2

T42

2

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T14

2

T58

1

T27

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T14

9

T58

13

T76

14

auto[1]

1062

1

T14

11

T58

7

T76

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

485

1

T14

5

T58

7

T76

6

from_0to1

490

1

T14

5

T58

8

T76

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1013

1

T14

7

T58

13

T76

12

auto[1]

1027

1

T14

13

T58

7

T76

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T14

14

T58

11

T76

10

auto[1]

1009

1

T14

6

T58

9

T76

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T58

3

T76

3

T82

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T58

2

T76

1

T11

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T76

1

T11

2

T27

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T14

1

T76

1

T37

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T14

1

T76

1

T82

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T58

1

T76

3

T82

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T14

1

T58

2

T11

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T58

1

T11

1

T27

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T14

2

T58

1

T11

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T82

2

T133

2

T42

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T14

2

T11

1

T133

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T58

1

T11

1

T27

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T58

2

T76

1

T11

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T14

1

T58

2

T11

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T14

2

T76

1

T133

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T11

1

T82

1

T133

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

989

1

T14

11

T58

10

T76

9

auto[1]

1051

1

T14

9

T58

10

T76

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

486

1

T14

4

T58

3

T76

5

from_0to1

479

1

T14

5

T58

2

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T14

12

T58

9

T76

12

auto[1]

978

1

T14

8

T58

11

T76

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T14

9

T58

7

T76

10

auto[1]

1037

1

T14

11

T58

13

T76

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T14

1

T133

1

T42

2

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T14

1

T58

1

T76

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T76

1

T82

1

T208

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T58

1

T27

1

T133

1

auto[0]

from_0to1

auto[0]

auto[0]

43

1

T133

1

T65

2

T37

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T14

1

T76

1

T27

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T58

1

T76

1

T11

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T14

1

T58

1

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T14

1

T76

1

T82

2

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T76

1

T11

2

T133

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T58

1

T11

1

T133

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T14

1

T76

1

T11

2

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T14

1

T37

2

T317

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T76

1

T11

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T14

1

T76

1

T11

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T11

3

T42

1

T208

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1012

1

T14

10

T58

14

T76

10

auto[1]

1028

1

T14

10

T58

6

T76

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

491

1

T14

4

T58

5

T76

3

from_0to1

496

1

T14

5

T58

6

T76

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T14

9

T58

14

T76

9

auto[1]

977

1

T14

11

T58

6

T76

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T14

13

T58

10

T76

15

auto[1]

1003

1

T14

7

T58

10

T76

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T14

2

T58

1

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T58

1

T82

2

T65

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T14

1

T58

1

T11

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T76

1

T42

2

T208

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T14

1

T58

2

T76

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T58

2

T82

1

T42

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T14

2

T76

1

T11

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T14

1

T82

1

T27

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T14

1

T11

1

T82

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T58

1

T76

1

T11

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T58

1

T82

1

T37

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T82

2

T27

1

T133

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T11

1

T82

3

T27

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T14

1

T58

1

T11

2

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T76

1

T82

2

T133

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T58

1

T11

1

T27

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T14

7

T58

16

T76

10

auto[1]

990

1

T14

13

T58

4

T76

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

492

1

T14

5

T58

5

T76

4

from_0to1

503

1

T14

4

T58

5

T76

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1017

1

T14

12

T58

8

T76

10

auto[1]

1023

1

T14

8

T58

12

T76

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T14

11

T58

12

T76

12

auto[1]

1019

1

T14

9

T58

8

T76

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T58

1

T27

1

T133

1

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T14

1

T58

1

T11

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T14

1

T76

1

T11

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T58

3

T11

2

T82

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T14

1

T58

2

T82

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T14

1

T11

1

T27

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T58

1

T76

1

T11

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T58

1

T76

1

T11

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T14

1

T76

1

T82

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T14

1

T76

2

T208

2

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T27

1

T133

1

T42

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T14

1

T42

1

T208

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T14

1

T27

2

T133

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T76

2

T27

1

T208

2

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T82

1

T27

1

T42

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T14

1

T58

1

T82

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T14

11

T58

12

T76

8

auto[1]

991

1

T14

9

T58

8

T76

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T14

7

T58

4

T76

6

from_0to1

505

1

T14

7

T58

4

T76

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T14

9

T58

10

T76

7

auto[1]

1005

1

T14

11

T58

10

T76

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T14

14

T58

9

T76

11

auto[1]

976

1

T14

6

T58

11

T76

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T14

1

T58

1

T133

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T14

1

T76

1

T27

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T14

2

T58

1

T133

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T14

1

T58

1

T11

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T14

1

T58

1

T11

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T76

2

T42

3

T37

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T14

1

T11

1

T27

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T58

1

T76

1

T133

2

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T76

1

T11

1

T82

3

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T58

1

T11

2

T42

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T14

1

T76

4

T133

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T14

1

T11

1

T27

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T14

2

T58

1

T82

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T14

1

T76

1

T11

2

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T14

2

T58

1

T76

2

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T76

1

T82

1

T42

1