Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154951	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117957

1

T1

245

T5

23

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138315	1			T1	398		T5	2		T6	4
values[0x0]	66408	1			T1	51		T5	30		T13	32
values[0x1]	68185	1			T1	55		T5	30		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147606

1

T1

298

T5

30

T6

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1027	1			T14	1		T2	3		T30	3
valid_sources[0x01]	1475	1			T1	2		T2	1		T30	2
valid_sources[0x02]	841	1			T1	2		T26	2		T2	5
valid_sources[0x03]	998	1			T1	5		T14	1		T16	2
valid_sources[0x04]	794	1			T1	3		T2	1		T72	1
valid_sources[0x05]	856	1			T30	4		T3	3		T25	1
valid_sources[0x06]	863	1			T1	1		T16	1		T2	5
valid_sources[0x07]	804	1			T1	3		T30	2		T3	5
valid_sources[0x08]	766	1			T1	2		T2	1		T72	1
valid_sources[0x09]	993	1			T1	7		T14	5		T2	3
valid_sources[0x0a]	1592	1			T1	1		T2	1		T30	2
valid_sources[0x0b]	1313	1			T1	2		T26	2		T2	1
valid_sources[0x0c]	806	1			T1	4		T26	1		T2	4
valid_sources[0x0d]	1048	1			T5	4		T2	4		T30	3
valid_sources[0x0e]	988	1			T1	3		T2	5		T3	2
valid_sources[0x0f]	875	1			T1	1		T2	19		T8	2
valid_sources[0x10]	924	1			T1	2		T30	2		T8	3
valid_sources[0x11]	902	1			T1	10		T2	8		T3	2
valid_sources[0x12]	1026	1			T1	2		T14	2		T30	3
valid_sources[0x13]	1681	1			T1	6		T5	2		T14	6
valid_sources[0x14]	1003	1			T1	6		T2	2		T30	3
valid_sources[0x15]	1137	1			T26	1		T30	1		T25	1
valid_sources[0x16]	920	1			T1	2		T6	1		T24	1
valid_sources[0x17]	1120	1			T1	1		T30	3		T72	1
valid_sources[0x18]	1844	1			T1	1		T2	1		T30	2
valid_sources[0x19]	1581	1			T1	4		T2	4		T30	2
valid_sources[0x1a]	909	1			T1	3		T2	4		T30	2
valid_sources[0x1b]	868	1			T1	2		T19	2		T26	2
valid_sources[0x1c]	999	1			T2	1		T30	1		T3	3
valid_sources[0x1d]	1093	1			T1	1		T2	4		T30	1
valid_sources[0x1e]	961	1			T1	2		T19	2		T2	1
valid_sources[0x1f]	958	1			T1	3		T28	16		T2	5
valid_sources[0x20]	1024	1			T1	1		T18	1		T2	2
valid_sources[0x21]	1098	1			T1	3		T2	4		T30	2
valid_sources[0x22]	1848	1			T1	7		T14	4		T26	1
valid_sources[0x23]	1005	1			T1	2		T2	3		T30	3
valid_sources[0x24]	1870	1			T2	3		T8	1		T11	1
valid_sources[0x25]	933	1			T14	1		T2	2		T30	1
valid_sources[0x26]	755	1			T2	5		T30	1		T8	2
valid_sources[0x27]	864	1			T2	4		T30	1		T3	1
valid_sources[0x28]	870	1			T1	1		T2	5		T30	1
valid_sources[0x29]	747	1			T1	2		T26	3		T2	2
valid_sources[0x2a]	1001	1			T1	4		T2	4		T30	5
valid_sources[0x2b]	1010	1			T1	3		T14	1		T16	1
valid_sources[0x2c]	827	1			T2	3		T30	2		T8	1
valid_sources[0x2d]	853	1			T1	2		T18	2		T19	1
valid_sources[0x2e]	1102	1			T1	7		T30	1		T29	11
valid_sources[0x2f]	1133	1			T14	1		T2	4		T8	1
valid_sources[0x30]	862	1			T1	4		T2	3		T30	1
valid_sources[0x31]	1461	1			T1	4		T2	8		T30	1
valid_sources[0x32]	1069	1			T1	1		T26	1		T2	9
valid_sources[0x33]	972	1			T1	1		T19	1		T24	1
valid_sources[0x34]	1066	1			T19	4		T2	8		T30	2
valid_sources[0x35]	1509	1			T1	5		T14	1		T2	5
valid_sources[0x36]	1071	1			T1	1		T2	5		T8	5
valid_sources[0x37]	993	1			T1	4		T30	2		T75	1
valid_sources[0x38]	966	1			T14	2		T2	5		T30	1
valid_sources[0x39]	780	1			T2	3		T30	2		T3	1
valid_sources[0x3a]	1159	1			T1	1		T2	11		T30	2
valid_sources[0x3b]	1104	1			T1	1		T26	3		T8	1
valid_sources[0x3c]	1113	1			T1	1		T24	1		T2	5
valid_sources[0x3d]	809	1			T1	3		T18	2		T2	7
valid_sources[0x3e]	916	1			T1	6		T6	2		T2	2
valid_sources[0x3f]	1128	1			T1	5		T30	3		T3	1
valid_sources[0x40]	902	1			T1	2		T14	1		T16	1
valid_sources[0x41]	1076	1			T14	7		T26	5		T2	1
valid_sources[0x42]	886	1			T1	3		T2	1		T30	1
valid_sources[0x43]	1130	1			T2	12		T30	3		T3	1
valid_sources[0x44]	1142	1			T2	2		T30	2		T75	1
valid_sources[0x45]	871	1			T1	3		T2	5		T75	1
valid_sources[0x46]	882	1			T30	2		T72	1		T7	17
valid_sources[0x47]	989	1			T1	3		T14	1		T24	1
valid_sources[0x48]	864	1			T14	1		T19	2		T2	1
valid_sources[0x49]	1128	1			T2	10		T30	2		T11	4
valid_sources[0x4a]	930	1			T2	1		T3	1		T11	3
valid_sources[0x4b]	883	1			T30	1		T3	1		T72	1
valid_sources[0x4c]	841	1			T14	1		T2	7		T30	1
valid_sources[0x4d]	2453	1			T1	7		T14	1		T2	7
valid_sources[0x4e]	1071	1			T16	1		T59	10		T30	3
valid_sources[0x4f]	869	1			T1	4		T2	1		T30	1
valid_sources[0x50]	1850	1			T2	6		T30	1		T3	2
valid_sources[0x51]	1273	1			T2	4		T30	3		T72	1
valid_sources[0x52]	785	1			T1	7		T5	16		T14	8
valid_sources[0x53]	898	1			T1	2		T24	2		T2	3
valid_sources[0x54]	1095	1			T1	1		T2	4		T3	5
valid_sources[0x55]	1504	1			T1	6		T2	7		T30	2
valid_sources[0x56]	804	1			T1	2		T19	1		T2	8
valid_sources[0x57]	759	1			T1	2		T19	1		T26	1
valid_sources[0x58]	1995	1			T5	9		T17	3		T2	4
valid_sources[0x59]	845	1			T1	2		T26	2		T2	2
valid_sources[0x5a]	963	1			T1	1		T26	3		T2	3
valid_sources[0x5b]	1175	1			T1	5		T14	1		T26	1
valid_sources[0x5c]	894	1			T1	2		T2	3		T30	3
valid_sources[0x5d]	965	1			T30	1		T8	1		T76	3
valid_sources[0x5e]	1065	1			T1	4		T19	2		T2	4
valid_sources[0x5f]	2199	1			T1	2		T13	63		T2	4
valid_sources[0x60]	894	1			T1	1		T2	6		T30	2
valid_sources[0x61]	1174	1			T1	4		T2	1		T30	1
valid_sources[0x62]	877	1			T1	3		T2	5		T30	3
valid_sources[0x63]	818	1			T2	12		T30	2		T52	7
valid_sources[0x64]	752	1			T1	2		T2	2		T30	2
valid_sources[0x65]	803	1			T1	3		T2	10		T30	3
valid_sources[0x66]	1915	1			T2	1		T30	1		T25	1
valid_sources[0x67]	945	1			T1	3		T2	8		T30	4
valid_sources[0x68]	1340	1			T30	1		T51	426		T11	17
valid_sources[0x69]	1112	1			T1	3		T15	5		T16	1
valid_sources[0x6a]	1158	1			T1	1		T30	2		T3	5
valid_sources[0x6b]	866	1			T1	2		T14	1		T19	2
valid_sources[0x6c]	884	1			T1	2		T16	1		T19	1
valid_sources[0x6d]	1013	1			T19	1		T2	4		T30	3
valid_sources[0x6e]	819	1			T2	1		T25	2		T8	1
valid_sources[0x6f]	1336	1			T1	9		T2	6		T30	2
valid_sources[0x70]	1659	1			T26	1		T2	1		T30	1
valid_sources[0x71]	947	1			T1	1		T19	1		T2	6
valid_sources[0x72]	812	1			T1	7		T26	1		T24	3
valid_sources[0x73]	995	1			T1	3		T19	3		T2	4
valid_sources[0x74]	1310	1			T1	1		T14	2		T26	1
valid_sources[0x75]	1291	1			T1	2		T2	1		T3	1
valid_sources[0x76]	1089	1			T1	2		T14	4		T2	4
valid_sources[0x77]	1554	1			T1	2		T26	2		T2	2
valid_sources[0x78]	2252	1			T24	3		T2	2		T30	3
valid_sources[0x79]	751	1			T1	3		T2	3		T30	3
valid_sources[0x7a]	887	1			T1	3		T24	1		T2	1
valid_sources[0x7b]	1034	1			T1	1		T30	1		T8	1
valid_sources[0x7c]	854	1			T1	5		T19	1		T30	2
valid_sources[0x7d]	1277	1			T1	3		T19	1		T2	2
valid_sources[0x7e]	1686	1			T14	3		T2	4		T3	1
valid_sources[0x7f]	967	1			T24	2		T2	3		T30	3
valid_sources[0x80]	827	1			T1	1		T24	3		T2	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62511

1

T1

196

T5

1

T6

1

values[0x0]

all_enables

biggest_size

32369

1

T1

25

T5

16

T13

8

values[0x1]

all_enables

biggest_size

23077

1

T1

24

T5

6

T13

6