Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1292664939	10910	0	0
auto_block_debounce_ctl_rd_A	1292664939	1826	0	0
auto_block_out_ctl_rd_A	1292664939	2442	0	0
com_det_ctl_0_rd_A	1292664939	3813	0	0
com_det_ctl_1_rd_A	1292664939	3563	0	0
com_det_ctl_2_rd_A	1292664939	3776	0	0
com_det_ctl_3_rd_A	1292664939	3799	0	0
com_out_ctl_0_rd_A	1292664939	4321	0	0
com_out_ctl_1_rd_A	1292664939	4066	0	0
com_out_ctl_2_rd_A	1292664939	4169	0	0
com_out_ctl_3_rd_A	1292664939	4138	0	0
com_pre_det_ctl_0_rd_A	1292664939	1327	0	0
com_pre_det_ctl_1_rd_A	1292664939	1375	0	0
com_pre_det_ctl_2_rd_A	1292664939	1329	0	0
com_pre_det_ctl_3_rd_A	1292664939	1381	0	0
com_pre_sel_ctl_0_rd_A	1292664939	4382	0	0
com_pre_sel_ctl_1_rd_A	1292664939	4517	0	0
com_pre_sel_ctl_2_rd_A	1292664939	4195	0	0
com_pre_sel_ctl_3_rd_A	1292664939	4536	0	0
com_sel_ctl_0_rd_A	1292664939	4297	0	0
com_sel_ctl_1_rd_A	1292664939	4220	0	0
com_sel_ctl_2_rd_A	1292664939	4410	0	0
com_sel_ctl_3_rd_A	1292664939	4414	0	0
ec_rst_ctl_rd_A	1292664939	2480	0	0
intr_enable_rd_A	1292664939	1995	0	0
key_intr_ctl_rd_A	1292664939	4055	0	0
key_intr_debounce_ctl_rd_A	1292664939	1422	0	0
key_invert_ctl_rd_A	1292664939	4321	0	0
pin_allowed_ctl_rd_A	1292664939	5454	0	0
pin_out_ctl_rd_A	1292664939	3708	0	0
pin_out_value_rd_A	1292664939	4146	0	0
regwen_rd_A	1292664939	1640	0	0
ulp_ac_debounce_ctl_rd_A	1292664939	1464	0	0
ulp_ctl_rd_A	1292664939	1487	0	0
ulp_lid_debounce_ctl_rd_A	1292664939	1498	0	0
ulp_pwrb_debounce_ctl_rd_A	1292664939	1464	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	10910	0	0
T8	130215	8	0	0
T9	108758	0	0	0
T10	64615	0	0	0
T11	748762	0	0	0
T12	67102	0	0	0
T37	0	8	0	0
T52	976309	0	0	0
T53	320934	14	0	0
T76	241017	0	0	0
T82	238371	0	0	0
T90	0	2	0	0
T110	0	23	0	0
T135	0	6	0	0
T147	0	7	0	0
T151	51213	0	0	0
T154	0	16	0	0
T303	0	6	0	0
T304	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1826	0	0
T2	139628	0	0	0
T3	691654	0	0	0
T4	454461	0	0	0
T11	0	8	0	0
T28	173871	13	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T37	0	35	0	0
T55	0	2	0	0
T56	0	17	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T78	103746	0	0	0
T90	0	8	0	0
T119	0	3	0	0
T147	0	18	0	0
T305	0	11	0	0
T306	0	10	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2442	0	0
T2	139628	0	0	0
T3	691654	0	0	0
T4	454461	0	0	0
T11	0	5	0	0
T28	173871	8	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T37	0	49	0	0
T55	0	5	0	0
T56	0	16	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T78	103746	0	0	0
T90	0	9	0	0
T119	0	10	0	0
T147	0	9	0	0
T305	0	5	0	0
T306	0	7	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	3813	0	0
T4	454461	25	0	0
T7	156332	0	0	0
T11	0	63	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	26	0	0
T50	0	78	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	19	0	0
T112	0	51	0	0
T122	0	57	0	0
T232	0	59	0	0
T279	0	18	0	0
T287	0	58	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	3563	0	0
T4	454461	25	0	0
T7	156332	0	0	0
T11	0	38	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	46	0	0
T50	0	48	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	21	0	0
T112	0	56	0	0
T122	0	50	0	0
T232	0	84	0	0
T279	0	40	0	0
T287	0	73	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	3776	0	0
T4	454461	15	0	0
T7	156332	0	0	0
T11	0	54	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	17	0	0
T50	0	72	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	20	0	0
T112	0	46	0	0
T122	0	66	0	0
T232	0	75	0	0
T279	0	29	0	0
T287	0	82	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	3799	0	0
T4	454461	45	0	0
T7	156332	0	0	0
T11	0	37	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	40	0	0
T50	0	44	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	15	0	0
T112	0	57	0	0
T122	0	61	0	0
T232	0	60	0	0
T279	0	28	0	0
T287	0	83	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4321	0	0
T4	454461	19	0	0
T7	156332	0	0	0
T11	0	33	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	30	0	0
T50	0	91	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	4	0	0
T112	0	40	0	0
T122	0	80	0	0
T232	0	75	0	0
T279	0	55	0	0
T287	0	58	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4066	0	0
T4	454461	14	0	0
T7	156332	0	0	0
T11	0	32	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	17	0	0
T50	0	69	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	4	0	0
T112	0	50	0	0
T122	0	88	0	0
T232	0	66	0	0
T279	0	19	0	0
T287	0	55	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4169	0	0
T4	454461	11	0	0
T7	156332	0	0	0
T11	0	48	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	36	0	0
T50	0	77	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	23	0	0
T112	0	51	0	0
T122	0	97	0	0
T232	0	35	0	0
T279	0	35	0	0
T287	0	81	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4138	0	0
T4	454461	31	0	0
T7	156332	0	0	0
T11	0	35	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	20	0	0
T50	0	95	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	12	0	0
T112	0	51	0	0
T122	0	58	0	0
T232	0	56	0	0
T279	0	48	0	0
T287	0	71	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1327	0	0
T32	0	4	0	0
T37	146164	34	0	0
T56	360473	0	0	0
T90	0	10	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	9	0	0
T159	0	4	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T226	0	4	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T304	0	7	0	0
T307	0	19	0	0
T308	0	6	0	0
T309	0	32	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1375	0	0
T32	0	12	0	0
T37	146164	18	0	0
T56	360473	0	0	0
T90	0	25	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	19	0	0
T159	0	8	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T226	0	4	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T304	0	11	0	0
T307	0	30	0	0
T308	0	2	0	0
T309	0	37	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1329	0	0
T32	0	12	0	0
T37	146164	22	0	0
T56	360473	0	0	0
T90	0	17	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	28	0	0
T159	0	23	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T226	0	9	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T304	0	13	0	0
T307	0	32	0	0
T309	0	30	0	0
T310	0	139	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1381	0	0
T32	0	5	0	0
T37	146164	14	0	0
T56	360473	0	0	0
T90	0	18	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	12	0	0
T159	0	19	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T226	0	2	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T304	0	13	0	0
T307	0	44	0	0
T308	0	1	0	0
T309	0	33	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4382	0	0
T4	454461	31	0	0
T7	156332	0	0	0
T11	0	39	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	40	0	0
T50	0	93	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	7	0	0
T112	0	39	0	0
T122	0	58	0	0
T232	0	68	0	0
T279	0	43	0	0
T287	0	60	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4517	0	0
T4	454461	21	0	0
T7	156332	0	0	0
T11	0	54	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	39	0	0
T50	0	72	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	20	0	0
T112	0	51	0	0
T122	0	90	0	0
T232	0	79	0	0
T279	0	39	0	0
T287	0	82	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4195	0	0
T4	454461	18	0	0
T7	156332	0	0	0
T11	0	51	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	41	0	0
T50	0	90	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	17	0	0
T112	0	54	0	0
T122	0	62	0	0
T232	0	80	0	0
T279	0	35	0	0
T287	0	86	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4536	0	0
T4	454461	15	0	0
T7	156332	0	0	0
T11	0	38	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	49	0	0
T50	0	80	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	8	0	0
T112	0	64	0	0
T122	0	52	0	0
T232	0	67	0	0
T279	0	36	0	0
T287	0	52	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4297	0	0
T4	454461	27	0	0
T7	156332	0	0	0
T11	0	47	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	28	0	0
T50	0	70	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	10	0	0
T112	0	20	0	0
T122	0	86	0	0
T232	0	78	0	0
T279	0	33	0	0
T287	0	64	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4220	0	0
T4	454461	17	0	0
T7	156332	0	0	0
T11	0	61	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	34	0	0
T50	0	80	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	6	0	0
T112	0	47	0	0
T122	0	67	0	0
T232	0	79	0	0
T279	0	57	0	0
T287	0	74	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4410	0	0
T4	454461	21	0	0
T7	156332	0	0	0
T11	0	38	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	34	0	0
T50	0	84	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	26	0	0
T112	0	49	0	0
T122	0	66	0	0
T232	0	69	0	0
T279	0	50	0	0
T287	0	81	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4414	0	0
T4	454461	23	0	0
T7	156332	0	0	0
T11	0	33	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	23	0	0
T50	0	70	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	8	0	0
T112	0	49	0	0
T122	0	60	0	0
T232	0	60	0	0
T279	0	39	0	0
T287	0	60	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2480	0	0
T4	454461	1	0	0
T7	156332	0	0	0
T11	0	23	0	0
T23	46783	0	0	0
T25	57449	0	0	0
T37	0	45	0	0
T50	0	29	0	0
T51	184954	0	0	0
T62	468541	0	0	0
T65	0	3	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T75	128203	0	0	0
T78	103746	0	0	0
T90	0	51	0	0
T112	0	12	0	0
T197	0	2	0	0
T279	0	11	0	0
T287	0	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1995	0	0
T37	146164	24	0	0
T56	360473	0	0	0
T90	0	12	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	9	0	0
T159	0	13	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T304	0	50	0	0
T307	0	34	0	0
T308	0	34	0	0
T311	0	14	0	0
T312	0	14	0	0
T313	0	21	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4055	0	0
T37	146164	29	0	0
T40	0	4	0	0
T44	0	4	0	0
T45	0	9	0	0
T47	0	1	0	0
T56	360473	0	0	0
T90	0	13	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	18	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T179	0	3	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T266	0	10	0	0
T304	0	9	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1422	0	0
T32	0	8	0	0
T37	146164	27	0	0
T56	360473	0	0	0
T90	0	14	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	16	0	0
T159	0	16	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T226	0	9	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T304	0	8	0	0
T307	0	44	0	0
T308	0	7	0	0
T309	0	24	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4321	0	0
T37	146164	109	0	0
T56	360473	0	0	0
T67	0	64	0	0
T69	0	58	0	0
T71	0	37	0	0
T90	0	16	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	26	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T265	0	65	0	0
T314	0	50	0	0
T315	0	52	0	0
T316	0	37	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	5454	0	0
T11	748762	48	0	0
T12	67102	0	0	0
T27	153830	0	0	0
T35	125590	0	0	0
T37	0	158	0	0
T53	320934	0	0	0
T54	135580	0	0	0
T65	0	68	0	0
T82	238371	0	0	0
T90	0	91	0	0
T147	0	23	0	0
T151	51213	0	0	0
T152	220860	0	0	0
T293	206749	0	0	0
T304	0	150	0	0
T317	0	58	0	0
T318	0	51	0	0
T319	0	59	0	0
T320	0	51	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	3708	0	0
T11	748762	48	0	0
T12	67102	0	0	0
T27	153830	0	0	0
T35	125590	0	0	0
T37	0	136	0	0
T53	320934	0	0	0
T54	135580	0	0	0
T65	0	66	0	0
T82	238371	0	0	0
T90	0	95	0	0
T147	0	10	0	0
T151	51213	0	0	0
T152	220860	0	0	0
T293	206749	0	0	0
T304	0	139	0	0
T317	0	56	0	0
T318	0	69	0	0
T319	0	48	0	0
T320	0	65	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	4146	0	0
T11	748762	50	0	0
T12	67102	0	0	0
T27	153830	0	0	0
T35	125590	0	0	0
T37	0	158	0	0
T53	320934	0	0	0
T54	135580	0	0	0
T65	0	84	0	0
T82	238371	0	0	0
T90	0	95	0	0
T147	0	33	0	0
T151	51213	0	0	0
T152	220860	0	0	0
T293	206749	0	0	0
T304	0	166	0	0
T317	0	65	0	0
T318	0	41	0	0
T319	0	64	0	0
T320	0	69	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1640	0	0
T32	0	11	0	0
T37	146164	18	0	0
T56	360473	0	0	0
T90	0	20	0	0
T144	188247	0	0	0
T145	402909	0	0	0
T147	0	22	0	0
T159	0	19	0	0
T162	351894	0	0	0
T163	34471	0	0	0
T164	47392	0	0	0
T165	50855	0	0	0
T226	0	4	0	0
T259	432681	0	0	0
T260	50791	0	0	0
T304	0	19	0	0
T307	0	42	0	0
T309	0	26	0	0
T310	0	142	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1464	0	0
T36	244858	0	0	0
T37	0	19	0	0
T43	314738	0	0	0
T50	544840	0	0	0
T55	33921	0	0	0
T63	147538	5	0	0
T64	18993	0	0	0
T65	0	4	0	0
T90	0	20	0	0
T134	42759	0	0	0
T147	0	20	0	0
T150	0	14	0	0
T168	0	7	0	0
T206	48570	0	0	0
T207	92576	0	0	0
T208	55685	0	0	0
T304	0	14	0	0
T311	0	8	0	0
T321	0	1	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1487	0	0
T36	244858	0	0	0
T37	0	35	0	0
T43	314738	0	0	0
T50	544840	0	0	0
T55	33921	0	0	0
T63	147538	5	0	0
T64	18993	0	0	0
T65	0	6	0	0
T90	0	25	0	0
T134	42759	0	0	0
T147	0	9	0	0
T150	0	15	0	0
T168	0	7	0	0
T206	48570	0	0	0
T207	92576	0	0	0
T208	55685	0	0	0
T304	0	15	0	0
T307	0	58	0	0
T321	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1498	0	0
T10	64615	5	0	0
T11	748762	0	0	0
T12	67102	0	0	0
T35	125590	0	0	0
T37	0	32	0	0
T53	320934	0	0	0
T54	135580	0	0	0
T63	0	1	0	0
T65	0	3	0	0
T82	238371	0	0	0
T90	0	18	0	0
T147	0	14	0	0
T150	0	11	0	0
T151	51213	0	0	0
T152	220860	0	0	0
T168	0	8	0	0
T293	206749	0	0	0
T304	0	19	0	0
T321	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1464	0	0
T8	130215	0	0	0
T9	108758	0	0	0
T10	64615	0	0	0
T11	748762	0	0	0
T12	67102	0	0	0
T23	46783	14	0	0
T37	0	23	0	0
T51	184954	0	0	0
T52	976309	0	0	0
T63	0	3	0	0
T65	0	2	0	0
T76	241017	0	0	0
T82	238371	0	0	0
T90	0	32	0	0
T147	0	19	0	0
T168	0	6	0	0
T304	0	9	0	0
T311	0	1	0	0
T321	0	3	0	0