Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T23,T9,T10
1	-	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T15,T31
0	0	1	Covered	T1,T15,T31
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T15,T31
0	0	1	Covered	T1,T15,T31
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	114473111	0	0
DstReqKnown_A	250649972	222750184	0	0
SrcAckBusyChk_A	2147483647	117283	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	114473111	0	0
T1	3331336	9696	0	0
T2	418884	2774	0	0
T3	691654	745	0	0
T4	0	5753	0	0
T5	2006688	0	0	0
T6	393120	0	0	0
T11	0	23496	0	0
T13	2024768	0	0	0
T14	1967088	0	0	0
T15	2286928	0	0	0
T16	3444260	13987	0	0
T17	488250	0	0	0
T18	167720	0	0	0
T19	604500	0	0	0
T24	118482	0	0	0
T26	522736	0	0	0
T27	0	22484	0	0
T28	347742	6663	0	0
T29	363077	15013	0	0
T30	259974	2858	0	0
T31	208402	0	0	0
T35	0	3684	0	0
T37	0	1816	0	0
T38	0	5502	0	0
T48	0	774	0	0
T51	0	260	0	0
T52	0	1354	0	0
T53	0	4830	0	0
T54	0	5491	0	0
T55	0	1369	0	0
T56	0	10483	0	0
T57	0	11986	0	0
T58	121442	0	0	0
T59	52806	0	0	0
T60	53340	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250649972	222750184	0	0
T1	577864	563550	0	0
T5	17748	4148	0	0
T6	13906	306	0	0
T13	17748	4148	0	0
T14	17068	3468	0	0
T15	20026	6426	0	0
T16	23392	9792	0	0
T17	13838	238	0	0
T18	14246	646	0	0
T19	17850	4250	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117283	0	0
T1	3331336	12	0	0
T2	418884	8	0	0
T3	691654	1	0	0
T4	0	4	0	0
T5	2006688	0	0	0
T6	393120	0	0	0
T11	0	15	0	0
T13	2024768	0	0	0
T14	1967088	0	0	0
T15	2286928	0	0	0
T16	3444260	8	0	0
T17	488250	0	0	0
T18	167720	0	0	0
T19	604500	0	0	0
T24	118482	0	0	0
T26	522736	0	0	0
T27	0	13	0	0
T28	347742	7	0	0
T29	363077	9	0	0
T30	259974	2	0	0
T31	208402	0	0	0
T35	0	8	0	0
T37	0	6	0	0
T38	0	3	0	0
T48	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	9	0	0
T55	0	8	0	0
T56	0	6	0	0
T57	0	8	0	0
T58	121442	0	0	0
T59	52806	0	0	0
T60	53340	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14158178	14140396	0	0
T5	8528424	8526452	0	0
T6	1670760	1668210	0	0
T13	8605264	8602476	0	0
T14	8360124	8357914	0	0
T15	9719444	9716690	0	0
T16	11710484	11708784	0	0
T17	1660050	1658316	0	0
T18	570248	568310	0	0
T19	2055300	2053430	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T38,T61,T20
1	-	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1221832	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1206	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1221832	0	0
T1	416417	4148	0	0
T2	0	2070	0	0
T4	0	5905	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T9	0	646	0	0
T10	0	377	0	0
T11	0	3238	0	0
T12	0	428	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	7439	0	0
T35	0	1366	0	0
T49	0	203	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1206	0	0
T1	416417	5	0	0
T2	0	6	0	0
T4	0	4	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	4	0	0
T35	0	3	0	0
T49	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T15,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T15,T2
1	1	Covered	T1,T15,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T15,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T15,T2
1	1	Covered	T1,T15,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T15,T2
0	0	1	Covered	T1,T15,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T15,T2
0	0	1	Covered	T1,T15,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	2120933	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	2093	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2120933	0	0
T1	416417	4758	0	0
T2	0	1271	0	0
T3	0	741	0	0
T4	0	2614	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T7	0	478	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	1449	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	1400	0	0
T51	0	136	0	0
T52	0	542	0	0
T62	0	1915	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2093	0	0
T1	416417	6	0	0
T2	0	4	0	0
T3	0	1	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T7	0	1	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	1	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T62	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T31,T23,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T31,T23,T8
1	1	Covered	T31,T23,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T31,T23,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T23,T8
1	1	Covered	T31,T23,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T31,T23,T8
0	0	1	Covered	T31,T23,T8
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T31,T23,T8
0	0	1	Covered	T31,T23,T8
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1266219	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1067	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1266219	0	0
T2	139628	0	0	0
T3	691654	0	0	0
T8	0	1436	0	0
T9	0	2289	0	0
T10	0	961	0	0
T12	0	1013	0	0
T23	0	758	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	0	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T31	104201	2132	0	0
T58	60721	0	0	0
T59	52806	0	0	0
T63	0	1434	0	0
T64	0	134	0	0
T65	0	723	0	0
T66	0	817	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1067	0	0
T2	139628	0	0	0
T3	691654	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	0	2	0	0
T12	0	2	0	0
T23	0	2	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	0	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T31	104201	3	0	0
T58	60721	0	0	0
T59	52806	0	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T31,T23,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T31,T23,T8
1	1	Covered	T31,T23,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T31,T23,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T23,T8
1	1	Covered	T31,T23,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T31,T23,T8
0	0	1	Covered	T31,T23,T8
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T31,T23,T8
0	0	1	Covered	T31,T23,T8
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1270429	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1101	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1270429	0	0
T2	139628	0	0	0
T3	691654	0	0	0
T8	0	1434	0	0
T9	0	2270	0	0
T10	0	952	0	0
T12	0	1009	0	0
T23	0	738	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	0	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T31	104201	2113	0	0
T58	60721	0	0	0
T59	52806	0	0	0
T63	0	1418	0	0
T64	0	132	0	0
T65	0	714	0	0
T66	0	813	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1101	0	0
T2	139628	0	0	0
T3	691654	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	0	2	0	0
T12	0	2	0	0
T23	0	2	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	0	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T31	104201	3	0	0
T58	60721	0	0	0
T59	52806	0	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T31,T23,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T31,T23,T8
1	1	Covered	T31,T23,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T31,T23,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T23,T8
1	1	Covered	T31,T23,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T31,T23,T8
0	0	1	Covered	T31,T23,T8
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T31,T23,T8
0	0	1	Covered	T31,T23,T8
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1257362	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1069	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1257362	0	0
T2	139628	0	0	0
T3	691654	0	0	0
T8	0	1432	0	0
T9	0	2235	0	0
T10	0	939	0	0
T12	0	1005	0	0
T23	0	719	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	0	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T31	104201	2095	0	0
T58	60721	0	0	0
T59	52806	0	0	0
T63	0	1413	0	0
T64	0	130	0	0
T65	0	701	0	0
T66	0	796	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1069	0	0
T2	139628	0	0	0
T3	691654	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	0	2	0	0
T12	0	2	0	0
T23	0	2	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	0	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T31	104201	3	0	0
T58	60721	0	0	0
T59	52806	0	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T24,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T24,T3,T25
1	1	Covered	T24,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T24,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T25
1	1	Covered	T24,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T24,T3,T25
0	0	1	Covered	T24,T3,T25
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T24,T3,T25
0	0	1	Covered	T24,T3,T25
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	2671201	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	2724	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2671201	0	0
T2	139628	0	0	0
T3	691654	17502	0	0
T4	454461	0	0	0
T24	59241	8281	0	0
T25	0	8147	0	0
T28	173871	0	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T37	0	7339	0	0
T53	0	35413	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T67	0	9482	0	0
T68	0	8776	0	0
T69	0	17128	0	0
T70	0	8532	0	0
T71	0	32997	0	0
T72	120491	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2724	0	0
T2	139628	0	0	0
T3	691654	20	0	0
T4	454461	0	0	0
T24	59241	20	0	0
T25	0	20	0	0
T28	173871	0	0	0
T29	363077	0	0	0
T30	259974	0	0	0
T37	0	20	0	0
T53	0	20	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	120491	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	5893757	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	6357	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	5893757	0	0
T3	0	18421	0	0
T5	250836	34654	0	0
T6	49140	0	0	0
T13	253096	34849	0	0
T14	245886	35209	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	7500	0	0
T24	0	354	0	0
T26	0	35466	0	0
T31	104201	0	0	0
T58	0	8689	0	0
T72	0	15818	0	0
T73	0	8221	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	6357	0	0
T3	0	21	0	0
T5	250836	20	0	0
T6	49140	0	0	0
T13	253096	20	0	0
T14	245886	20	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	20	0	0
T24	0	1	0	0
T26	0	20	0	0
T31	104201	0	0	0
T58	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	7003785	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7527	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7003785	0	0
T1	416417	4883	0	0
T2	0	1424	0	0
T5	250836	34968	0	0
T6	49140	0	0	0
T13	253096	34929	0	0
T14	245886	35289	0	0
T15	285866	1451	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	7815	0	0
T24	0	356	0	0
T26	0	35886	0	0
T58	0	8769	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7527	0	0
T1	416417	6	0	0
T2	0	4	0	0
T5	250836	20	0	0
T6	49140	0	0	0
T13	253096	20	0	0
T14	245886	20	0	0
T15	285866	1	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	20	0	0
T24	0	1	0	0
T26	0	20	0	0
T58	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	5810196	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	6240	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	5810196	0	0
T3	0	17466	0	0
T5	250836	34822	0	0
T6	49140	0	0	0
T7	0	15891	0	0
T13	253096	34889	0	0
T14	245886	35249	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	7671	0	0
T26	0	35681	0	0
T31	104201	0	0	0
T58	0	8729	0	0
T72	0	16007	0	0
T73	0	8369	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	6240	0	0
T3	0	20	0	0
T5	250836	20	0	0
T6	49140	0	0	0
T7	0	40	0	0
T13	253096	20	0	0
T14	245886	20	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	20	0	0
T26	0	20	0	0
T31	104201	0	0	0
T58	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T8,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T8,T27
1	1	Covered	T7,T8,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T8,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T27
1	1	Covered	T7,T8,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T8,T27
0	0	1	Covered	T7,T8,T27
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T8,T27
0	0	1	Covered	T7,T8,T27
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1336406	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1085	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1336406	0	0
T7	156332	477	0	0
T8	130215	1436	0	0
T9	108758	0	0	0
T10	64615	0	0	0
T11	748762	0	0	0
T23	46783	0	0	0
T27	0	1982	0	0
T37	0	314	0	0
T38	0	48457	0	0
T41	0	134	0	0
T42	0	480	0	0
T43	0	1439	0	0
T45	0	992	0	0
T51	184954	0	0	0
T52	976309	0	0	0
T74	0	977	0	0
T75	128203	0	0	0
T76	241017	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1085	0	0
T7	156332	1	0	0
T8	130215	1	0	0
T9	108758	0	0	0
T10	64615	0	0	0
T11	748762	0	0	0
T23	46783	0	0	0
T27	0	1	0	0
T37	0	1	0	0
T38	0	28	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T51	184954	0	0	0
T52	976309	0	0	0
T74	0	1	0	0
T75	128203	0	0	0
T76	241017	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	2072515	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	2079	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2072515	0	0
T1	416417	4746	0	0
T2	0	1263	0	0
T3	0	739	0	0
T4	0	2590	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T7	0	475	0	0
T8	0	1434	0	0
T11	0	6057	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	1398	0	0
T51	0	134	0	0
T52	0	532	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2079	0	0
T1	416417	6	0	0
T2	0	4	0	0
T3	0	1	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T16,T28,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T16,T28,T29
1	1	Covered	T16,T28,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T16,T28,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T28,T29
1	1	Covered	T16,T28,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T16,T28,T29
0	0	1	Covered	T16,T28,T29
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T16,T28,T29
0	0	1	Covered	T16,T28,T29
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1447926	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1293	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1447926	0	0
T2	139628	0	0	0
T11	0	6074	0	0
T16	344426	8997	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	3815	0	0
T29	0	10176	0	0
T31	104201	0	0	0
T37	0	921	0	0
T38	0	3501	0	0
T54	0	3603	0	0
T55	0	866	0	0
T56	0	5255	0	0
T57	0	7676	0	0
T58	60721	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1293	0	0
T2	139628	0	0	0
T11	0	4	0	0
T16	344426	5	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	4	0	0
T29	0	6	0	0
T31	104201	0	0	0
T37	0	3	0	0
T38	0	2	0	0
T54	0	6	0	0
T55	0	5	0	0
T56	0	3	0	0
T57	0	5	0	0
T58	60721	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T16,T28,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T16,T28,T29
1	1	Covered	T16,T28,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T16,T28,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T28,T29
1	1	Covered	T16,T28,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T16,T28,T29
0	0	1	Covered	T16,T28,T29
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T16,T28,T29
0	0	1	Covered	T16,T28,T29
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1310032	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1134	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1310032	0	0
T2	139628	0	0	0
T11	0	4656	0	0
T16	344426	4990	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	2848	0	0
T29	0	4837	0	0
T31	104201	0	0	0
T37	0	895	0	0
T38	0	2001	0	0
T54	0	1888	0	0
T55	0	503	0	0
T56	0	5228	0	0
T57	0	4310	0	0
T58	60721	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1134	0	0
T2	139628	0	0	0
T11	0	3	0	0
T16	344426	3	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T24	59241	0	0	0
T26	261368	0	0	0
T28	173871	3	0	0
T29	0	3	0	0
T31	104201	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T54	0	3	0	0
T55	0	3	0	0
T56	0	3	0	0
T57	0	3	0	0
T58	60721	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	6804191	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7122	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	6804191	0	0
T2	139628	23903	0	0
T3	691654	0	0	0
T4	454461	125526	0	0
T29	363077	0	0	0
T30	259974	82958	0	0
T38	0	17985	0	0
T48	0	26614	0	0
T49	0	6824	0	0
T50	0	67518	0	0
T51	0	6083	0	0
T52	0	42139	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	21723	0	0
T78	103746	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7122	0	0
T2	139628	65	0	0
T3	691654	0	0	0
T4	454461	72	0	0
T29	363077	0	0	0
T30	259974	51	0	0
T38	0	11	0	0
T48	0	68	0	0
T49	0	60	0	0
T50	0	83	0	0
T51	0	51	0	0
T52	0	51	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	51	0	0
T78	103746	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	6906584	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7325	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	6906584	0	0
T2	139628	19500	0	0
T3	691654	0	0	0
T4	454461	146580	0	0
T29	363077	0	0	0
T30	259974	82748	0	0
T38	0	17979	0	0
T48	0	36549	0	0
T49	0	6614	0	0
T50	0	68023	0	0
T51	0	5873	0	0
T52	0	41392	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	20965	0	0
T78	103746	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7325	0	0
T2	139628	54	0	0
T3	691654	0	0	0
T4	454461	85	0	0
T29	363077	0	0	0
T30	259974	51	0	0
T38	0	11	0	0
T48	0	93	0	0
T49	0	62	0	0
T50	0	85	0	0
T51	0	51	0	0
T52	0	51	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	51	0	0
T78	103746	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	6619087	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7207	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	6619087	0	0
T2	139628	24407	0	0
T3	691654	0	0	0
T4	454461	117808	0	0
T29	363077	0	0	0
T30	259974	82538	0	0
T38	0	17979	0	0
T48	0	23758	0	0
T49	0	8309	0	0
T50	0	71197	0	0
T51	0	5663	0	0
T52	0	40566	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	20230	0	0
T78	103746	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7207	0	0
T2	139628	67	0	0
T3	691654	0	0	0
T4	454461	69	0	0
T29	363077	0	0	0
T30	259974	51	0	0
T38	0	11	0	0
T48	0	62	0	0
T49	0	77	0	0
T50	0	91	0	0
T51	0	51	0	0
T52	0	51	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	51	0	0
T78	103746	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	6856567	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7359	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	6856567	0	0
T2	139628	29179	0	0
T3	691654	0	0	0
T4	454461	108172	0	0
T29	363077	0	0	0
T30	259974	82328	0	0
T38	0	17979	0	0
T48	0	35915	0	0
T49	0	8232	0	0
T50	0	51529	0	0
T51	0	5453	0	0
T52	0	39804	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	19600	0	0
T78	103746	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7359	0	0
T2	139628	80	0	0
T3	691654	0	0	0
T4	454461	64	0	0
T29	363077	0	0	0
T30	259974	51	0	0
T38	0	11	0	0
T48	0	93	0	0
T49	0	77	0	0
T50	0	68	0	0
T51	0	51	0	0
T52	0	51	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	51	0	0
T78	103746	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1481782	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1330	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1481782	0	0
T2	139628	1423	0	0
T3	691654	0	0	0
T4	454461	2985	0	0
T29	363077	0	0	0
T30	259974	1438	0	0
T38	0	14967	0	0
T48	0	802	0	0
T49	0	357	0	0
T50	0	7078	0	0
T51	0	139	0	0
T52	0	710	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	482	0	0
T78	103746	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1330	0	0
T2	139628	4	0	0
T3	691654	0	0	0
T4	454461	2	0	0
T29	363077	0	0	0
T30	259974	1	0	0
T38	0	9	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	8	0	0
T51	0	1	0	0
T52	0	1	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	1	0	0
T78	103746	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1458068	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1308	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1458068	0	0
T2	139628	1383	0	0
T3	691654	0	0	0
T4	454461	2865	0	0
T29	363077	0	0	0
T30	259974	1428	0	0
T38	0	14961	0	0
T48	0	782	0	0
T49	0	374	0	0
T50	0	6650	0	0
T51	0	129	0	0
T52	0	675	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	452	0	0
T78	103746	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1308	0	0
T2	139628	4	0	0
T3	691654	0	0	0
T4	454461	2	0	0
T29	363077	0	0	0
T30	259974	1	0	0
T38	0	9	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	8	0	0
T51	0	1	0	0
T52	0	1	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	1	0	0
T78	103746	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1502825	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1359	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1502825	0	0
T2	139628	1343	0	0
T3	691654	0	0	0
T4	454461	2779	0	0
T29	363077	0	0	0
T30	259974	1418	0	0
T38	0	14961	0	0
T48	0	762	0	0
T49	0	354	0	0
T50	0	6213	0	0
T51	0	119	0	0
T52	0	629	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	411	0	0
T78	103746	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1359	0	0
T2	139628	4	0	0
T3	691654	0	0	0
T4	454461	2	0	0
T29	363077	0	0	0
T30	259974	1	0	0
T38	0	9	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	8	0	0
T51	0	1	0	0
T52	0	1	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	1	0	0
T78	103746	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T4
1	1	Covered	T2,T30,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T30,T4
0	0	1	Covered	T2,T30,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1476000	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1324	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1476000	0	0
T2	139628	1303	0	0
T3	691654	0	0	0
T4	454461	2700	0	0
T29	363077	0	0	0
T30	259974	1408	0	0
T38	0	14961	0	0
T48	0	742	0	0
T49	0	340	0	0
T50	0	5832	0	0
T51	0	109	0	0
T52	0	582	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	493	0	0
T78	103746	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1324	0	0
T2	139628	4	0	0
T3	691654	0	0	0
T4	454461	2	0	0
T29	363077	0	0	0
T30	259974	1	0	0
T38	0	9	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	8	0	0
T51	0	1	0	0
T52	0	1	0	0
T59	52806	0	0	0
T60	53340	0	0	0
T72	120491	0	0	0
T73	65794	0	0	0
T77	0	1	0	0
T78	103746	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	7443123	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7807	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7443123	0	0
T1	416417	4902	0	0
T2	0	24009	0	0
T3	0	747	0	0
T4	0	126159	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6564	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	83054	0	0
T35	0	1878	0	0
T51	0	6179	0	0
T52	0	42500	0	0
T53	0	4836	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7807	0	0
T1	416417	6	0	0
T2	0	65	0	0
T3	0	1	0	0
T4	0	72	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	51	0	0
T35	0	4	0	0
T51	0	51	0	0
T52	0	51	0	0
T53	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	7412446	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7856	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7412446	0	0
T1	416417	4890	0	0
T2	0	19584	0	0
T4	0	147274	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6522	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	22853	0	0
T30	0	82844	0	0
T35	0	1870	0	0
T48	0	36723	0	0
T51	0	5969	0	0
T52	0	41709	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7856	0	0
T1	416417	6	0	0
T2	0	54	0	0
T4	0	85	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	51	0	0
T35	0	4	0	0
T48	0	93	0	0
T51	0	51	0	0
T52	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	7196429	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7836	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7196429	0	0
T1	416417	4878	0	0
T2	0	24517	0	0
T4	0	118344	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6476	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	22762	0	0
T30	0	82634	0	0
T35	0	1862	0	0
T48	0	23870	0	0
T51	0	5759	0	0
T52	0	40936	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7836	0	0
T1	416417	6	0	0
T2	0	67	0	0
T4	0	69	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	51	0	0
T35	0	4	0	0
T48	0	62	0	0
T51	0	51	0	0
T52	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	7437807	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	7963	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7437807	0	0
T1	416417	4866	0	0
T2	0	29315	0	0
T4	0	108689	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6445	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	22675	0	0
T30	0	82424	0	0
T35	0	1854	0	0
T48	0	36089	0	0
T51	0	5584	0	0
T52	0	40140	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	7963	0	0
T1	416417	6	0	0
T2	0	80	0	0
T4	0	64	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	51	0	0
T35	0	4	0	0
T48	0	93	0	0
T51	0	51	0	0
T52	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	2069207	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1985	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2069207	0	0
T1	416417	4854	0	0
T2	0	1407	0	0
T3	0	745	0	0
T4	0	2937	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6404	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	1434	0	0
T35	0	1846	0	0
T51	0	135	0	0
T52	0	699	0	0
T53	0	4830	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1985	0	0
T1	416417	6	0	0
T2	0	4	0	0
T3	0	1	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	1	0	0
T35	0	4	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	2002638	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1926	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2002638	0	0
T1	416417	4842	0	0
T2	0	1367	0	0
T4	0	2816	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6362	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	22484	0	0
T30	0	1424	0	0
T35	0	1838	0	0
T48	0	774	0	0
T51	0	125	0	0
T52	0	655	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1926	0	0
T1	416417	6	0	0
T2	0	4	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	1	0	0
T35	0	4	0	0
T48	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1963853	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1923	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1963853	0	0
T1	416417	4830	0	0
T2	0	1327	0	0
T4	0	2752	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6331	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	22383	0	0
T30	0	1414	0	0
T35	0	1830	0	0
T48	0	754	0	0
T51	0	115	0	0
T52	0	610	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1923	0	0
T1	416417	6	0	0
T2	0	4	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	1	0	0
T35	0	4	0	0
T48	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	2001527	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1938	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2001527	0	0
T1	416417	4818	0	0
T2	0	1287	0	0
T4	0	2665	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6286	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	22276	0	0
T30	0	1404	0	0
T35	0	1822	0	0
T48	0	734	0	0
T51	0	140	0	0
T52	0	562	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1938	0	0
T1	416417	6	0	0
T2	0	4	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	1	0	0
T35	0	4	0	0
T48	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	2045624	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1982	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2045624	0	0
T1	416417	4806	0	0
T2	0	1399	0	0
T3	0	743	0	0
T4	0	2910	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6247	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	1432	0	0
T35	0	1814	0	0
T51	0	133	0	0
T52	0	687	0	0
T53	0	4824	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1982	0	0
T1	416417	6	0	0
T2	0	4	0	0
T3	0	1	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T30	0	1	0	0
T35	0	4	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	2009180	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1936	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	2009180	0	0
T1	416417	4794	0	0
T2	0	1359	0	0
T4	0	2804	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6213	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	22108	0	0
T30	0	1422	0	0
T35	0	1806	0	0
T48	0	770	0	0
T51	0	123	0	0
T52	0	645	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1936	0	0
T1	416417	6	0	0
T2	0	4	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	1	0	0
T35	0	4	0	0
T48	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1950218	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1908	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1950218	0	0
T1	416417	4782	0	0
T2	0	1319	0	0
T4	0	2735	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6175	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	22042	0	0
T30	0	1412	0	0
T35	0	1798	0	0
T48	0	750	0	0
T51	0	113	0	0
T52	0	599	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1908	0	0
T1	416417	6	0	0
T2	0	4	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	1	0	0
T35	0	4	0	0
T48	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T30
0	0	1	Covered	T1,T2,T30
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1913359	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1867	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1913359	0	0
T1	416417	4770	0	0
T2	0	1279	0	0
T4	0	2634	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	6143	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	21948	0	0
T30	0	1402	0	0
T35	0	1790	0	0
T48	0	730	0	0
T51	0	138	0	0
T52	0	552	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1867	0	0
T1	416417	6	0	0
T2	0	4	0	0
T4	0	2	0	0
T5	250836	0	0	0
T6	49140	0	0	0
T11	0	4	0	0
T13	253096	0	0	0
T14	245886	0	0	0
T15	285866	0	0	0
T16	344426	0	0	0
T17	48825	0	0	0
T18	16772	0	0	0
T19	60450	0	0	0
T27	0	13	0	0
T30	0	1	0	0
T35	0	4	0	0
T48	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T23,T9,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T23,T9,T10
1	1	Covered	T23,T9,T10

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T23,T9,T10
1	-	Covered	T23,T9,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T23,T9,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T23,T9,T10
1	1	Covered	T23,T9,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T23,T9,T10
0	0	1	Covered	T23,T9,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T23,T9,T10
0	0	1	Covered	T23,T9,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1292664939	1240003	0	0
DstReqKnown_A	7372058	6551476	0	0
SrcAckBusyChk_A	1292664939	1047	0	0
SrcBusyKnown_A	1292664939	1290902614	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1240003	0	0
T8	130215	0	0	0
T9	108758	1344	0	0
T10	64615	939	0	0
T11	748762	0	0	0
T12	67102	1010	0	0
T23	46783	768	0	0
T38	0	5991	0	0
T51	184954	0	0	0
T52	976309	0	0	0
T65	0	1431	0	0
T66	0	813	0	0
T76	241017	0	0	0
T79	0	665	0	0
T80	0	3473	0	0
T81	0	1476	0	0
T82	238371	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7372058	6551476	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1047	0	0
T8	130215	0	0	0
T9	108758	2	0	0
T10	64615	2	0	0
T11	748762	0	0	0
T12	67102	2	0	0
T23	46783	2	0	0
T38	0	4	0	0
T51	184954	0	0	0
T52	976309	0	0	0
T65	0	2	0	0
T66	0	2	0	0
T76	241017	0	0	0
T79	0	4	0	0
T80	0	2	0	0
T81	0	6	0	0
T82	238371	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292664939	1290902614	0	0
T1	416417	415894	0	0
T5	250836	250778	0	0
T6	49140	49065	0	0
T13	253096	253014	0	0
T14	245886	245821	0	0
T15	285866	285785	0	0
T16	344426	344376	0	0
T17	48825	48774	0	0
T18	16772	16715	0	0
T19	60450	60395	0	0