Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T5 |
9 |
|
T10 |
13 |
|
T26 |
15 |
| auto[1] |
826 |
1 |
|
|
T5 |
11 |
|
T10 |
7 |
|
T26 |
5 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T5 |
9 |
|
T10 |
12 |
|
T26 |
10 |
| auto[1] |
829 |
1 |
|
|
T5 |
11 |
|
T10 |
8 |
|
T26 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T5 |
10 |
|
T10 |
12 |
|
T26 |
8 |
| auto[1] |
866 |
1 |
|
|
T5 |
10 |
|
T10 |
8 |
|
T26 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
835 |
1 |
|
|
T5 |
13 |
|
T10 |
5 |
|
T26 |
6 |
| auto[1] |
845 |
1 |
|
|
T5 |
7 |
|
T10 |
15 |
|
T26 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T5 |
8 |
|
T10 |
8 |
|
T26 |
11 |
| auto[1] |
822 |
1 |
|
|
T5 |
12 |
|
T10 |
12 |
|
T26 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T5 |
10 |
|
T10 |
9 |
|
T26 |
4 |
| auto[1] |
844 |
1 |
|
|
T5 |
10 |
|
T10 |
11 |
|
T26 |
16 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T5 |
11 |
|
T10 |
8 |
|
T26 |
9 |
| auto[1] |
804 |
1 |
|
|
T5 |
9 |
|
T10 |
12 |
|
T26 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T5 |
16 |
|
T10 |
9 |
|
T26 |
12 |
| auto[1] |
846 |
1 |
|
|
T5 |
4 |
|
T10 |
11 |
|
T26 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T5 |
10 |
|
T10 |
10 |
|
T26 |
9 |
| auto[1] |
813 |
1 |
|
|
T5 |
10 |
|
T10 |
10 |
|
T26 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
816 |
1 |
|
|
T5 |
6 |
|
T10 |
5 |
|
T26 |
9 |
| auto[1] |
864 |
1 |
|
|
T5 |
14 |
|
T10 |
15 |
|
T26 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
805 |
1 |
|
|
T5 |
6 |
|
T10 |
7 |
|
T26 |
7 |
| auto[1] |
875 |
1 |
|
|
T5 |
14 |
|
T10 |
13 |
|
T26 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T5 |
8 |
|
T10 |
12 |
|
T26 |
11 |
| auto[1] |
847 |
1 |
|
|
T5 |
12 |
|
T10 |
8 |
|
T26 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
857 |
1 |
|
|
T5 |
11 |
|
T10 |
13 |
|
T26 |
5 |
| auto[1] |
823 |
1 |
|
|
T5 |
9 |
|
T10 |
7 |
|
T26 |
15 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T5 |
9 |
|
T10 |
12 |
|
T26 |
10 |
| auto[1] |
829 |
1 |
|
|
T5 |
11 |
|
T10 |
8 |
|
T26 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T5 |
13 |
|
T10 |
11 |
|
T26 |
11 |
| auto[1] |
833 |
1 |
|
|
T5 |
7 |
|
T10 |
9 |
|
T26 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T5 |
12 |
|
T10 |
12 |
|
T26 |
5 |
| auto[1] |
844 |
1 |
|
|
T5 |
8 |
|
T10 |
8 |
|
T26 |
15 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T5 |
14 |
|
T10 |
12 |
|
T26 |
11 |
| auto[1] |
820 |
1 |
|
|
T5 |
6 |
|
T10 |
8 |
|
T26 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
822 |
1 |
|
|
T5 |
12 |
|
T10 |
11 |
|
T26 |
10 |
| auto[1] |
858 |
1 |
|
|
T5 |
8 |
|
T10 |
9 |
|
T26 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T5 |
11 |
|
T10 |
9 |
|
T26 |
8 |
| auto[1] |
804 |
1 |
|
|
T5 |
9 |
|
T10 |
11 |
|
T26 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
822 |
1 |
|
|
T5 |
10 |
|
T10 |
12 |
|
T26 |
11 |
| auto[1] |
858 |
1 |
|
|
T5 |
10 |
|
T10 |
8 |
|
T26 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
819 |
1 |
|
|
T5 |
7 |
|
T10 |
9 |
|
T26 |
8 |
| auto[1] |
861 |
1 |
|
|
T5 |
13 |
|
T10 |
11 |
|
T26 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
809 |
1 |
|
|
T5 |
7 |
|
T10 |
15 |
|
T26 |
11 |
| auto[1] |
871 |
1 |
|
|
T5 |
13 |
|
T10 |
5 |
|
T26 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T5 |
11 |
|
T10 |
13 |
|
T26 |
11 |
| auto[1] |
854 |
1 |
|
|
T5 |
9 |
|
T10 |
7 |
|
T26 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T5 |
8 |
|
T10 |
12 |
|
T26 |
11 |
| auto[1] |
847 |
1 |
|
|
T5 |
12 |
|
T10 |
8 |
|
T26 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
395 |
1 |
|
|
T5 |
6 |
|
T10 |
6 |
|
T26 |
4 |
| auto[0] |
auto[1] |
452 |
1 |
|
|
T5 |
7 |
|
T10 |
5 |
|
T26 |
7 |
| auto[1] |
auto[0] |
419 |
1 |
|
|
T5 |
4 |
|
T10 |
6 |
|
T26 |
4 |
| auto[1] |
auto[1] |
414 |
1 |
|
|
T5 |
3 |
|
T10 |
3 |
|
T26 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
400 |
1 |
|
|
T5 |
7 |
|
T10 |
3 |
|
T51 |
3 |
| auto[0] |
auto[1] |
436 |
1 |
|
|
T5 |
5 |
|
T10 |
9 |
|
T26 |
5 |
| auto[1] |
auto[0] |
435 |
1 |
|
|
T5 |
6 |
|
T10 |
2 |
|
T26 |
6 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T5 |
2 |
|
T10 |
6 |
|
T26 |
9 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T5 |
6 |
|
T10 |
6 |
|
T26 |
7 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T5 |
8 |
|
T10 |
6 |
|
T26 |
4 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T5 |
2 |
|
T10 |
2 |
|
T26 |
4 |
| auto[1] |
auto[1] |
393 |
1 |
|
|
T5 |
4 |
|
T10 |
6 |
|
T26 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
401 |
1 |
|
|
T5 |
6 |
|
T10 |
6 |
|
T26 |
3 |
| auto[0] |
auto[1] |
421 |
1 |
|
|
T5 |
6 |
|
T10 |
5 |
|
T26 |
7 |
| auto[1] |
auto[0] |
435 |
1 |
|
|
T5 |
4 |
|
T10 |
3 |
|
T26 |
1 |
| auto[1] |
auto[1] |
423 |
1 |
|
|
T5 |
4 |
|
T10 |
6 |
|
T26 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
466 |
1 |
|
|
T5 |
5 |
|
T10 |
3 |
|
T26 |
6 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T5 |
6 |
|
T10 |
6 |
|
T26 |
2 |
| auto[1] |
auto[0] |
410 |
1 |
|
|
T5 |
6 |
|
T10 |
5 |
|
T26 |
3 |
| auto[1] |
auto[1] |
394 |
1 |
|
|
T5 |
3 |
|
T10 |
6 |
|
T26 |
9 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
418 |
1 |
|
|
T5 |
7 |
|
T10 |
5 |
|
T26 |
9 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T5 |
3 |
|
T10 |
7 |
|
T26 |
2 |
| auto[1] |
auto[0] |
416 |
1 |
|
|
T5 |
9 |
|
T10 |
4 |
|
T26 |
3 |
| auto[1] |
auto[1] |
442 |
1 |
|
|
T5 |
1 |
|
T10 |
4 |
|
T26 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
382 |
1 |
|
|
T10 |
4 |
|
T26 |
5 |
|
T51 |
3 |
| auto[0] |
auto[1] |
427 |
1 |
|
|
T5 |
7 |
|
T10 |
11 |
|
T26 |
6 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T5 |
6 |
|
T10 |
1 |
|
T26 |
4 |
| auto[1] |
auto[1] |
437 |
1 |
|
|
T5 |
7 |
|
T10 |
4 |
|
T26 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
385 |
1 |
|
|
T5 |
2 |
|
T10 |
4 |
|
T26 |
4 |
| auto[0] |
auto[1] |
441 |
1 |
|
|
T5 |
9 |
|
T10 |
9 |
|
T26 |
7 |
| auto[1] |
auto[0] |
420 |
1 |
|
|
T5 |
4 |
|
T10 |
3 |
|
T26 |
3 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T5 |
5 |
|
T10 |
4 |
|
T26 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
435 |
1 |
|
|
T5 |
5 |
|
T10 |
7 |
|
T26 |
4 |
| auto[0] |
auto[1] |
422 |
1 |
|
|
T5 |
6 |
|
T10 |
6 |
|
T26 |
1 |
| auto[1] |
auto[0] |
419 |
1 |
|
|
T5 |
4 |
|
T10 |
6 |
|
T26 |
11 |
| auto[1] |
auto[1] |
404 |
1 |
|
|
T5 |
5 |
|
T10 |
1 |
|
T26 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
851 |
1 |
|
|
T5 |
9 |
|
T10 |
12 |
|
T26 |
10 |
| auto[1] |
auto[1] |
829 |
1 |
|
|
T5 |
11 |
|
T10 |
8 |
|
T26 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T5 |
3 |
|
T10 |
5 |
|
T26 |
4 |
| auto[0] |
auto[1] |
389 |
1 |
|
|
T5 |
4 |
|
T10 |
4 |
|
T26 |
4 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T5 |
7 |
|
T10 |
5 |
|
T26 |
5 |
| auto[1] |
auto[1] |
424 |
1 |
|
|
T5 |
6 |
|
T10 |
6 |
|
T26 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
833 |
1 |
|
|
T5 |
8 |
|
T10 |
12 |
|
T26 |
11 |
| auto[1] |
auto[1] |
847 |
1 |
|
|
T5 |
12 |
|
T10 |
8 |
|
T26 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
98 |
1 |
|
|
T5 |
11 |
|
T282 |
9 |
|
T78 |
6 |
| auto[1] |
122 |
1 |
|
|
T5 |
9 |
|
T282 |
11 |
|
T78 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T5 |
12 |
|
T282 |
10 |
|
T78 |
9 |
| auto[1] |
103 |
1 |
|
|
T5 |
8 |
|
T282 |
10 |
|
T78 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T5 |
10 |
|
T282 |
10 |
|
T78 |
7 |
| auto[1] |
105 |
1 |
|
|
T5 |
10 |
|
T282 |
10 |
|
T78 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T5 |
9 |
|
T282 |
9 |
|
T78 |
8 |
| auto[1] |
110 |
1 |
|
|
T5 |
11 |
|
T282 |
11 |
|
T78 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T5 |
12 |
|
T282 |
9 |
|
T78 |
14 |
| auto[1] |
110 |
1 |
|
|
T5 |
8 |
|
T282 |
11 |
|
T78 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T5 |
9 |
|
T282 |
9 |
|
T78 |
10 |
| auto[1] |
117 |
1 |
|
|
T5 |
11 |
|
T282 |
11 |
|
T78 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T5 |
11 |
|
T282 |
8 |
|
T78 |
11 |
| auto[1] |
107 |
1 |
|
|
T5 |
9 |
|
T282 |
12 |
|
T78 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T5 |
13 |
|
T282 |
11 |
|
T78 |
8 |
| auto[1] |
104 |
1 |
|
|
T5 |
7 |
|
T282 |
9 |
|
T78 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T5 |
13 |
|
T282 |
8 |
|
T78 |
9 |
| auto[1] |
110 |
1 |
|
|
T5 |
7 |
|
T282 |
12 |
|
T78 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T5 |
11 |
|
T282 |
11 |
|
T78 |
12 |
| auto[1] |
110 |
1 |
|
|
T5 |
9 |
|
T282 |
9 |
|
T78 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T5 |
9 |
|
T282 |
8 |
|
T78 |
10 |
| auto[1] |
101 |
1 |
|
|
T5 |
11 |
|
T282 |
12 |
|
T78 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T5 |
9 |
|
T282 |
12 |
|
T78 |
9 |
| auto[1] |
110 |
1 |
|
|
T5 |
11 |
|
T282 |
8 |
|
T78 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T5 |
7 |
|
T282 |
11 |
|
T78 |
11 |
| auto[1] |
111 |
1 |
|
|
T5 |
13 |
|
T282 |
9 |
|
T78 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T5 |
12 |
|
T282 |
10 |
|
T78 |
9 |
| auto[1] |
103 |
1 |
|
|
T5 |
8 |
|
T282 |
10 |
|
T78 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T5 |
10 |
|
T282 |
9 |
|
T78 |
9 |
| auto[1] |
107 |
1 |
|
|
T5 |
10 |
|
T282 |
11 |
|
T78 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T5 |
11 |
|
T282 |
6 |
|
T78 |
12 |
| auto[1] |
112 |
1 |
|
|
T5 |
9 |
|
T282 |
14 |
|
T78 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
105 |
1 |
|
|
T5 |
9 |
|
T282 |
8 |
|
T78 |
12 |
| auto[1] |
115 |
1 |
|
|
T5 |
11 |
|
T282 |
12 |
|
T78 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T5 |
14 |
|
T282 |
10 |
|
T78 |
8 |
| auto[1] |
108 |
1 |
|
|
T5 |
6 |
|
T282 |
10 |
|
T78 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T5 |
13 |
|
T282 |
11 |
|
T78 |
14 |
| auto[1] |
86 |
1 |
|
|
T5 |
7 |
|
T282 |
9 |
|
T78 |
6 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T5 |
11 |
|
T282 |
10 |
|
T78 |
11 |
| auto[1] |
111 |
1 |
|
|
T5 |
9 |
|
T282 |
10 |
|
T78 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T5 |
10 |
|
T282 |
8 |
|
T78 |
12 |
| auto[1] |
110 |
1 |
|
|
T5 |
10 |
|
T282 |
12 |
|
T78 |
8 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T5 |
10 |
|
T282 |
13 |
|
T78 |
9 |
| auto[1] |
116 |
1 |
|
|
T5 |
10 |
|
T282 |
7 |
|
T78 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T5 |
6 |
|
T282 |
6 |
|
T78 |
15 |
| auto[1] |
105 |
1 |
|
|
T5 |
14 |
|
T282 |
14 |
|
T78 |
5 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T5 |
9 |
|
T282 |
12 |
|
T78 |
9 |
| auto[1] |
110 |
1 |
|
|
T5 |
11 |
|
T282 |
8 |
|
T78 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T5 |
3 |
|
T282 |
5 |
|
T78 |
2 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T5 |
7 |
|
T282 |
4 |
|
T78 |
7 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T5 |
7 |
|
T282 |
5 |
|
T78 |
5 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T5 |
3 |
|
T282 |
6 |
|
T78 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T5 |
3 |
|
T282 |
3 |
|
T78 |
4 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T5 |
8 |
|
T282 |
3 |
|
T78 |
8 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T5 |
6 |
|
T282 |
6 |
|
T78 |
4 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T5 |
3 |
|
T282 |
8 |
|
T78 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T5 |
5 |
|
T282 |
5 |
|
T78 |
8 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T5 |
4 |
|
T282 |
3 |
|
T78 |
4 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T5 |
7 |
|
T282 |
4 |
|
T78 |
6 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T5 |
4 |
|
T282 |
8 |
|
T78 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T5 |
6 |
|
T282 |
6 |
|
T78 |
4 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T5 |
8 |
|
T282 |
4 |
|
T78 |
4 |
| auto[1] |
auto[0] |
46 |
1 |
|
|
T5 |
3 |
|
T282 |
3 |
|
T78 |
6 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T5 |
3 |
|
T282 |
7 |
|
T78 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T5 |
7 |
|
T282 |
4 |
|
T78 |
8 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T5 |
6 |
|
T282 |
7 |
|
T78 |
6 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T5 |
4 |
|
T282 |
4 |
|
T78 |
3 |
| auto[1] |
auto[1] |
38 |
1 |
|
|
T5 |
3 |
|
T282 |
5 |
|
T78 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
54 |
1 |
|
|
T5 |
7 |
|
T282 |
5 |
|
T78 |
5 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T5 |
4 |
|
T282 |
5 |
|
T78 |
6 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T5 |
6 |
|
T282 |
6 |
|
T78 |
3 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T5 |
3 |
|
T282 |
4 |
|
T78 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
49 |
1 |
|
|
T5 |
7 |
|
T282 |
7 |
|
T78 |
5 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T5 |
3 |
|
T282 |
6 |
|
T78 |
4 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T5 |
4 |
|
T282 |
4 |
|
T78 |
7 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T5 |
6 |
|
T282 |
3 |
|
T78 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T5 |
4 |
|
T282 |
2 |
|
T78 |
7 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T5 |
2 |
|
T282 |
4 |
|
T78 |
8 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T5 |
5 |
|
T282 |
6 |
|
T78 |
3 |
| auto[1] |
auto[1] |
45 |
1 |
|
|
T5 |
9 |
|
T282 |
8 |
|
T78 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
48 |
1 |
|
|
T5 |
5 |
|
T282 |
5 |
|
T78 |
3 |
| auto[0] |
auto[1] |
61 |
1 |
|
|
T5 |
2 |
|
T282 |
6 |
|
T78 |
8 |
| auto[1] |
auto[0] |
50 |
1 |
|
|
T5 |
6 |
|
T282 |
4 |
|
T78 |
3 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T5 |
7 |
|
T282 |
5 |
|
T78 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
117 |
1 |
|
|
T5 |
12 |
|
T282 |
10 |
|
T78 |
9 |
| auto[1] |
auto[1] |
103 |
1 |
|
|
T5 |
8 |
|
T282 |
10 |
|
T78 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
55 |
1 |
|
|
T5 |
8 |
|
T282 |
4 |
|
T78 |
3 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T5 |
2 |
|
T282 |
4 |
|
T78 |
9 |
| auto[1] |
auto[0] |
55 |
1 |
|
|
T5 |
5 |
|
T282 |
4 |
|
T78 |
6 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T5 |
5 |
|
T282 |
8 |
|
T78 |
2 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
110 |
1 |
|
|
T5 |
9 |
|
T282 |
12 |
|
T78 |
9 |
| auto[1] |
auto[1] |
110 |
1 |
|
|
T5 |
11 |
|
T282 |
8 |
|
T78 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T268 |
12 |
|
T103 |
5 |
|
T104 |
12 |
| auto[1] |
48 |
1 |
|
|
T268 |
8 |
|
T103 |
15 |
|
T104 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T268 |
11 |
|
T103 |
11 |
|
T104 |
8 |
| auto[1] |
55 |
1 |
|
|
T268 |
9 |
|
T103 |
9 |
|
T104 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T268 |
10 |
|
T103 |
11 |
|
T104 |
12 |
| auto[1] |
45 |
1 |
|
|
T268 |
10 |
|
T103 |
9 |
|
T104 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T268 |
12 |
|
T103 |
7 |
|
T104 |
8 |
| auto[1] |
55 |
1 |
|
|
T268 |
8 |
|
T103 |
13 |
|
T104 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T268 |
8 |
|
T103 |
8 |
|
T104 |
7 |
| auto[1] |
55 |
1 |
|
|
T268 |
12 |
|
T103 |
12 |
|
T104 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T268 |
10 |
|
T103 |
11 |
|
T104 |
9 |
| auto[1] |
50 |
1 |
|
|
T268 |
10 |
|
T103 |
9 |
|
T104 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T268 |
7 |
|
T103 |
10 |
|
T104 |
14 |
| auto[1] |
50 |
1 |
|
|
T268 |
13 |
|
T103 |
10 |
|
T104 |
6 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T268 |
9 |
|
T103 |
12 |
|
T104 |
9 |
| auto[1] |
48 |
1 |
|
|
T268 |
11 |
|
T103 |
8 |
|
T104 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T268 |
8 |
|
T103 |
8 |
|
T104 |
8 |
| auto[1] |
58 |
1 |
|
|
T268 |
12 |
|
T103 |
12 |
|
T104 |
12 |