Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1917

1

T5

18

T1

1

T3

18

auto[1]

629

1

T1

14

T3

2

T8

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2029

1

T5

5

T1

13

T3

11

auto[1]

517

1

T5

13

T1

2

T3

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1907

1

T5

13

T1

13

T3

20

auto[1]

639

1

T5

5

T1

2

T9

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1989

1

T5

18

T1

14

T3

7

auto[1]

557

1

T1

1

T3

13

T9

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2377

1

T5

18

T1

15

T3

20

auto[1]

169

1

T29

1

T54

7

T52

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2342

1

T5

18

T1

15

T3

20

auto[1]

204

1

T52

1

T85

8

T87

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2322

1

T5

18

T1

15

T3

20

auto[1]

224

1

T11

1

T54

15

T52

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2310

1

T5

18

T1

15

T3

20

auto[1]

236

1

T54

3

T52

2

T86

33

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2334

1

T5

18

T1

15

T3

20

auto[1]

212

1

T11

1

T29

1

T54

18

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1985

1

T5

18

T1

14

T3

11

auto[1]

561

1

T1

1

T3

9

T10

5

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	879	1			T5	18		T1	15		T3	20
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	38	1			T132	7		T358	7		T367	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	64	1			T11	1		T287	13		T120	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	26	1			T29	1		T368	11		T369	9
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	71	1			T52	2		T86	14		T87	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	13	1			T370	3		T352	3		T371	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	18	1			T54	1		T86	2		T356	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T368	6		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	73	1			T11	1		T52	1		T283	9
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	14	1			T283	3		T372	6		T373	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	21	1			T54	4		T85	1		T134	8
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T54	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	21	1			T281	3		T231	5		T359	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	6	1			T281	2		T231	1		T120	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	37	1			T85	1		T281	5		T356	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	18	1			T52	1		T368	11		T359	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	10	1			T87	2		T374	3		T375	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T376	6		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	30	1			T353	1		T368	6		T377	8
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T378	3		T286	2		T372	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	7	1			T379	4		T351	3		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T121	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	25	1			T85	1		T281	3		T353	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	5	1			T377	2		T372	1		T376	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T132	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T380	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T286	1		T381	5		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T382	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

133

1

T1

13

T8

2

T223

15

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

110

1

T52

1

T86

7

T281

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T37

5

T52

2

T231

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

121

1

T3

11

T12

10

T54

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

43

1

T12

5

T164

5

T85

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T10

4

T127

3

T164

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T37

3

T300

3

T349

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

140

1

T5

5

T10

11

T307

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

77

1

T11

1

T37

14

T87

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T70

1

T192

6

T308

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T304

2

T291

4

T205

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T37

4

T369

9

T358

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

40

1

T37

5

T85

1

T307

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T299

5

T346

4

T202

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T349

2

T142

2

T383

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

102

1

T5

13

T54

4

T303

13

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T86

2

T299

4

T356

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T3

7

T281

5

T231

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T127

1

T37

1

T231

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T70

4

T29

1

T384

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T223

10

T85

1

T304

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T11

1

T304

2

T229

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T3

2

T52

1

T385

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T10

7

T303

9

T86

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T9

3

T36

1

T54

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

10

1

T1

1

T294

1

T345

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T303

2

T304

1

T93

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T384

4

T300

2

T205

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T1

1

T9

2

T303

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T10

1

T345

1

T350

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T140

2

T142

1

T159

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded