Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1220

1

T5

7

T81

11

T8

10

auto[1]

1180

1

T5

13

T81

9

T8

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

573

1

T5

4

T81

3

T8

3

from_0to1

578

1

T5

4

T81

4

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1217

1

T5

15

T81

9

T8

12

auto[1]

1183

1

T5

5

T81

11

T8

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1191

1

T5

13

T81

14

T8

11

auto[1]

1209

1

T5

7

T81

6

T8

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T81

1

T8

1

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T5

1

T83

1

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T83

2

T35

2

T165

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T5

1

T83

1

T35

2

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T35

1

T41

1

T178

2

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T8

1

T83

2

T40

1

auto[0]

from_0to1

auto[1]

auto[0]

83

1

T81

1

T8

1

T83

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T5

1

T81

1

T83

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T5

1

T178

1

T165

2

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T84

4

T251

1

T165

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T5

1

T81

1

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T81

1

T8

1

T84

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T5

2

T81

1

T8

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T5

1

T8

1

T83

2

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T35

2

T41

1

T178

1

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T81

1

T84

1

T35

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1220

1

T5

9

T81

12

T8

9

auto[1]

1180

1

T5

11

T81

8

T8

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

578

1

T5

3

T81

5

T8

4

from_0to1

580

1

T5

4

T81

5

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T5

9

T81

12

T8

8

auto[1]

1237

1

T5

11

T81

8

T8

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1214

1

T5

5

T81

12

T8

14

auto[1]

1186

1

T5

15

T81

8

T8

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T81

2

T83

2

T35

4

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T81

1

T8

1

T84

3

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T5

1

T84

2

T35

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T8

1

T35

2

T328

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T81

1

T83

1

T35

3

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T83

2

T35

2

T178

1

auto[0]

from_0to1

auto[1]

auto[0]

87

1

T81

1

T83

1

T84

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T5

1

T8

1

T35

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T81

1

T83

1

T35

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T5

1

T83

1

T35

2

auto[1]

from_1to0

auto[1]

auto[0]

84

1

T81

1

T8

2

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T5

1

T83

1

T41

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T5

1

T81

2

T41

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T5

2

T83

1

T84

1

auto[1]

from_0to1

auto[1]

auto[0]

81

1

T81

1

T8

2

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

80

1

T8

1

T35

1

T178

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1165

1

T5

11

T81

9

T8

12

auto[1]

1235

1

T5

9

T81

11

T8

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

575

1

T5

4

T81

7

T8

5

from_0to1

580

1

T5

4

T81

8

T8

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1227

1

T5

12

T81

15

T8

9

auto[1]

1173

1

T5

8

T81

5

T8

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T5

10

T81

13

T8

8

auto[1]

1242

1

T5

10

T81

7

T8

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T5

1

T81

3

T35

1

auto[0]

from_1to0

auto[0]

auto[1]

84

1

T5

1

T81

1

T8

1

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T84

1

T35

2

T58

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T5

1

T8

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T5

1

T84

1

T251

1

auto[0]

from_0to1

auto[0]

auto[1]

83

1

T81

1

T8

2

T35

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T81

1

T8

1

T84

1

auto[0]

from_0to1

auto[1]

auto[1]

80

1

T81

1

T83

2

T84

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T81

1

T83

2

T84

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T5

1

T81

1

T8

2

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T81

1

T8

1

T84

4

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T35

1

T41

3

T178

2

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T5

1

T81

3

T35

4

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T8

1

T83

1

T35

2

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T5

1

T81

1

T8

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T5

1

T81

1

T84

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1206

1

T5

8

T81

12

T8

11

auto[1]

1194

1

T5

12

T81

8

T8

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

576

1

T5

5

T81

5

T8

4

from_0to1

584

1

T5

5

T81

5

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1222

1

T5

11

T81

9

T8

7

auto[1]

1178

1

T5

9

T81

11

T8

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1198

1

T5

9

T81

11

T8

13

auto[1]

1202

1

T5

11

T81

9

T8

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T5

1

T84

1

T35

2

auto[0]

from_1to0

auto[0]

auto[1]

82

1

T5

2

T84

1

T35

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T81

1

T83

1

T84

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T81

1

T8

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T5

1

T35

2

T178

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T81

2

T178

1

T165

2

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T8

1

T83

1

T35

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T5

1

T81

3

T8

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T5

1

T81

3

T8

2

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T8

1

T35

2

T41

2

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T35

1

T41

1

T178

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T5

1

T83

1

T58

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T5

1

T8

1

T84

1

auto[1]

from_0to1

auto[0]

auto[1]

93

1

T5

1

T8

1

T84

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T5

1

T83

1

T84

2

auto[1]

from_0to1

auto[1]

auto[1]

88

1

T83

1

T41

1

T58

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T5

13

T81

13

T8

7

auto[1]

1221

1

T5

7

T81

7

T8

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

549

1

T5

6

T81

5

T8

5

from_0to1

546

1

T5

5

T81

6

T8

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1194

1

T5

8

T81

11

T8

12

auto[1]

1206

1

T5

12

T81

9

T8

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1182

1

T5

12

T81

10

T8

9

auto[1]

1218

1

T5

8

T81

10

T8

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T5

1

T81

1

T8

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T8

1

T83

2

T84

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T5

2

T83

1

T84

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T5

1

T81

1

T8

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T35

3

T40

2

T101

3

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T5

2

T81

2

T35

1

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T81

3

T83

3

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T5

1

T84

1

T35

3

auto[1]

from_1to0

auto[0]

auto[0]

82

1

T5

1

T8

1

T83

3

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T81

2

T84

1

T41

2

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T5

1

T84

1

T58

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T81

1

T8

1

T35

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T5

1

T8

3

T83

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T8

1

T83

1

T35

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T83

1

T84

1

T35

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T5

1

T81

1

T8

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T5

7

T81

10

T8

10

auto[1]

1200

1

T5

13

T81

10

T8

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

579

1

T5

6

T81

5

T8

6

from_0to1

580

1

T5

6

T81

6

T8

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203

1

T5

9

T81

7

T8

10

auto[1]

1197

1

T5

11

T81

13

T8

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T5

13

T81

14

T8

7

auto[1]

1228

1

T5

7

T81

6

T8

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T81

1

T8

2

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T81

1

T83

3

T35

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T5

3

T81

1

T8

1

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T8

1

T84

1

T251

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T5

1

T84

1

T35

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T8

1

T83

2

T35

2

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T5

2

T81

1

T8

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T5

1

T81

1

T8

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T5

2

T81

2

T83

2

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T8

2

T83

1

T84

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T35

1

T58

2

T165

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T5

1

T41

2

T178

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T5

1

T81

1

T83

2

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T8

1

T83

1

T35

2

auto[1]

from_0to1

auto[1]

auto[0]

81

1

T5

1

T81

3

T83

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T8

1

T83

1

T35

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T5

11

T81

11

T8

10

auto[1]

1237

1

T5

9

T81

9

T8

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

576

1

T5

3

T81

5

T8

4

from_0to1

567

1

T5

4

T81

5

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1266

1

T5

9

T81

15

T8

9

auto[1]

1134

1

T5

11

T81

5

T8

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1213

1

T5

10

T81

14

T8

9

auto[1]

1187

1

T5

10

T81

6

T8

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T81

1

T83

1

T84

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T81

1

T8

1

T84

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T5

1

T8

1

T84

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T83

2

T35

3

T41

2

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T5

1

T81

1

T8

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T81

2

T83

3

T35

2

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T5

2

T81

1

T8

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T83

1

T58

1

T251

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T81

2

T8

1

T35

1

auto[1]

from_1to0

auto[0]

auto[1]

85

1

T178

1

T58

1

T251

3

auto[1]

from_1to0

auto[1]

auto[0]

82

1

T5

2

T81

1

T83

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T8

1

T83

1

T84

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T8

1

T83

2

T84

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T5

1

T83

1

T35

2

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T81

1

T251

1

T40

3

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T8

1

T84

2

T35

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1217

1

T5

13

T81

8

T8

10

auto[1]

1183

1

T5

7

T81

12

T8

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

564

1

T5

5

T81

2

T8

3

from_0to1

568

1

T5

5

T81

3

T8

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1195

1

T5

7

T81

9

T8

8

auto[1]

1205

1

T5

13

T81

11

T8

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T5

12

T81

10

T8

11

auto[1]

1221

1

T5

8

T81

10

T8

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T58

1

T165

1

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T5

1

T83

1

T35

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T5

2

T8

1

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T5

1

T81

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T35

2

T41

1

T251

1

auto[0]

from_0to1

auto[0]

auto[1]

83

1

T5

1

T81

2

T8

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T8

1

T83

1

T178

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T35

1

T178

1

T165

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T8

1

T83

1

T35

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T81

1

T83

1

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T5

1

T83

2

T84

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T8

1

T35

3

T41

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T81

1

T84

3

T41

2

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T5

1

T35

1

T41

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T5

2

T83

2

T35

1

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T5

1

T83

2

T35

2