Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119472

1

T4

6

T5

411

T1

246

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136563	1			T4	7		T5	470		T1	410
values[0x0]	66731	1			T5	192		T1	37		T13	2
values[0x1]	67513	1			T5	179		T1	33		T13	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122954	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147853

1

T4

6

T5

487

T1

285

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	747	1			T3	5		T19	1		T73	1
valid_sources[0x01]	950	1			T5	35		T1	1		T3	8
valid_sources[0x02]	829	1			T1	1		T13	1		T9	2
valid_sources[0x03]	1014	1			T3	1		T19	1		T28	1
valid_sources[0x04]	1604	1			T1	2		T6	2		T81	1
valid_sources[0x05]	904	1			T3	7		T9	4		T28	1
valid_sources[0x06]	1181	1			T19	1		T8	255		T9	3
valid_sources[0x07]	919	1			T1	1		T3	4		T8	20
valid_sources[0x08]	872	1			T5	41		T3	6		T28	2
valid_sources[0x09]	823	1			T1	1		T3	3		T28	3
valid_sources[0x0a]	1611	1			T1	3		T3	2		T108	2
valid_sources[0x0b]	1576	1			T5	5		T1	1		T17	8
valid_sources[0x0c]	1105	1			T1	2		T28	8		T64	1
valid_sources[0x0d]	2048	1			T1	1		T3	7		T83	1
valid_sources[0x0e]	915	1			T13	1		T3	2		T83	3
valid_sources[0x0f]	913	1			T1	5		T3	2		T9	1
valid_sources[0x10]	1323	1			T1	2		T3	1		T81	3
valid_sources[0x11]	975	1			T5	97		T1	1		T9	2
valid_sources[0x12]	1061	1			T1	1		T27	12		T81	2
valid_sources[0x13]	1092	1			T1	1		T2	2		T108	1
valid_sources[0x14]	854	1			T1	6		T3	1		T78	2
valid_sources[0x15]	1221	1			T3	5		T25	1		T28	2
valid_sources[0x16]	895	1			T3	7		T143	1		T83	1
valid_sources[0x17]	835	1			T1	1		T3	3		T19	3
valid_sources[0x18]	989	1			T1	2		T3	2		T83	2
valid_sources[0x19]	907	1			T1	2		T17	2		T25	1
valid_sources[0x1a]	994	1			T1	1		T3	4		T28	1
valid_sources[0x1b]	943	1			T1	5		T78	1		T9	2
valid_sources[0x1c]	968	1			T1	1		T28	2		T64	1
valid_sources[0x1d]	897	1			T5	39		T16	1		T3	14
valid_sources[0x1e]	832	1			T1	1		T3	7		T81	1
valid_sources[0x1f]	1089	1			T1	4		T13	1		T9	1
valid_sources[0x20]	983	1			T1	3		T15	32		T17	1
valid_sources[0x21]	872	1			T18	2		T9	1		T28	4
valid_sources[0x22]	1094	1			T1	2		T18	1		T6	2
valid_sources[0x23]	1054	1			T1	1		T28	1		T12	7
valid_sources[0x24]	1482	1			T2	3		T28	2		T65	1
valid_sources[0x25]	798	1			T1	3		T81	3		T9	2
valid_sources[0x26]	1050	1			T1	3		T3	3		T73	1
valid_sources[0x27]	928	1			T1	1		T17	2		T81	1
valid_sources[0x28]	784	1			T1	2		T3	5		T12	2
valid_sources[0x29]	1007	1			T3	3		T9	8		T28	1
valid_sources[0x2a]	1120	1			T9	4		T28	2		T12	6
valid_sources[0x2b]	904	1			T28	1		T64	1		T12	1
valid_sources[0x2c]	883	1			T1	3		T3	3		T27	18
valid_sources[0x2d]	822	1			T1	2		T3	14		T28	6
valid_sources[0x2e]	918	1			T1	6		T18	3		T9	12
valid_sources[0x2f]	854	1			T1	2		T9	2		T83	1
valid_sources[0x30]	840	1			T1	4		T3	3		T81	8
valid_sources[0x31]	953	1			T1	5		T3	4		T19	2
valid_sources[0x32]	971	1			T83	1		T12	1		T397	1
valid_sources[0x33]	861	1			T3	8		T28	3		T397	1
valid_sources[0x34]	823	1			T1	7		T3	5		T28	5
valid_sources[0x35]	1217	1			T1	3		T3	1		T34	12
valid_sources[0x36]	1256	1			T13	2		T3	2		T28	3
valid_sources[0x37]	1067	1			T3	4		T25	4		T9	1
valid_sources[0x38]	876	1			T16	1		T17	1		T9	2
valid_sources[0x39]	1942	1			T1	3		T25	4		T81	1
valid_sources[0x3a]	826	1			T1	5		T3	2		T19	1
valid_sources[0x3b]	811	1			T1	3		T6	1		T9	1
valid_sources[0x3c]	1650	1			T3	8		T9	5		T28	1
valid_sources[0x3d]	1185	1			T1	1		T2	7		T3	20
valid_sources[0x3e]	992	1			T1	1		T3	5		T9	6
valid_sources[0x3f]	828	1			T1	2		T3	3		T9	9
valid_sources[0x40]	984	1			T1	8		T3	4		T8	6
valid_sources[0x41]	1003	1			T1	1		T3	7		T9	2
valid_sources[0x42]	852	1			T1	1		T13	1		T3	2
valid_sources[0x43]	2120	1			T1	1		T3	2		T19	1
valid_sources[0x44]	1891	1			T1	3		T3	2		T81	9
valid_sources[0x45]	854	1			T1	2		T3	5		T6	2
valid_sources[0x46]	1016	1			T5	26		T1	2		T3	3
valid_sources[0x47]	854	1			T2	2		T3	4		T83	1
valid_sources[0x48]	1003	1			T5	74		T1	5		T28	3
valid_sources[0x49]	944	1			T3	3		T27	5		T28	2
valid_sources[0x4a]	1548	1			T1	1		T3	2		T81	4
valid_sources[0x4b]	1690	1			T1	1		T3	9		T9	4
valid_sources[0x4c]	1018	1			T5	154		T3	6		T9	1
valid_sources[0x4d]	1393	1			T9	19		T83	2		T28	2
valid_sources[0x4e]	1400	1			T1	1		T3	1		T26	44
valid_sources[0x4f]	1926	1			T1	2		T13	1		T3	11
valid_sources[0x50]	882	1			T1	1		T9	2		T83	1
valid_sources[0x51]	960	1			T1	1		T9	1		T28	3
valid_sources[0x52]	1110	1			T1	10		T9	11		T28	1
valid_sources[0x53]	931	1			T3	5		T8	3		T9	4
valid_sources[0x54]	864	1			T1	1		T3	3		T81	7
valid_sources[0x55]	918	1			T3	1		T19	4		T9	5
valid_sources[0x56]	1956	1			T1	3		T9	19		T28	2
valid_sources[0x57]	1698	1			T5	1		T1	5		T3	2
valid_sources[0x58]	884	1			T1	8		T3	8		T81	4
valid_sources[0x59]	1918	1			T1	5		T3	6		T78	1
valid_sources[0x5a]	1031	1			T1	1		T28	1		T12	1
valid_sources[0x5b]	911	1			T28	1		T66	4		T12	3
valid_sources[0x5c]	1482	1			T1	2		T78	2		T10	627
valid_sources[0x5d]	891	1			T1	3		T3	9		T9	1
valid_sources[0x5e]	891	1			T1	1		T9	10		T28	2
valid_sources[0x5f]	840	1			T1	4		T2	1		T3	2
valid_sources[0x60]	1036	1			T1	3		T3	2		T27	10
valid_sources[0x61]	914	1			T1	1		T9	2		T12	2
valid_sources[0x62]	944	1			T1	7		T3	4		T9	5
valid_sources[0x63]	952	1			T81	1		T28	3		T64	1
valid_sources[0x64]	1006	1			T81	1		T78	2		T28	4
valid_sources[0x65]	896	1			T1	3		T3	8		T9	1
valid_sources[0x66]	1108	1			T1	1		T3	2		T81	7
valid_sources[0x67]	970	1			T1	1		T19	4		T9	12
valid_sources[0x68]	908	1			T1	2		T3	5		T8	1
valid_sources[0x69]	949	1			T1	5		T3	10		T9	4
valid_sources[0x6a]	1264	1			T3	10		T81	2		T9	4
valid_sources[0x6b]	1179	1			T1	4		T3	6		T6	2
valid_sources[0x6c]	946	1			T5	58		T1	2		T25	3
valid_sources[0x6d]	1231	1			T1	7		T3	8		T19	1
valid_sources[0x6e]	971	1			T83	2		T66	1		T12	1
valid_sources[0x6f]	819	1			T1	2		T19	12		T83	1
valid_sources[0x70]	1180	1			T1	5		T17	2		T3	1
valid_sources[0x71]	1418	1			T1	2		T3	3		T83	2
valid_sources[0x72]	956	1			T83	2		T28	1		T64	1
valid_sources[0x73]	1103	1			T1	1		T83	1		T28	3
valid_sources[0x74]	922	1			T1	6		T13	1		T3	2
valid_sources[0x75]	917	1			T5	4		T19	1		T78	2
valid_sources[0x76]	829	1			T1	4		T3	4		T28	2
valid_sources[0x77]	917	1			T1	2		T3	5		T81	3
valid_sources[0x78]	2048	1			T5	13		T3	1		T27	1
valid_sources[0x79]	862	1			T64	2		T12	1		T84	1
valid_sources[0x7a]	926	1			T3	2		T8	10		T83	2
valid_sources[0x7b]	1627	1			T1	2		T3	2		T81	3
valid_sources[0x7c]	1705	1			T3	1		T28	3		T12	3
valid_sources[0x7d]	1112	1			T1	3		T3	8		T83	1
valid_sources[0x7e]	966	1			T1	3		T16	1		T3	4
valid_sources[0x7f]	961	1			T1	1		T3	3		T19	1
valid_sources[0x80]	964	1			T1	1		T3	3		T19	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63875

1

T4

6

T5

245

T1

223

values[0x0]

all_enables

biggest_size

32532

1

T5

103

T1

14

T13

2

values[0x1]

all_enables

biggest_size

23065

1

T5

63

T1

9

T13

1