Unified Coverage Report :: Module :: sysrst_ctrl_keyintr

Module : sysrst_ctrl_keyintr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr	100.00	100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_keyintr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.94	99.07	92.18		97.62	98.57	97.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	96.76	100.00	90.48		100.00	100.00	93.33
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	96.85	100.00	90.48		100.00	100.00	93.75
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	96.85	100.00	90.48		100.00	100.00	93.75
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	95.41	97.83	90.48		100.00	95.00	93.75
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_keyintr

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	48	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
39	1	1
48	1	1