Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T11,T29
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T11,T29
1	0	Covered	T11,T29,T54
1	1	Covered	T28,T11,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T11,T29
0	1	Covered	T28,T59,T54
1	0	Covered	T29,T54,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T52,T53
0	1	Covered	T11,T52,T53
1	0	Covered	T116

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T52,T53
1	-	Covered	T11,T52,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T11,T29
DetectSt	168	Covered	T28,T11,T29
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T52,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T11,T29
DebounceSt->IdleSt	163	Covered	T279,T69,T280
DetectSt->IdleSt	186	Covered	T28,T29,T59
DetectSt->StableSt	191	Covered	T11,T52,T53
IdleSt->DebounceSt	148	Covered	T28,T11,T29
StableSt->IdleSt	206	Covered	T11,T52,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T28,T11,T29
0	1	Covered	T28,T11,T29
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T11,T29
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T28,T11,T29
IdleSt	0	-	-	-	-	-	-	Covered	T28,T11,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T11,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T279,T69,T280
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T11,T29
DetectSt	-	-	-	-	1	-	-	Covered	T28,T29,T59
DetectSt	-	-	-	-	0	1	-	Covered	T11,T52,T53
DetectSt	-	-	-	-	0	0	-	Covered	T28,T11,T29
StableSt	-	-	-	-	-	-	1	Covered	T11,T52,T53
StableSt	-	-	-	-	-	-	0	Covered	T11,T52,T53
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	2994	0	0
CntIncr_A	8955184	102362	0	0
CntNoWrap_A	8955184	8303987	0	0
DetectStDropOut_A	8955184	527	0	0
DetectedOut_A	8955184	63628	0	0
DetectedPulseOut_A	8955184	751	0	0
DisabledIdleSt_A	8955184	7887113	0	0
DisabledNoDetection_A	8955184	7889287	0	0
EnterDebounceSt_A	8955184	1518	0	0
EnterDetectSt_A	8955184	1477	0	0
EnterStableSt_A	8955184	751	0	0
PulseIsPulse_A	8955184	751	0	0
StayInStableSt	8955184	62765	0	0
gen_high_event_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	638	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2994	0	0
T11	12088	40	0	0
T12	25979	0	0	0
T28	5016	56	0	0
T29	0	28	0	0
T52	0	28	0	0
T53	0	50	0	0
T54	0	32	0	0
T59	0	22	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	20	0	0
T86	0	48	0	0
T87	0	36	0	0
T88	432	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	102362	0	0
T11	12088	1400	0	0
T12	25979	0	0	0
T28	5016	1348	0	0
T29	0	902	0	0
T52	0	938	0	0
T53	0	1575	0	0
T54	0	1679	0	0
T59	0	512	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	659	0	0
T86	0	1872	0	0
T87	0	648	0	0
T88	432	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8303987	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	527	0	0
T11	12088	0	0	0
T12	25979	0	0	0
T28	5016	28	0	0
T54	0	9	0	0
T59	0	11	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	1	0	0
T88	432	0	0	0
T130	0	6	0	0
T131	0	2	0	0
T132	0	17	0	0
T133	0	30	0	0
T134	0	6	0	0
T237	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	63628	0	0
T11	12088	3593	0	0
T12	25979	0	0	0
T52	0	773	0	0
T53	0	627	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T86	0	3559	0	0
T87	0	735	0	0
T88	432	0	0	0
T117	0	497	0	0
T231	0	775	0	0
T281	0	793	0	0
T282	0	372	0	0
T283	0	1378	0	0
T284	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	751	0	0
T11	12088	20	0	0
T12	25979	0	0	0
T52	0	14	0	0
T53	0	25	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T86	0	24	0	0
T87	0	18	0	0
T88	432	0	0	0
T117	0	7	0	0
T231	0	7	0	0
T281	0	11	0	0
T282	0	14	0	0
T283	0	26	0	0
T284	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7887113	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7889287	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1518	0	0
T11	12088	20	0	0
T12	25979	0	0	0
T28	5016	28	0	0
T29	0	14	0	0
T52	0	14	0	0
T53	0	25	0	0
T54	0	16	0	0
T59	0	11	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	10	0	0
T86	0	24	0	0
T87	0	18	0	0
T88	432	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1477	0	0
T11	12088	20	0	0
T12	25979	0	0	0
T28	5016	28	0	0
T29	0	14	0	0
T52	0	14	0	0
T53	0	25	0	0
T54	0	16	0	0
T59	0	11	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	10	0	0
T86	0	24	0	0
T87	0	18	0	0
T88	432	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	751	0	0
T11	12088	20	0	0
T12	25979	0	0	0
T52	0	14	0	0
T53	0	25	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T86	0	24	0	0
T87	0	18	0	0
T88	432	0	0	0
T117	0	7	0	0
T231	0	7	0	0
T281	0	11	0	0
T282	0	14	0	0
T283	0	26	0	0
T284	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	751	0	0
T11	12088	20	0	0
T12	25979	0	0	0
T52	0	14	0	0
T53	0	25	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T86	0	24	0	0
T87	0	18	0	0
T88	432	0	0	0
T117	0	7	0	0
T231	0	7	0	0
T281	0	11	0	0
T282	0	14	0	0
T283	0	26	0	0
T284	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	62765	0	0
T11	12088	3572	0	0
T12	25979	0	0	0
T52	0	758	0	0
T53	0	602	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T86	0	3528	0	0
T87	0	715	0	0
T88	432	0	0	0
T117	0	490	0	0
T231	0	768	0	0
T281	0	779	0	0
T282	0	358	0	0
T283	0	1347	0	0
T284	405	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	638	0	0
T11	12088	19	0	0
T12	25979	0	0	0
T52	0	13	0	0
T53	0	25	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T86	0	17	0	0
T87	0	16	0	0
T88	432	0	0	0
T117	0	7	0	0
T231	0	7	0	0
T281	0	8	0	0
T282	0	14	0	0
T283	0	21	0	0
T284	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T5,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T9,T12,T136
1	0	Covered	T69,T116

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
1	0	Covered	T69,T285,T286

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T1,T3
1	-	Covered	T5,T1,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T3
DetectSt	168	Covered	T5,T1,T3
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T5,T1,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T3
DebounceSt->IdleSt	163	Covered	T5,T3,T9
DetectSt->IdleSt	186	Covered	T9,T12,T69
DetectSt->StableSt	191	Covered	T5,T1,T3
IdleSt->DebounceSt	148	Covered	T5,T1,T3
StableSt->IdleSt	206	Covered	T5,T1,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T3
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T3,T9
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	1	-	-	Covered	T9,T12,T69
DetectSt	-	-	-	-	0	1	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	1	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	0	Covered	T5,T1,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	808	0	0
CntIncr_A	8955184	38555	0	0
CntNoWrap_A	8955184	8306173	0	0
DetectStDropOut_A	8955184	43	0	0
DetectedOut_A	8955184	13301	0	0
DetectedPulseOut_A	8955184	322	0	0
DisabledIdleSt_A	8955184	7960887	0	0
DisabledNoDetection_A	8955184	7962520	0	0
EnterDebounceSt_A	8955184	439	0	0
EnterDetectSt_A	8955184	369	0	0
EnterStableSt_A	8955184	322	0	0
PulseIsPulse_A	8955184	322	0	0
StayInStableSt	8955184	12937	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	275	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	808	0	0
T1	8953	2	0	0
T2	788	0	0	0
T3	38319	15	0	0
T5	38517	28	0	0
T8	0	4	0	0
T9	0	7	0	0
T10	0	2	0	0
T12	0	24	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	2	0	0
T41	0	2	0	0
T127	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	38555	0	0
T1	8953	145	0	0
T2	788	0	0	0
T3	38319	802	0	0
T5	38517	667	0	0
T8	0	170	0	0
T9	0	308	0	0
T10	0	67	0	0
T12	0	1465	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	25	0	0
T41	0	25	0	0
T127	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306173	0	0
T1	8953	8543	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	35977	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	43	0	0
T9	12144	3	0	0
T10	32256	0	0	0
T11	12088	0	0	0
T12	0	12	0	0
T28	5016	0	0	0
T71	319237	0	0	0
T72	750	0	0	0
T83	502	0	0	0
T108	404	0	0	0
T110	0	1	0	0
T136	0	5	0	0
T137	0	4	0	0
T138	0	5	0	0
T139	0	2	0	0
T140	0	3	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	409	0	0	0
T144	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	13301	0	0
T1	8953	8	0	0
T2	788	0	0	0
T3	38319	33	0	0
T5	38517	583	0	0
T8	0	65	0	0
T10	0	65	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	3	0	0
T37	0	258	0	0
T41	0	3	0	0
T58	0	3	0	0
T127	0	16	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	322	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	7	0	0
T5	38517	13	0	0
T8	0	2	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	1	0	0
T37	0	5	0	0
T41	0	1	0	0
T58	0	1	0	0
T127	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7960887	0	0
T1	8953	4029	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	32835	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7962520	0	0
T1	8953	4029	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	32838	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	439	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	8	0	0
T5	38517	15	0	0
T8	0	2	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	0	12	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	1	0	0
T41	0	1	0	0
T127	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	369	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	7	0	0
T5	38517	13	0	0
T8	0	2	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	12	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	1	0	0
T41	0	1	0	0
T127	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	322	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	7	0	0
T5	38517	13	0	0
T8	0	2	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	1	0	0
T37	0	5	0	0
T41	0	1	0	0
T58	0	1	0	0
T127	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	322	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	7	0	0
T5	38517	13	0	0
T8	0	2	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	1	0	0
T37	0	5	0	0
T41	0	1	0	0
T58	0	1	0	0
T127	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	12937	0	0
T1	8953	7	0	0
T2	788	0	0	0
T3	38319	26	0	0
T5	38517	569	0	0
T8	0	63	0	0
T10	0	64	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	2	0	0
T37	0	253	0	0
T41	0	2	0	0
T58	0	2	0	0
T127	0	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	275	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	7	0	0
T5	38517	11	0	0
T8	0	2	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T35	0	1	0	0
T37	0	5	0	0
T41	0	1	0	0
T58	0	1	0	0
T127	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T11,T29
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T11,T29
1	0	Covered	T11,T29,T54
1	1	Covered	T28,T11,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T11,T29
0	1	Covered	T28,T29,T59
1	0	Covered	T29,T87,T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T54,T52
0	1	Covered	T11,T54,T52
1	0	Covered	T122,T116

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T54,T52
1	-	Covered	T11,T54,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T11,T29
DetectSt	168	Covered	T28,T11,T29
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T54,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T11,T29
DebounceSt->IdleSt	163	Covered	T279,T69,T280
DetectSt->IdleSt	186	Covered	T28,T29,T59
DetectSt->StableSt	191	Covered	T11,T54,T52
IdleSt->DebounceSt	148	Covered	T28,T11,T29
StableSt->IdleSt	206	Covered	T11,T54,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T28,T11,T29
0	1	Covered	T28,T11,T29
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T11,T29
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T28,T11,T29
IdleSt	0	-	-	-	-	-	-	Covered	T28,T11,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T11,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T279,T69,T280
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T11,T29
DetectSt	-	-	-	-	1	-	-	Covered	T28,T29,T59
DetectSt	-	-	-	-	0	1	-	Covered	T11,T54,T52
DetectSt	-	-	-	-	0	0	-	Covered	T28,T11,T29
StableSt	-	-	-	-	-	-	1	Covered	T11,T54,T52
StableSt	-	-	-	-	-	-	0	Covered	T11,T54,T52
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	3004	0	0
CntIncr_A	8955184	100648	0	0
CntNoWrap_A	8955184	8303977	0	0
DetectStDropOut_A	8955184	412	0	0
DetectedOut_A	8955184	79058	0	0
DetectedPulseOut_A	8955184	908	0	0
DisabledIdleSt_A	8955184	7874590	0	0
DisabledNoDetection_A	8955184	7876763	0	0
EnterDebounceSt_A	8955184	1520	0	0
EnterDetectSt_A	8955184	1484	0	0
EnterStableSt_A	8955184	908	0	0
PulseIsPulse_A	8955184	908	0	0
StayInStableSt	8955184	78037	0	0
gen_high_event_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	789	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	3004	0	0
T11	12088	44	0	0
T12	25979	0	0	0
T28	5016	48	0	0
T29	0	58	0	0
T52	0	58	0	0
T53	0	46	0	0
T54	0	20	0	0
T59	0	18	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	42	0	0
T86	0	18	0	0
T87	0	72	0	0
T88	432	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	100648	0	0
T11	12088	1518	0	0
T12	25979	0	0	0
T28	5016	1152	0	0
T29	0	1867	0	0
T52	0	2059	0	0
T53	0	1495	0	0
T54	0	540	0	0
T59	0	418	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	903	0	0
T86	0	639	0	0
T87	0	1471	0	0
T88	432	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8303977	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	412	0	0
T11	12088	0	0	0
T12	25979	0	0	0
T28	5016	24	0	0
T29	0	15	0	0
T59	0	9	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T87	0	8	0	0
T88	432	0	0	0
T117	0	7	0	0
T130	0	11	0	0
T133	0	13	0	0
T237	0	21	0	0
T287	0	10	0	0
T288	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	79058	0	0
T11	12088	1208	0	0
T12	25979	0	0	0
T52	0	1080	0	0
T53	0	1927	0	0
T54	0	1562	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	1903	0	0
T86	0	1819	0	0
T88	432	0	0	0
T131	0	1687	0	0
T132	0	2572	0	0
T281	0	1744	0	0
T282	0	2330	0	0
T284	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	908	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T52	0	29	0	0
T53	0	23	0	0
T54	0	10	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	21	0	0
T86	0	9	0	0
T88	432	0	0	0
T131	0	32	0	0
T132	0	20	0	0
T281	0	19	0	0
T282	0	26	0	0
T284	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7874590	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7876763	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1520	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T28	5016	24	0	0
T29	0	29	0	0
T52	0	29	0	0
T53	0	23	0	0
T54	0	10	0	0
T59	0	9	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	21	0	0
T86	0	9	0	0
T87	0	36	0	0
T88	432	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1484	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T28	5016	24	0	0
T29	0	29	0	0
T52	0	29	0	0
T53	0	23	0	0
T54	0	10	0	0
T59	0	9	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	21	0	0
T86	0	9	0	0
T87	0	36	0	0
T88	432	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	908	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T52	0	29	0	0
T53	0	23	0	0
T54	0	10	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	21	0	0
T86	0	9	0	0
T88	432	0	0	0
T131	0	32	0	0
T132	0	20	0	0
T281	0	19	0	0
T282	0	26	0	0
T284	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	908	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T52	0	29	0	0
T53	0	23	0	0
T54	0	10	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	21	0	0
T86	0	9	0	0
T88	432	0	0	0
T131	0	32	0	0
T132	0	20	0	0
T281	0	19	0	0
T282	0	26	0	0
T284	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	78037	0	0
T11	12088	1185	0	0
T12	25979	0	0	0
T52	0	1051	0	0
T53	0	1904	0	0
T54	0	1548	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	1881	0	0
T86	0	1808	0	0
T88	432	0	0	0
T131	0	1655	0	0
T132	0	2545	0	0
T281	0	1722	0	0
T282	0	2304	0	0
T284	405	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	789	0	0
T11	12088	21	0	0
T12	25979	0	0	0
T52	0	29	0	0
T53	0	23	0	0
T54	0	6	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	20	0	0
T86	0	7	0	0
T88	432	0	0	0
T131	0	32	0	0
T132	0	13	0	0
T281	0	16	0	0
T282	0	26	0	0
T284	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T5,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
1	0	Covered	T69,T116

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T11
0	1	Covered	T9,T10,T11
1	0	Covered	T118,T289,T285

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T11
1	-	Covered	T9,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T3
DetectSt	168	Covered	T5,T1,T3
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T3
DebounceSt->IdleSt	163	Covered	T1,T9,T10
DetectSt->IdleSt	186	Covered	T5,T1,T3
DetectSt->StableSt	191	Covered	T9,T10,T11
IdleSt->DebounceSt	148	Covered	T5,T1,T3
StableSt->IdleSt	206	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T3
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T9,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	1	-	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	814	0	0
CntIncr_A	8955184	39944	0	0
CntNoWrap_A	8955184	8306167	0	0
DetectStDropOut_A	8955184	68	0	0
DetectedOut_A	8955184	14384	0	0
DetectedPulseOut_A	8955184	311	0	0
DisabledIdleSt_A	8955184	7949156	0	0
DisabledNoDetection_A	8955184	7950844	0	0
EnterDebounceSt_A	8955184	431	0	0
EnterDetectSt_A	8955184	384	0	0
EnterStableSt_A	8955184	311	0	0
PulseIsPulse_A	8955184	311	0	0
StayInStableSt	8955184	14026	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	258	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	814	0	0
T1	8953	10	0	0
T2	788	0	0	0
T3	38319	10	0	0
T5	38517	7	0	0
T9	0	7	0	0
T10	0	23	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T36	0	2	0	0
T70	0	2	0	0
T127	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	39944	0	0
T1	8953	768	0	0
T2	788	0	0	0
T3	38319	561	0	0
T5	38517	377	0	0
T9	0	189	0	0
T10	0	987	0	0
T11	0	44	0	0
T12	0	121	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T36	0	143	0	0
T70	0	165	0	0
T127	0	116	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306167	0	0
T1	8953	8535	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	35998	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	68	0	0
T1	8953	4	0	0
T2	788	0	0	0
T3	38319	5	0	0
T5	38517	3	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T94	0	3	0	0
T127	0	1	0	0
T205	0	3	0	0
T290	0	3	0	0
T291	0	2	0	0
T292	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	14384	0	0
T9	12144	119	0	0
T10	32256	528	0	0
T11	12088	259	0	0
T28	5016	0	0	0
T36	0	34	0	0
T37	0	278	0	0
T52	0	123	0	0
T54	0	276	0	0
T70	0	39	0	0
T71	319237	0	0	0
T72	750	0	0	0
T83	502	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T192	0	57	0	0
T223	0	176	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	311	0	0
T9	12144	3	0	0
T10	32256	11	0	0
T11	12088	1	0	0
T28	5016	0	0	0
T36	0	1	0	0
T37	0	9	0	0
T52	0	2	0	0
T54	0	4	0	0
T70	0	1	0	0
T71	319237	0	0	0
T72	750	0	0	0
T83	502	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T192	0	6	0	0
T223	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7949156	0	0
T1	8953	4029	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	32869	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7950844	0	0
T1	8953	4029	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	32873	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	431	0	0
T1	8953	6	0	0
T2	788	0	0	0
T3	38319	5	0	0
T5	38517	4	0	0
T9	0	4	0	0
T10	0	12	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T36	0	1	0	0
T70	0	1	0	0
T127	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	384	0	0
T1	8953	4	0	0
T2	788	0	0	0
T3	38319	5	0	0
T5	38517	4	0	0
T9	0	3	0	0
T10	0	11	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T36	0	1	0	0
T70	0	1	0	0
T127	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	311	0	0
T9	12144	3	0	0
T10	32256	11	0	0
T11	12088	1	0	0
T28	5016	0	0	0
T36	0	1	0	0
T37	0	9	0	0
T52	0	2	0	0
T54	0	4	0	0
T70	0	1	0	0
T71	319237	0	0	0
T72	750	0	0	0
T83	502	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T192	0	6	0	0
T223	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	311	0	0
T9	12144	3	0	0
T10	32256	11	0	0
T11	12088	1	0	0
T28	5016	0	0	0
T36	0	1	0	0
T37	0	9	0	0
T52	0	2	0	0
T54	0	4	0	0
T70	0	1	0	0
T71	319237	0	0	0
T72	750	0	0	0
T83	502	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T192	0	6	0	0
T223	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	14026	0	0
T9	12144	116	0	0
T10	32256	517	0	0
T11	12088	258	0	0
T28	5016	0	0	0
T36	0	33	0	0
T37	0	269	0	0
T52	0	121	0	0
T54	0	272	0	0
T70	0	38	0	0
T71	319237	0	0	0
T72	750	0	0	0
T83	502	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T192	0	51	0	0
T223	0	171	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	258	0	0
T9	12144	3	0	0
T10	32256	11	0	0
T11	12088	1	0	0
T28	5016	0	0	0
T36	0	1	0	0
T37	0	9	0	0
T52	0	2	0	0
T54	0	4	0	0
T70	0	1	0	0
T71	319237	0	0	0
T72	750	0	0	0
T83	502	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T192	0	6	0	0
T223	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T11,T29
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T11,T29
1	0	Covered	T11,T29,T54
1	1	Covered	T28,T11,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T11,T29
0	1	Covered	T28,T59,T130
1	0	Covered	T87,T132,T283

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T29,T54
0	1	Covered	T11,T29,T54
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T29,T54
1	-	Covered	T11,T29,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T11,T29
DetectSt	168	Covered	T28,T11,T29
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T29,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T11,T29
DebounceSt->IdleSt	163	Covered	T279,T69,T280
DetectSt->IdleSt	186	Covered	T28,T59,T87
DetectSt->StableSt	191	Covered	T11,T29,T54
IdleSt->DebounceSt	148	Covered	T28,T11,T29
StableSt->IdleSt	206	Covered	T11,T29,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T28,T11,T29
0	1	Covered	T28,T11,T29
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T11,T29
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T28,T11,T29
IdleSt	0	-	-	-	-	-	-	Covered	T28,T11,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T11,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T279,T69,T280
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T11,T29
DetectSt	-	-	-	-	1	-	-	Covered	T28,T59,T87
DetectSt	-	-	-	-	0	1	-	Covered	T11,T29,T54
DetectSt	-	-	-	-	0	0	-	Covered	T28,T11,T29
StableSt	-	-	-	-	-	-	1	Covered	T11,T29,T54
StableSt	-	-	-	-	-	-	0	Covered	T11,T29,T54
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	2630	0	0
CntIncr_A	8955184	88391	0	0
CntNoWrap_A	8955184	8304351	0	0
DetectStDropOut_A	8955184	436	0	0
DetectedOut_A	8955184	56668	0	0
DetectedPulseOut_A	8955184	673	0	0
DisabledIdleSt_A	8955184	7892714	0	0
DisabledNoDetection_A	8955184	7894910	0	0
EnterDebounceSt_A	8955184	1329	0	0
EnterDetectSt_A	8955184	1302	0	0
EnterStableSt_A	8955184	673	0	0
PulseIsPulse_A	8955184	673	0	0
StayInStableSt	8955184	55905	0	0
gen_high_event_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	583	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2630	0	0
T11	12088	8	0	0
T12	25979	0	0	0
T28	5016	20	0	0
T29	0	28	0	0
T52	0	20	0	0
T53	0	16	0	0
T54	0	14	0	0
T59	0	22	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	20	0	0
T86	0	16	0	0
T87	0	28	0	0
T88	432	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	88391	0	0
T11	12088	208	0	0
T12	25979	0	0	0
T28	5016	476	0	0
T29	0	812	0	0
T52	0	550	0	0
T53	0	640	0	0
T54	0	462	0	0
T59	0	514	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	560	0	0
T86	0	608	0	0
T87	0	570	0	0
T88	432	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8304351	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	436	0	0
T11	12088	0	0	0
T12	25979	0	0	0
T28	5016	10	0	0
T59	0	11	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T88	432	0	0	0
T121	0	22	0	0
T130	0	8	0	0
T133	0	30	0	0
T134	0	7	0	0
T237	0	7	0	0
T287	0	5	0	0
T288	0	13	0	0
T293	0	31	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	56668	0	0
T11	12088	118	0	0
T12	25979	0	0	0
T29	0	1349	0	0
T52	0	375	0	0
T53	0	61	0	0
T54	0	1023	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	616	0	0
T86	0	408	0	0
T88	432	0	0	0
T131	0	25	0	0
T281	0	211	0	0
T282	0	345	0	0
T284	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	673	0	0
T11	12088	4	0	0
T12	25979	0	0	0
T29	0	14	0	0
T52	0	10	0	0
T53	0	8	0	0
T54	0	7	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	10	0	0
T86	0	8	0	0
T88	432	0	0	0
T131	0	5	0	0
T281	0	6	0	0
T282	0	13	0	0
T284	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7892714	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7894910	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1329	0	0
T11	12088	4	0	0
T12	25979	0	0	0
T28	5016	10	0	0
T29	0	14	0	0
T52	0	10	0	0
T53	0	8	0	0
T54	0	7	0	0
T59	0	11	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	10	0	0
T86	0	8	0	0
T87	0	14	0	0
T88	432	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1302	0	0
T11	12088	4	0	0
T12	25979	0	0	0
T28	5016	10	0	0
T29	0	14	0	0
T52	0	10	0	0
T53	0	8	0	0
T54	0	7	0	0
T59	0	11	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	10	0	0
T86	0	8	0	0
T87	0	14	0	0
T88	432	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	673	0	0
T11	12088	4	0	0
T12	25979	0	0	0
T29	0	14	0	0
T52	0	10	0	0
T53	0	8	0	0
T54	0	7	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	10	0	0
T86	0	8	0	0
T88	432	0	0	0
T131	0	5	0	0
T281	0	6	0	0
T282	0	13	0	0
T284	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	673	0	0
T11	12088	4	0	0
T12	25979	0	0	0
T29	0	14	0	0
T52	0	10	0	0
T53	0	8	0	0
T54	0	7	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	10	0	0
T86	0	8	0	0
T88	432	0	0	0
T131	0	5	0	0
T281	0	6	0	0
T282	0	13	0	0
T284	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	55905	0	0
T11	12088	114	0	0
T12	25979	0	0	0
T29	0	1334	0	0
T52	0	365	0	0
T53	0	53	0	0
T54	0	1013	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	605	0	0
T86	0	400	0	0
T88	432	0	0	0
T131	0	20	0	0
T281	0	204	0	0
T282	0	332	0	0
T284	405	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	583	0	0
T11	12088	4	0	0
T12	25979	0	0	0
T29	0	13	0	0
T52	0	10	0	0
T53	0	8	0	0
T54	0	4	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	9	0	0
T86	0	8	0	0
T88	432	0	0	0
T131	0	5	0	0
T281	0	5	0	0
T282	0	13	0	0
T284	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T5,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T164,T294,T93
1	0	Covered	T69,T116

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
1	0	Covered	T117,T116

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T1,T3
1	-	Covered	T5,T1,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T3
DetectSt	168	Covered	T5,T1,T3
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T5,T1,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T3
DebounceSt->IdleSt	163	Covered	T5,T12,T127
DetectSt->IdleSt	186	Covered	T164,T294,T93
DetectSt->StableSt	191	Covered	T5,T1,T3
IdleSt->DebounceSt	148	Covered	T5,T1,T3
StableSt->IdleSt	206	Covered	T5,T1,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T3
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T12,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	1	-	-	Covered	T164,T294,T93
DetectSt	-	-	-	-	0	1	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	1	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	0	Covered	T5,T1,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	881	0	0
CntIncr_A	8955184	46053	0	0
CntNoWrap_A	8955184	8306100	0	0
DetectStDropOut_A	8955184	50	0	0
DetectedOut_A	8955184	16617	0	0
DetectedPulseOut_A	8955184	368	0	0
DisabledIdleSt_A	8955184	7965928	0	0
DisabledNoDetection_A	8955184	7967624	0	0
EnterDebounceSt_A	8955184	459	0	0
EnterDetectSt_A	8955184	422	0	0
EnterStableSt_A	8955184	368	0	0
PulseIsPulse_A	8955184	368	0	0
StayInStableSt	8955184	16197	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	310	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	881	0	0
T1	8953	2	0	0
T2	788	0	0	0
T3	38319	22	0	0
T5	38517	11	0	0
T9	0	4	0	0
T10	0	8	0	0
T12	0	11	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	2	0	0
T51	0	2	0	0
T70	0	10	0	0
T127	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	46053	0	0
T1	8953	89	0	0
T2	788	0	0	0
T3	38319	682	0	0
T5	38517	435	0	0
T9	0	130	0	0
T10	0	392	0	0
T12	0	674	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	56	0	0
T51	0	111	0	0
T70	0	628	0	0
T127	0	399	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306100	0	0
T1	8953	8543	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	35994	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	50	0	0
T40	15100	0	0	0
T89	1192	0	0	0
T93	0	4	0	0
T103	0	2	0	0
T129	698	0	0	0
T136	0	1	0	0
T139	0	5	0	0
T164	21865	2	0	0
T165	3568	0	0	0
T166	527	0	0	0
T167	489	0	0	0
T168	402	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T205	0	5	0	0
T294	0	8	0	0
T295	0	6	0	0
T296	0	7	0	0
T297	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	16617	0	0
T1	8953	65	0	0
T2	788	0	0	0
T3	38319	564	0	0
T5	38517	46	0	0
T9	0	49	0	0
T10	0	140	0	0
T12	0	22	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	53	0	0
T51	0	20	0	0
T70	0	36	0	0
T127	0	126	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	368	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	11	0	0
T5	38517	5	0	0
T9	0	2	0	0
T10	0	4	0	0
T12	0	5	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	1	0	0
T51	0	1	0	0
T70	0	4	0	0
T127	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7965928	0	0
T1	8953	4029	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	32869	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7967624	0	0
T1	8953	4029	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	32873	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	459	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	11	0	0
T5	38517	6	0	0
T9	0	2	0	0
T10	0	4	0	0
T12	0	6	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	1	0	0
T51	0	1	0	0
T70	0	6	0	0
T127	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	422	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	11	0	0
T5	38517	5	0	0
T9	0	2	0	0
T10	0	4	0	0
T12	0	5	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	1	0	0
T51	0	1	0	0
T70	0	4	0	0
T127	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	368	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	11	0	0
T5	38517	5	0	0
T9	0	2	0	0
T10	0	4	0	0
T12	0	5	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	1	0	0
T51	0	1	0	0
T70	0	4	0	0
T127	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	368	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	11	0	0
T5	38517	5	0	0
T9	0	2	0	0
T10	0	4	0	0
T12	0	5	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	1	0	0
T51	0	1	0	0
T70	0	4	0	0
T127	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	16197	0	0
T1	8953	64	0	0
T2	788	0	0	0
T3	38319	553	0	0
T5	38517	41	0	0
T9	0	47	0	0
T10	0	136	0	0
T12	0	17	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T29	0	51	0	0
T51	0	18	0	0
T70	0	32	0	0
T127	0	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	310	0	0
T1	8953	1	0	0
T2	788	0	0	0
T3	38319	11	0	0
T5	38517	5	0	0
T9	0	2	0	0
T10	0	4	0	0
T12	0	5	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T37	0	8	0	0
T54	0	2	0	0
T70	0	4	0	0
T127	0	3	0	0