Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T11,T29
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T11,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T11,T29
1	0	Covered	T11,T29,T54
1	1	Covered	T28,T11,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T11,T29
0	1	Covered	T28,T59,T130
1	0	Covered	T131,T287,T134

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T29,T54
0	1	Covered	T11,T29,T54
1	0	Covered	T120,T121

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T29,T54
1	-	Covered	T11,T29,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T11,T29
DetectSt	168	Covered	T28,T11,T29
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T29,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T11,T29
DebounceSt->IdleSt	163	Covered	T279,T69,T280
DetectSt->IdleSt	186	Covered	T28,T59,T130
DetectSt->StableSt	191	Covered	T11,T29,T54
IdleSt->DebounceSt	148	Covered	T28,T11,T29
StableSt->IdleSt	206	Covered	T11,T29,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T28,T11,T29
0	1	Covered	T28,T11,T29
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T11,T29
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T28,T11,T29
IdleSt	0	-	-	-	-	-	-	Covered	T28,T11,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T11,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T279,T69,T280
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T11,T29
DetectSt	-	-	-	-	1	-	-	Covered	T28,T59,T130
DetectSt	-	-	-	-	0	1	-	Covered	T11,T29,T54
DetectSt	-	-	-	-	0	0	-	Covered	T28,T11,T29
StableSt	-	-	-	-	-	-	1	Covered	T11,T29,T54
StableSt	-	-	-	-	-	-	0	Covered	T11,T29,T54
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	2996	0	0
CntIncr_A	8955184	102884	0	0
CntNoWrap_A	8955184	8303985	0	0
DetectStDropOut_A	8955184	431	0	0
DetectedOut_A	8955184	70322	0	0
DetectedPulseOut_A	8955184	822	0	0
DisabledIdleSt_A	8955184	7883816	0	0
DisabledNoDetection_A	8955184	7886004	0	0
EnterDebounceSt_A	8955184	1513	0	0
EnterDetectSt_A	8955184	1484	0	0
EnterStableSt_A	8955184	822	0	0
PulseIsPulse_A	8955184	822	0	0
StayInStableSt	8955184	69400	0	0
gen_high_event_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	719	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2996	0	0
T11	12088	44	0	0
T12	25979	0	0	0
T28	5016	48	0	0
T29	0	30	0	0
T52	0	46	0	0
T53	0	26	0	0
T54	0	18	0	0
T59	0	12	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	26	0	0
T86	0	48	0	0
T87	0	54	0	0
T88	432	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	102884	0	0
T11	12088	1210	0	0
T12	25979	0	0	0
T28	5016	1152	0	0
T29	0	525	0	0
T52	0	1886	0	0
T53	0	702	0	0
T54	0	594	0	0
T59	0	277	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	689	0	0
T86	0	1272	0	0
T87	0	1026	0	0
T88	432	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8303985	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	431	0	0
T11	12088	0	0	0
T12	25979	0	0	0
T28	5016	24	0	0
T59	0	6	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T88	432	0	0	0
T120	0	2	0	0
T130	0	2	0	0
T131	0	10	0	0
T133	0	22	0	0
T134	0	2	0	0
T237	0	27	0	0
T287	0	14	0	0
T288	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	70322	0	0
T11	12088	592	0	0
T12	25979	0	0	0
T29	0	474	0	0
T52	0	1361	0	0
T53	0	434	0	0
T54	0	1521	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	695	0	0
T86	0	4159	0	0
T87	0	1600	0	0
T88	432	0	0	0
T281	0	631	0	0
T282	0	289	0	0
T284	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	822	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T29	0	15	0	0
T52	0	23	0	0
T53	0	13	0	0
T54	0	9	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	13	0	0
T86	0	24	0	0
T87	0	27	0	0
T88	432	0	0	0
T281	0	11	0	0
T282	0	7	0	0
T284	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7883816	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7886004	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1513	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T28	5016	24	0	0
T29	0	15	0	0
T52	0	23	0	0
T53	0	13	0	0
T54	0	9	0	0
T59	0	6	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	13	0	0
T86	0	24	0	0
T87	0	27	0	0
T88	432	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1484	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T28	5016	24	0	0
T29	0	15	0	0
T52	0	23	0	0
T53	0	13	0	0
T54	0	9	0	0
T59	0	6	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	13	0	0
T86	0	24	0	0
T87	0	27	0	0
T88	432	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	822	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T29	0	15	0	0
T52	0	23	0	0
T53	0	13	0	0
T54	0	9	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	13	0	0
T86	0	24	0	0
T87	0	27	0	0
T88	432	0	0	0
T281	0	11	0	0
T282	0	7	0	0
T284	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	822	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T29	0	15	0	0
T52	0	23	0	0
T53	0	13	0	0
T54	0	9	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	13	0	0
T86	0	24	0	0
T87	0	27	0	0
T88	432	0	0	0
T281	0	11	0	0
T282	0	7	0	0
T284	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	69400	0	0
T11	12088	570	0	0
T12	25979	0	0	0
T29	0	459	0	0
T52	0	1337	0	0
T53	0	421	0	0
T54	0	1511	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	681	0	0
T86	0	4128	0	0
T87	0	1567	0	0
T88	432	0	0	0
T281	0	618	0	0
T282	0	282	0	0
T284	405	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	719	0	0
T11	12088	22	0	0
T12	25979	0	0	0
T29	0	15	0	0
T52	0	22	0	0
T53	0	13	0	0
T54	0	8	0	0
T63	412	0	0	0
T64	526	0	0	0
T65	521	0	0	0
T66	494	0	0	0
T67	904	0	0	0
T68	522	0	0	0
T85	0	12	0	0
T86	0	17	0	0
T87	0	21	0	0
T88	432	0	0	0
T281	0	9	0	0
T282	0	7	0	0
T284	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T1,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T9,T127,T192
1	0	Covered	T69,T116

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T10
0	1	Covered	T1,T3,T10
1	0	Covered	T298

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T10
1	-	Covered	T1,T3,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T9
DetectSt	168	Covered	T1,T3,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T9
DebounceSt->IdleSt	163	Covered	T1,T9,T12
DetectSt->IdleSt	186	Covered	T9,T127,T192
DetectSt->StableSt	191	Covered	T1,T3,T10
IdleSt->DebounceSt	148	Covered	T1,T3,T9
StableSt->IdleSt	206	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T9,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T127,T192
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	968	0	0
CntIncr_A	8955184	55715	0	0
CntNoWrap_A	8955184	8306013	0	0
DetectStDropOut_A	8955184	83	0	0
DetectedOut_A	8955184	16106	0	0
DetectedPulseOut_A	8955184	367	0	0
DisabledIdleSt_A	8955184	7948634	0	0
DisabledNoDetection_A	8955184	7950315	0	0
EnterDebounceSt_A	8955184	514	0	0
EnterDetectSt_A	8955184	454	0	0
EnterStableSt_A	8955184	367	0	0
PulseIsPulse_A	8955184	367	0	0
StayInStableSt	8955184	15718	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	342	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	968	0	0
T1	8953	28	0	0
T2	788	0	0	0
T3	38319	4	0	0
T9	0	17	0	0
T10	0	14	0	0
T12	0	21	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	21	0	0
T54	0	5	0	0
T127	0	9	0	0
T192	0	12	0	0
T223	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	55715	0	0
T1	8953	1738	0	0
T2	788	0	0	0
T3	38319	118	0	0
T9	0	761	0	0
T10	0	882	0	0
T12	0	1149	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	1365	0	0
T54	0	127	0	0
T127	0	525	0	0
T192	0	793	0	0
T223	0	1033	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306013	0	0
T1	8953	8517	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	83	0	0
T9	12144	8	0	0
T10	32256	0	0	0
T11	12088	0	0	0
T28	5016	0	0	0
T71	319237	0	0	0
T72	750	0	0	0
T83	502	0	0	0
T93	0	1	0	0
T108	404	0	0	0
T127	0	4	0	0
T143	409	0	0	0
T144	402	0	0	0
T192	0	6	0	0
T227	0	3	0	0
T292	0	13	0	0
T299	0	9	0	0
T300	0	5	0	0
T301	0	4	0	0
T302	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	16106	0	0
T1	8953	426	0	0
T2	788	0	0	0
T3	38319	106	0	0
T10	0	45	0	0
T12	0	160	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	891	0	0
T54	0	187	0	0
T85	0	58	0	0
T164	0	398	0	0
T223	0	106	0	0
T303	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	367	0	0
T1	8953	13	0	0
T2	788	0	0	0
T3	38319	2	0	0
T10	0	7	0	0
T12	0	10	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	10	0	0
T54	0	2	0	0
T85	0	1	0	0
T164	0	5	0	0
T223	0	5	0	0
T303	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7948634	0	0
T1	8953	4029	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	32869	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7950315	0	0
T1	8953	4029	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	32873	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	514	0	0
T1	8953	15	0	0
T2	788	0	0	0
T3	38319	2	0	0
T9	0	9	0	0
T10	0	7	0	0
T12	0	11	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	11	0	0
T54	0	3	0	0
T127	0	5	0	0
T192	0	6	0	0
T223	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	454	0	0
T1	8953	13	0	0
T2	788	0	0	0
T3	38319	2	0	0
T9	0	8	0	0
T10	0	7	0	0
T12	0	10	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	10	0	0
T54	0	2	0	0
T127	0	4	0	0
T192	0	6	0	0
T223	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	367	0	0
T1	8953	13	0	0
T2	788	0	0	0
T3	38319	2	0	0
T10	0	7	0	0
T12	0	10	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	10	0	0
T54	0	2	0	0
T85	0	1	0	0
T164	0	5	0	0
T223	0	5	0	0
T303	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	367	0	0
T1	8953	13	0	0
T2	788	0	0	0
T3	38319	2	0	0
T10	0	7	0	0
T12	0	10	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	10	0	0
T54	0	2	0	0
T85	0	1	0	0
T164	0	5	0	0
T223	0	5	0	0
T303	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	15718	0	0
T1	8953	413	0	0
T2	788	0	0	0
T3	38319	104	0	0
T10	0	38	0	0
T12	0	150	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	881	0	0
T54	0	185	0	0
T85	0	56	0	0
T164	0	393	0	0
T223	0	101	0	0
T303	0	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	342	0	0
T1	8953	13	0	0
T2	788	0	0	0
T3	38319	2	0	0
T10	0	7	0	0
T12	0	10	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T37	0	10	0	0
T54	0	2	0	0
T164	0	5	0	0
T223	0	5	0	0
T303	0	2	0	0
T304	0	1	0	0