Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1244620364	8749	0	0
auto_block_debounce_ctl_rd_A	1244620364	1529	0	0
auto_block_out_ctl_rd_A	1244620364	2409	0	0
com_det_ctl_0_rd_A	1244620364	3245	0	0
com_det_ctl_1_rd_A	1244620364	3411	0	0
com_det_ctl_2_rd_A	1244620364	3427	0	0
com_det_ctl_3_rd_A	1244620364	3347	0	0
com_out_ctl_0_rd_A	1244620364	3894	0	0
com_out_ctl_1_rd_A	1244620364	3950	0	0
com_out_ctl_2_rd_A	1244620364	3630	0	0
com_out_ctl_3_rd_A	1244620364	3912	0	0
com_pre_det_ctl_0_rd_A	1244620364	1070	0	0
com_pre_det_ctl_1_rd_A	1244620364	1070	0	0
com_pre_det_ctl_2_rd_A	1244620364	970	0	0
com_pre_det_ctl_3_rd_A	1244620364	1018	0	0
com_pre_sel_ctl_0_rd_A	1244620364	3871	0	0
com_pre_sel_ctl_1_rd_A	1244620364	3935	0	0
com_pre_sel_ctl_2_rd_A	1244620364	3977	0	0
com_pre_sel_ctl_3_rd_A	1244620364	4270	0	0
com_sel_ctl_0_rd_A	1244620364	4162	0	0
com_sel_ctl_1_rd_A	1244620364	3993	0	0
com_sel_ctl_2_rd_A	1244620364	3938	0	0
com_sel_ctl_3_rd_A	1244620364	4114	0	0
ec_rst_ctl_rd_A	1244620364	1980	0	0
intr_enable_rd_A	1244620364	1550	0	0
key_intr_ctl_rd_A	1244620364	3680	0	0
key_intr_debounce_ctl_rd_A	1244620364	1110	0	0
key_invert_ctl_rd_A	1244620364	4577	0	0
pin_allowed_ctl_rd_A	1244620364	6058	0	0
pin_out_ctl_rd_A	1244620364	4742	0	0
pin_out_value_rd_A	1244620364	4999	0	0
regwen_rd_A	1244620364	1246	0	0
ulp_ac_debounce_ctl_rd_A	1244620364	1282	0	0
ulp_ctl_rd_A	1244620364	1217	0	0
ulp_lid_debounce_ctl_rd_A	1244620364	1077	0	0
ulp_pwrb_debounce_ctl_rd_A	1244620364	1150	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	8749	0	0
T8	215836	10	0	0
T9	595089	4	0	0
T10	161285	0	0	0
T36	0	5	0	0
T40	0	10	0	0
T51	0	7	0	0
T70	0	12	0	0
T71	399046	0	0	0
T72	371212	0	0	0
T78	71831	0	0	0
T82	103618	0	0	0
T101	0	19	0	0
T108	99075	0	0	0
T143	38913	0	0	0
T144	201455	0	0	0
T165	0	8	0	0
T233	0	6	0	0
T313	0	13	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1529	0	0
T35	116649	0	0	0
T36	216452	23	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T57	0	15	0	0
T60	0	16	0	0
T61	0	9	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T128	0	3	0	0
T135	0	8	0	0
T156	0	3	0	0
T165	0	10	0	0
T191	13053	0	0	0
T225	0	35	0	0
T300	0	9	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	2409	0	0
T35	116649	0	0	0
T36	216452	14	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T57	0	16	0	0
T60	0	20	0	0
T61	0	27	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T128	0	4	0	0
T156	0	3	0	0
T165	0	12	0	0
T191	13053	0	0	0
T199	0	34	0	0
T225	0	28	0	0
T300	0	7	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3245	0	0
T1	223838	60	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	35	0	0
T11	0	40	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	26	0	0
T53	0	11	0	0
T86	0	29	0	0
T127	0	72	0	0
T165	0	9	0	0
T299	0	64	0	0
T308	0	48	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3411	0	0
T1	223838	78	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	53	0	0
T11	0	35	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	24	0	0
T53	0	39	0	0
T86	0	20	0	0
T127	0	78	0	0
T165	0	24	0	0
T299	0	71	0	0
T308	0	67	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3427	0	0
T1	223838	96	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	46	0	0
T11	0	44	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	47	0	0
T53	0	37	0	0
T86	0	41	0	0
T127	0	74	0	0
T165	0	19	0	0
T299	0	71	0	0
T308	0	43	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3347	0	0
T1	223838	83	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	63	0	0
T11	0	30	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	24	0	0
T53	0	45	0	0
T86	0	47	0	0
T127	0	52	0	0
T165	0	17	0	0
T299	0	74	0	0
T308	0	61	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3894	0	0
T1	223838	77	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	29	0	0
T11	0	28	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	25	0	0
T53	0	20	0	0
T86	0	29	0	0
T127	0	68	0	0
T165	0	16	0	0
T299	0	59	0	0
T308	0	65	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3950	0	0
T1	223838	57	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	22	0	0
T11	0	32	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	17	0	0
T53	0	48	0	0
T86	0	36	0	0
T127	0	78	0	0
T165	0	21	0	0
T299	0	86	0	0
T308	0	72	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3630	0	0
T1	223838	67	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	36	0	0
T11	0	53	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	34	0	0
T53	0	20	0	0
T86	0	30	0	0
T127	0	63	0	0
T165	0	31	0	0
T299	0	56	0	0
T308	0	56	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3912	0	0
T1	223838	60	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	44	0	0
T11	0	42	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	24	0	0
T53	0	19	0	0
T86	0	33	0	0
T127	0	74	0	0
T165	0	15	0	0
T299	0	67	0	0
T308	0	69	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1070	0	0
T35	116649	0	0	0
T36	216452	14	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T156	0	8	0	0
T165	0	9	0	0
T191	13053	0	0	0
T199	0	17	0	0
T225	0	35	0	0
T228	0	8	0	0
T268	0	23	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	15	0	0
T318	0	24	0	0
T319	0	17	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1070	0	0
T35	116649	0	0	0
T36	216452	20	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T165	0	6	0	0
T191	13053	0	0	0
T199	0	27	0	0
T212	0	32	0	0
T225	0	56	0	0
T228	0	22	0	0
T268	0	5	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	14	0	0
T318	0	37	0	0
T319	0	18	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	970	0	0
T35	116649	0	0	0
T36	216452	11	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T165	0	11	0	0
T191	13053	0	0	0
T199	0	34	0	0
T212	0	13	0	0
T225	0	46	0	0
T228	0	6	0	0
T268	0	17	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	28	0	0
T318	0	31	0	0
T319	0	13	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1018	0	0
T35	116649	0	0	0
T36	216452	22	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T165	0	17	0	0
T191	13053	0	0	0
T199	0	46	0	0
T212	0	7	0	0
T225	0	29	0	0
T228	0	9	0	0
T268	0	6	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	10	0	0
T318	0	43	0	0
T319	0	12	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3871	0	0
T1	223838	66	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	35	0	0
T11	0	38	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	23	0	0
T53	0	25	0	0
T86	0	55	0	0
T127	0	70	0	0
T165	0	15	0	0
T299	0	63	0	0
T308	0	70	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3935	0	0
T1	223838	62	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	52	0	0
T11	0	43	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	32	0	0
T53	0	27	0	0
T86	0	42	0	0
T127	0	84	0	0
T165	0	21	0	0
T299	0	57	0	0
T308	0	73	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3977	0	0
T1	223838	79	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	46	0	0
T11	0	44	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	33	0	0
T53	0	45	0	0
T86	0	24	0	0
T127	0	83	0	0
T165	0	19	0	0
T299	0	85	0	0
T308	0	63	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	4270	0	0
T1	223838	56	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	42	0	0
T11	0	22	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	18	0	0
T53	0	39	0	0
T86	0	20	0	0
T127	0	69	0	0
T165	0	9	0	0
T299	0	68	0	0
T308	0	87	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	4162	0	0
T1	223838	76	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	43	0	0
T11	0	47	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	21	0	0
T53	0	27	0	0
T86	0	35	0	0
T127	0	68	0	0
T165	0	7	0	0
T299	0	63	0	0
T308	0	64	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3993	0	0
T1	223838	67	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	46	0	0
T11	0	39	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	17	0	0
T53	0	29	0	0
T86	0	23	0	0
T127	0	83	0	0
T165	0	22	0	0
T299	0	81	0	0
T308	0	69	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3938	0	0
T1	223838	64	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	52	0	0
T11	0	34	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	36	0	0
T53	0	17	0	0
T86	0	24	0	0
T127	0	57	0	0
T165	0	21	0	0
T299	0	57	0	0
T308	0	76	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	4114	0	0
T1	223838	81	0	0
T2	222286	0	0	0
T3	613112	0	0	0
T10	0	42	0	0
T11	0	35	0	0
T13	185448	0	0	0
T14	345429	0	0	0
T15	98950	0	0	0
T16	53327	0	0	0
T17	49910	0	0	0
T18	98968	0	0	0
T19	125626	0	0	0
T36	0	22	0	0
T53	0	25	0	0
T86	0	49	0	0
T127	0	72	0	0
T165	0	8	0	0
T299	0	70	0	0
T308	0	79	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1980	0	0
T10	161285	37	0	0
T11	580225	8	0	0
T28	248278	0	0	0
T36	0	24	0	0
T63	22696	0	0	0
T71	399046	0	0	0
T72	371212	0	0	0
T83	246192	0	0	0
T86	0	14	0	0
T108	99075	0	0	0
T127	0	18	0	0
T143	38913	0	0	0
T144	201455	0	0	0
T151	0	2	0	0
T165	0	16	0	0
T169	0	6	0	0
T250	0	1	0	0
T308	0	40	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1550	0	0
T35	116649	0	0	0
T36	216452	23	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T156	0	9	0	0
T165	0	11	0	0
T191	13053	0	0	0
T199	0	51	0	0
T225	0	45	0	0
T256	0	27	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	24	0	0
T318	0	26	0	0
T319	0	20	0	0
T320	0	20	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	3680	0	0
T7	76500	4	0	0
T8	215836	0	0	0
T9	595089	0	0	0
T10	161285	0	0	0
T36	0	6	0	0
T42	0	4	0	0
T43	0	6	0	0
T61	0	4	0	0
T71	399046	0	0	0
T78	71831	0	0	0
T82	103618	0	0	0
T108	99075	0	0	0
T143	38913	0	0	0
T144	201455	0	0	0
T165	0	16	0	0
T196	0	2	0	0
T217	0	5	0	0
T225	0	36	0	0
T226	0	4	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1110	0	0
T35	116649	0	0	0
T36	216452	23	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T165	0	19	0	0
T191	13053	0	0	0
T199	0	33	0	0
T212	0	13	0	0
T225	0	49	0	0
T228	0	9	0	0
T268	0	30	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	17	0	0
T318	0	44	0	0
T319	0	7	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	4577	0	0
T6	53205	0	0	0
T7	76500	0	0	0
T8	215836	0	0	0
T25	91348	34	0	0
T26	61918	0	0	0
T27	250961	0	0	0
T34	13032	0	0	0
T35	0	69	0	0
T36	0	159	0	0
T73	37090	0	0	0
T79	0	58	0	0
T81	108143	0	0	0
T82	103618	0	0	0
T165	0	56	0	0
T182	0	38	0	0
T214	0	80	0	0
T271	0	72	0	0
T275	0	47	0	0
T321	0	46	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	6058	0	0
T35	116649	159	0	0
T36	216452	26	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T156	0	39	0	0
T165	0	75	0	0
T191	13053	0	0	0
T199	0	146	0	0
T225	0	261	0	0
T258	0	53	0	0
T300	0	45	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T322	0	66	0	0
T323	0	73	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	4742	0	0
T35	116649	137	0	0
T36	216452	22	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T156	0	19	0	0
T165	0	90	0	0
T191	13053	0	0	0
T199	0	185	0	0
T225	0	252	0	0
T258	0	87	0	0
T300	0	76	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T322	0	64	0	0
T323	0	66	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	4999	0	0
T35	116649	162	0	0
T36	216452	22	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T156	0	63	0	0
T165	0	109	0	0
T191	13053	0	0	0
T199	0	147	0	0
T225	0	267	0	0
T258	0	48	0	0
T300	0	62	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T322	0	83	0	0
T323	0	62	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1246	0	0
T35	116649	0	0	0
T36	216452	21	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T127	150677	0	0	0
T156	0	3	0	0
T165	0	18	0	0
T191	13053	0	0	0
T199	0	32	0	0
T225	0	47	0	0
T228	0	11	0	0
T268	0	17	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	35	0	0
T318	0	45	0	0
T319	0	21	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1282	0	0
T35	116649	0	0	0
T36	216452	22	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T123	0	12	0	0
T127	150677	0	0	0
T156	0	4	0	0
T165	0	11	0	0
T191	13053	0	0	0
T199	0	34	0	0
T225	0	21	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	10	0	0
T318	0	47	0	0
T320	0	4	0	0
T324	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1217	0	0
T24	0	6	0	0
T35	116649	0	0	0
T36	216452	5	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T123	0	4	0	0
T127	150677	0	0	0
T156	0	2	0	0
T165	0	16	0	0
T191	13053	0	0	0
T199	0	24	0	0
T225	0	38	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	27	0	0
T318	0	33	0	0
T324	0	9	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1077	0	0
T24	0	7	0	0
T35	116649	0	0	0
T36	216452	17	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T123	0	13	0	0
T127	150677	0	0	0
T156	0	1	0	0
T165	0	12	0	0
T191	13053	0	0	0
T199	0	38	0	0
T225	0	16	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	18	0	0
T318	0	19	0	0
T324	0	6	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1244620364	1150	0	0
T35	116649	0	0	0
T36	216452	7	0	0
T49	219794	0	0	0
T56	192226	0	0	0
T75	33575	0	0	0
T123	0	12	0	0
T127	150677	0	0	0
T165	0	15	0	0
T191	13053	0	0	0
T199	0	38	0	0
T225	0	40	0	0
T314	139688	0	0	0
T315	99262	0	0	0
T316	53314	0	0	0
T317	0	29	0	0
T318	0	42	0	0
T319	0	25	0	0
T324	0	9	0	0
T325	0	10	0	0