Module Definition
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Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ec_rst_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_ac_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_lid_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_pwrb_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_ulp_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.88 100.00 87.50 100.00 100.00 u_wkup_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_invert_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_allowed_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_out_value_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_intr_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_intr_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_auto_block_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_auto_block_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T15
10CoveredT5,T1,T15
11CoveredT15,T2,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T15
10CoveredT15,T2,T8
11CoveredT5,T1,T15

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 232175 0 0
SrcPulseCheck_M 2147483647 233862 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 232175 0 0
T1 1862328 32 0 0
T2 2230740 0 0 0
T3 6514310 272 0 0
T5 4005792 260 0 0
T8 0 64 0 0
T9 0 62 0 0
T10 0 224 0 0
T11 580225 34 0 0
T12 0 176 0 0
T13 1486800 0 0 0
T14 3461480 14 0 0
T15 1011120 0 0 0
T16 537530 0 0 0
T17 503640 0 0 0
T18 993720 0 0 0
T19 252298 0 0 0
T25 183684 0 0 0
T27 502966 0 0 0
T28 248278 17 0 0
T29 0 2 0 0
T36 0 16 0 0
T54 0 5 0 0
T55 0 12 0 0
T56 0 14 0 0
T57 0 12 0 0
T58 0 16 0 0
T59 0 1 0 0
T60 0 14 0 0
T61 0 42 0 0
T62 0 16 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 233862 0 0
T1 1862328 32 0 0
T2 2230740 0 0 0
T3 6514310 272 0 0
T5 4005792 260 0 0
T8 0 64 0 0
T9 0 62 0 0
T10 0 224 0 0
T11 12088 34 0 0
T12 0 176 0 0
T13 1486800 0 0 0
T14 3461480 14 0 0
T15 1011120 0 0 0
T16 537530 0 0 0
T17 503640 0 0 0
T18 993720 0 0 0
T19 252298 0 0 0
T25 183684 0 0 0
T27 502966 0 0 0
T28 5016 17 0 0
T29 0 2 0 0
T36 0 16 0 0
T54 0 5 0 0
T55 0 12 0 0
T56 0 14 0 0
T57 0 12 0 0
T58 0 16 0 0
T59 0 1 0 0
T60 0 14 0 0
T61 0 42 0 0
T62 0 16 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT32,T21,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT32,T21,T23
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 2007 0 0
SrcPulseCheck_M 1244620364 2055 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 2007 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 18 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T71 0 1 0 0
T72 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 2055 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 18 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T71 0 1 0 0
T72 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT32,T21,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT32,T21,T23
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 2047 0 0
SrcPulseCheck_M 9202852 2047 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 2047 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 18 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T71 0 1 0 0
T72 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 2047 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 18 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T71 0 1 0 0
T72 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T34
11CoveredT15,T2,T76

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T76
11CoveredT15,T2,T34

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1046 0 0
SrcPulseCheck_M 1244620364 1095 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1046 0 0
T2 788 2 0 0
T3 38319 0 0 0
T6 659 0 0 0
T8 0 3 0 0
T15 2162 3 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T24 0 2 0 0
T25 494 0 0 0
T27 522 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1095 0 0
T2 222286 2 0 0
T3 613112 0 0 0
T6 53205 0 0 0
T8 0 3 0 0
T15 98950 3 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T24 0 2 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T34
11CoveredT15,T2,T76

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T76
11CoveredT15,T2,T34

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1086 0 0
SrcPulseCheck_M 9202852 1086 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1086 0 0
T2 222286 2 0 0
T3 613112 0 0 0
T6 53205 0 0 0
T8 0 3 0 0
T15 98950 3 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T24 0 2 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1086 0 0
T2 788 2 0 0
T3 38319 0 0 0
T6 659 0 0 0
T8 0 3 0 0
T15 2162 3 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T24 0 2 0 0
T25 494 0 0 0
T27 522 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T34
11CoveredT15,T2,T76

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T76
11CoveredT15,T2,T34

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1037 0 0
SrcPulseCheck_M 1244620364 1084 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1037 0 0
T2 788 2 0 0
T3 38319 0 0 0
T6 659 0 0 0
T8 0 3 0 0
T15 2162 3 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T24 0 2 0 0
T25 494 0 0 0
T27 522 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1084 0 0
T2 222286 2 0 0
T3 613112 0 0 0
T6 53205 0 0 0
T8 0 3 0 0
T15 98950 3 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T24 0 2 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T34
11CoveredT15,T2,T76

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T76
11CoveredT15,T2,T34

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1076 0 0
SrcPulseCheck_M 9202852 1077 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1076 0 0
T2 222286 2 0 0
T3 613112 0 0 0
T6 53205 0 0 0
T8 0 3 0 0
T15 98950 3 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T24 0 2 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1077 0 0
T2 788 2 0 0
T3 38319 0 0 0
T6 659 0 0 0
T8 0 3 0 0
T15 2162 3 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T24 0 2 0 0
T25 494 0 0 0
T27 522 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T34
11CoveredT15,T2,T76

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T76
11CoveredT15,T2,T34

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1006 0 0
SrcPulseCheck_M 1244620364 1056 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1006 0 0
T2 788 2 0 0
T3 38319 0 0 0
T6 659 0 0 0
T8 0 3 0 0
T15 2162 3 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T24 0 2 0 0
T25 494 0 0 0
T27 522 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1056 0 0
T2 222286 2 0 0
T3 613112 0 0 0
T6 53205 0 0 0
T8 0 3 0 0
T15 98950 3 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T24 0 2 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T34
11CoveredT15,T2,T76

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT15,T2,T34
10CoveredT15,T2,T76
11CoveredT15,T2,T34

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1046 0 0
SrcPulseCheck_M 9202852 1046 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1046 0 0
T2 222286 2 0 0
T3 613112 0 0 0
T6 53205 0 0 0
T8 0 3 0 0
T15 98950 3 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T24 0 2 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1046 0 0
T2 788 2 0 0
T3 38319 0 0 0
T6 659 0 0 0
T8 0 3 0 0
T15 2162 3 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T24 0 2 0 0
T25 494 0 0 0
T27 522 0 0 0
T34 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0
T75 0 1 0 0
T76 0 3 0 0
T77 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT2,T8,T24
10CoveredT2,T8,T24
11CoveredT2,T8,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT2,T8,T24
10CoveredT2,T8,T24
11CoveredT2,T8,T24

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1048 0 0
SrcPulseCheck_M 1244620364 1098 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1048 0 0
T2 788 2 0 0
T3 38319 0 0 0
T6 659 0 0 0
T8 0 4 0 0
T18 404 0 0 0
T19 523 0 0 0
T24 0 2 0 0
T25 494 0 0 0
T26 495 0 0 0
T27 522 0 0 0
T34 656 0 0 0
T77 0 2 0 0
T81 502 0 0 0
T89 0 4 0 0
T90 0 4 0 0
T91 0 2 0 0
T92 0 4 0 0
T93 0 2 0 0
T94 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1098 0 0
T2 222286 2 0 0
T3 613112 0 0 0
T6 53205 0 0 0
T8 0 4 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T24 0 2 0 0
T25 91348 0 0 0
T26 61918 0 0 0
T27 250961 0 0 0
T34 13032 0 0 0
T77 0 2 0 0
T81 108143 0 0 0
T89 0 4 0 0
T90 0 4 0 0
T91 0 2 0 0
T92 0 4 0 0
T93 0 2 0 0
T94 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT2,T8,T24
10CoveredT2,T8,T24
11CoveredT2,T8,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT2,T8,T24
10CoveredT2,T8,T24
11CoveredT2,T8,T24

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1088 0 0
SrcPulseCheck_M 9202852 1088 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1088 0 0
T2 222286 2 0 0
T3 613112 0 0 0
T6 53205 0 0 0
T8 0 4 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T24 0 2 0 0
T25 91348 0 0 0
T26 61918 0 0 0
T27 250961 0 0 0
T34 13032 0 0 0
T77 0 2 0 0
T81 108143 0 0 0
T89 0 4 0 0
T90 0 4 0 0
T91 0 2 0 0
T92 0 4 0 0
T93 0 2 0 0
T94 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1088 0 0
T2 788 2 0 0
T3 38319 0 0 0
T6 659 0 0 0
T8 0 4 0 0
T18 404 0 0 0
T19 523 0 0 0
T24 0 2 0 0
T25 494 0 0 0
T26 495 0 0 0
T27 522 0 0 0
T34 656 0 0 0
T77 0 2 0 0
T81 502 0 0 0
T89 0 4 0 0
T90 0 4 0 0
T91 0 2 0 0
T92 0 4 0 0
T93 0 2 0 0
T94 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T89,T307

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T89,T307
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1086 0 0
SrcPulseCheck_M 1244620364 1136 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1086 0 0
T1 8953 13 0 0
T2 788 1 0 0
T3 38319 11 0 0
T8 0 4 0 0
T9 0 3 0 0
T10 0 4 0 0
T11 0 1 0 0
T12 0 10 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T36 0 1 0 0
T70 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1136 0 0
T1 223838 13 0 0
T2 222286 1 0 0
T3 613112 11 0 0
T8 0 4 0 0
T9 0 3 0 0
T10 0 4 0 0
T11 0 1 0 0
T12 0 10 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T36 0 1 0 0
T70 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT25,T26,T8
10CoveredT25,T26,T8
11CoveredT25,T26,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT25,T26,T8
10CoveredT25,T26,T8
11CoveredT25,T26,T8

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 3208 0 0
SrcPulseCheck_M 1244620364 3255 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 3208 0 0
T6 659 0 0 0
T7 1131 0 0 0
T8 18107 80 0 0
T9 0 20 0 0
T25 494 20 0 0
T26 495 20 0 0
T27 522 0 0 0
T34 656 0 0 0
T35 0 20 0 0
T36 0 40 0 0
T66 0 20 0 0
T73 770 0 0 0
T78 0 20 0 0
T79 0 20 0 0
T80 0 20 0 0
T81 502 0 0 0
T82 422 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 3255 0 0
T6 53205 0 0 0
T7 76500 0 0 0
T8 215836 80 0 0
T9 0 20 0 0
T25 91348 20 0 0
T26 61918 20 0 0
T27 250961 0 0 0
T34 13032 0 0 0
T35 0 20 0 0
T36 0 40 0 0
T66 0 20 0 0
T73 37090 0 0 0
T78 0 20 0 0
T79 0 20 0 0
T80 0 20 0 0
T81 108143 0 0 0
T82 103618 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT25,T26,T8
10CoveredT25,T26,T8
11CoveredT25,T26,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT25,T26,T8
10CoveredT25,T26,T8
11CoveredT25,T26,T8

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 3248 0 0
SrcPulseCheck_M 9202852 3248 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 3248 0 0
T6 53205 0 0 0
T7 76500 0 0 0
T8 215836 80 0 0
T9 0 20 0 0
T25 91348 20 0 0
T26 61918 20 0 0
T27 250961 0 0 0
T34 13032 0 0 0
T35 0 20 0 0
T36 0 40 0 0
T66 0 20 0 0
T73 37090 0 0 0
T78 0 20 0 0
T79 0 20 0 0
T80 0 20 0 0
T81 108143 0 0 0
T82 103618 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 3248 0 0
T6 659 0 0 0
T7 1131 0 0 0
T8 18107 80 0 0
T9 0 20 0 0
T25 494 20 0 0
T26 495 20 0 0
T27 522 0 0 0
T34 656 0 0 0
T35 0 20 0 0
T36 0 40 0 0
T66 0 20 0 0
T73 770 0 0 0
T78 0 20 0 0
T79 0 20 0 0
T80 0 20 0 0
T81 502 0 0 0
T82 422 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T19,T25
10CoveredT5,T19,T25
11CoveredT5,T19,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T19,T25
10CoveredT5,T19,T27
11CoveredT5,T19,T25

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 6609 0 0
SrcPulseCheck_M 1244620364 6660 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 6609 0 0
T1 8953 0 0 0
T2 788 0 0 0
T3 38319 0 0 0
T5 38517 40 0 0
T8 0 104 0 0
T9 0 1 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 0 20 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 20 0 0
T78 0 1 0 0
T81 0 20 0 0
T83 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 6660 0 0
T1 223838 0 0 0
T2 222286 0 0 0
T3 613112 0 0 0
T5 462207 40 0 0
T8 0 104 0 0
T9 0 1 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 0 20 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 20 0 0
T78 0 1 0 0
T81 0 20 0 0
T83 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T19,T25
10CoveredT5,T19,T25
11CoveredT5,T19,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T19,T25
10CoveredT5,T19,T27
11CoveredT5,T19,T25

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 6649 0 0
SrcPulseCheck_M 9202852 6649 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 6649 0 0
T1 223838 0 0 0
T2 222286 0 0 0
T3 613112 0 0 0
T5 462207 40 0 0
T8 0 104 0 0
T9 0 1 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 0 20 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 20 0 0
T78 0 1 0 0
T81 0 20 0 0
T83 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 6649 0 0
T1 8953 0 0 0
T2 788 0 0 0
T3 38319 0 0 0
T5 38517 40 0 0
T8 0 104 0 0
T9 0 1 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 0 20 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 20 0 0
T78 0 1 0 0
T81 0 20 0 0
T83 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT5,T19,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T19,T27
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 7808 0 0
SrcPulseCheck_M 1244620364 7856 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7808 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 58 0 0
T8 0 108 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 0 20 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 20 0 0
T78 0 1 0 0
T81 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7856 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 58 0 0
T8 0 108 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 0 20 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 20 0 0
T78 0 1 0 0
T81 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT5,T19,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T19,T27
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 7844 0 0
SrcPulseCheck_M 9202852 7845 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7844 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 58 0 0
T8 0 108 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 0 20 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 20 0 0
T78 0 1 0 0
T81 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7845 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 58 0 0
T8 0 108 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 0 20 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 20 0 0
T78 0 1 0 0
T81 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T19,T27
10CoveredT5,T19,T27
11CoveredT5,T19,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T19,T27
10CoveredT5,T19,T27
11CoveredT5,T19,T27

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 6491 0 0
SrcPulseCheck_M 1244620364 6543 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 6491 0 0
T1 8953 0 0 0
T2 788 0 0 0
T3 38319 0 0 0
T5 38517 40 0 0
T8 0 100 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 0 20 0 0
T27 0 20 0 0
T64 0 20 0 0
T65 0 20 0 0
T68 0 20 0 0
T81 0 20 0 0
T83 0 20 0 0
T84 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 6543 0 0
T1 223838 0 0 0
T2 222286 0 0 0
T3 613112 0 0 0
T5 462207 40 0 0
T8 0 100 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 0 20 0 0
T27 0 20 0 0
T64 0 20 0 0
T65 0 20 0 0
T68 0 20 0 0
T81 0 20 0 0
T83 0 20 0 0
T84 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T19,T27
10CoveredT5,T19,T27
11CoveredT5,T19,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T19,T27
10CoveredT5,T19,T27
11CoveredT5,T19,T27

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 6532 0 0
SrcPulseCheck_M 9202852 6532 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 6532 0 0
T1 223838 0 0 0
T2 222286 0 0 0
T3 613112 0 0 0
T5 462207 40 0 0
T8 0 100 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 0 20 0 0
T27 0 20 0 0
T64 0 20 0 0
T65 0 20 0 0
T68 0 20 0 0
T81 0 20 0 0
T83 0 20 0 0
T84 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 6532 0 0
T1 8953 0 0 0
T2 788 0 0 0
T3 38319 0 0 0
T5 38517 40 0 0
T8 0 100 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 0 20 0 0
T27 0 20 0 0
T64 0 20 0 0
T65 0 20 0 0
T68 0 20 0 0
T81 0 20 0 0
T83 0 20 0 0
T84 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT6,T7,T8
10CoveredT69,T116,T20
11CoveredT6,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1020 0 0
SrcPulseCheck_M 1244620364 1072 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1020 0 0
T6 659 1 0 0
T7 1131 1 0 0
T8 18107 1 0 0
T9 12144 0 0 0
T26 495 0 0 0
T34 656 0 0 0
T38 0 1 0 0
T41 0 1 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 1 0 0
T73 770 0 0 0
T78 495 0 0 0
T81 502 0 0 0
T82 422 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1072 0 0
T6 53205 1 0 0
T7 76500 1 0 0
T8 215836 1 0 0
T9 595089 0 0 0
T26 61918 0 0 0
T34 13032 0 0 0
T38 0 1 0 0
T41 0 1 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 1 0 0
T73 37090 0 0 0
T78 71831 0 0 0
T81 108143 0 0 0
T82 103618 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT6,T7,T8
10CoveredT69,T116,T20
11CoveredT6,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1062 0 0
SrcPulseCheck_M 9202852 1063 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1062 0 0
T6 53205 1 0 0
T7 76500 1 0 0
T8 215836 1 0 0
T9 595089 0 0 0
T26 61918 0 0 0
T34 13032 0 0 0
T38 0 1 0 0
T41 0 1 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 1 0 0
T73 37090 0 0 0
T78 71831 0 0 0
T81 108143 0 0 0
T82 103618 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1063 0 0
T6 659 1 0 0
T7 1131 1 0 0
T8 18107 1 0 0
T9 12144 0 0 0
T26 495 0 0 0
T34 656 0 0 0
T38 0 1 0 0
T41 0 1 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 1 0 0
T73 770 0 0 0
T78 495 0 0 0
T81 502 0 0 0
T82 422 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 2049 0 0
SrcPulseCheck_M 1244620364 2100 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 2049 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 17 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 3 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 2100 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 17 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 3 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 2090 0 0
SrcPulseCheck_M 9202852 2090 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 2090 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 17 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 3 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 2090 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 17 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 3 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT14,T8,T9
10CoveredT14,T8,T9
11CoveredT14,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT14,T8,T9
10CoveredT14,T8,T9
11CoveredT14,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1408 0 0
SrcPulseCheck_M 1244620364 1456 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1408 0 0
T2 788 0 0 0
T3 38319 0 0 0
T8 0 11 0 0
T9 0 4 0 0
T14 719 4 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T25 494 0 0 0
T27 522 0 0 0
T55 0 3 0 0
T56 0 4 0 0
T57 0 3 0 0
T58 0 5 0 0
T60 0 4 0 0
T61 0 12 0 0
T62 0 5 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1456 0 0
T2 222286 0 0 0
T3 613112 0 0 0
T8 0 11 0 0
T9 0 4 0 0
T14 345429 4 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T55 0 3 0 0
T56 0 4 0 0
T57 0 3 0 0
T58 0 5 0 0
T60 0 4 0 0
T61 0 12 0 0
T62 0 5 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT14,T8,T9
10CoveredT14,T8,T9
11CoveredT14,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT14,T8,T9
10CoveredT14,T8,T9
11CoveredT14,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1449 0 0
SrcPulseCheck_M 9202852 1450 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1449 0 0
T2 222286 0 0 0
T3 613112 0 0 0
T8 0 11 0 0
T9 0 4 0 0
T14 345429 4 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T55 0 3 0 0
T56 0 4 0 0
T57 0 3 0 0
T58 0 5 0 0
T60 0 4 0 0
T61 0 12 0 0
T62 0 5 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1450 0 0
T2 788 0 0 0
T3 38319 0 0 0
T8 0 11 0 0
T9 0 4 0 0
T14 719 4 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T25 494 0 0 0
T27 522 0 0 0
T55 0 3 0 0
T56 0 4 0 0
T57 0 3 0 0
T58 0 5 0 0
T60 0 4 0 0
T61 0 12 0 0
T62 0 5 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT14,T8,T9
10CoveredT14,T8,T9
11CoveredT14,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT14,T8,T9
10CoveredT14,T8,T9
11CoveredT14,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1249 0 0
SrcPulseCheck_M 1244620364 1296 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1249 0 0
T2 788 0 0 0
T3 38319 0 0 0
T8 0 5 0 0
T9 0 3 0 0
T14 719 3 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T25 494 0 0 0
T27 522 0 0 0
T55 0 3 0 0
T56 0 3 0 0
T57 0 3 0 0
T58 0 3 0 0
T60 0 3 0 0
T61 0 9 0 0
T62 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1296 0 0
T2 222286 0 0 0
T3 613112 0 0 0
T8 0 5 0 0
T9 0 3 0 0
T14 345429 3 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T55 0 3 0 0
T56 0 3 0 0
T57 0 3 0 0
T58 0 3 0 0
T60 0 3 0 0
T61 0 9 0 0
T62 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT14,T8,T9
10CoveredT14,T8,T9
11CoveredT14,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT14,T8,T9
10CoveredT14,T8,T9
11CoveredT14,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1288 0 0
SrcPulseCheck_M 9202852 1288 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1288 0 0
T2 222286 0 0 0
T3 613112 0 0 0
T8 0 5 0 0
T9 0 3 0 0
T14 345429 3 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T19 125626 0 0 0
T25 91348 0 0 0
T27 250961 0 0 0
T55 0 3 0 0
T56 0 3 0 0
T57 0 3 0 0
T58 0 3 0 0
T60 0 3 0 0
T61 0 9 0 0
T62 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1288 0 0
T2 788 0 0 0
T3 38319 0 0 0
T8 0 5 0 0
T9 0 3 0 0
T14 719 3 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T19 523 0 0 0
T25 494 0 0 0
T27 522 0 0 0
T55 0 3 0 0
T56 0 3 0 0
T57 0 3 0 0
T58 0 3 0 0
T60 0 3 0 0
T61 0 9 0 0
T62 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 7072 0 0
SrcPulseCheck_M 1244620364 7123 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7072 0 0
T11 12088 74 0 0
T12 25979 0 0 0
T28 5016 51 0 0
T29 0 77 0 0
T52 0 82 0 0
T53 0 63 0 0
T54 0 69 0 0
T59 0 51 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 81 0 0
T86 0 61 0 0
T87 0 74 0 0
T88 432 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7123 0 0
T11 580225 74 0 0
T12 649501 0 0 0
T28 248278 51 0 0
T29 0 77 0 0
T52 0 82 0 0
T53 0 63 0 0
T54 0 69 0 0
T59 0 51 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 81 0 0
T86 0 61 0 0
T87 0 74 0 0
T88 17267 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 7115 0 0
SrcPulseCheck_M 9202852 7116 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7115 0 0
T11 580225 74 0 0
T12 649501 0 0 0
T28 248278 51 0 0
T29 0 77 0 0
T52 0 82 0 0
T53 0 63 0 0
T54 0 69 0 0
T59 0 51 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 81 0 0
T86 0 61 0 0
T87 0 74 0 0
T88 17267 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7116 0 0
T11 12088 74 0 0
T12 25979 0 0 0
T28 5016 51 0 0
T29 0 77 0 0
T52 0 82 0 0
T53 0 63 0 0
T54 0 69 0 0
T59 0 51 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 81 0 0
T86 0 61 0 0
T87 0 74 0 0
T88 432 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 6880 0 0
SrcPulseCheck_M 1244620364 6930 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 6880 0 0
T11 12088 72 0 0
T12 25979 0 0 0
T28 5016 51 0 0
T29 0 77 0 0
T52 0 67 0 0
T53 0 65 0 0
T54 0 59 0 0
T59 0 51 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 60 0 0
T86 0 76 0 0
T87 0 92 0 0
T88 432 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 6930 0 0
T11 580225 72 0 0
T12 649501 0 0 0
T28 248278 51 0 0
T29 0 77 0 0
T52 0 67 0 0
T53 0 65 0 0
T54 0 59 0 0
T59 0 51 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 60 0 0
T86 0 76 0 0
T87 0 92 0 0
T88 17267 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 6922 0 0
SrcPulseCheck_M 9202852 6923 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 6922 0 0
T11 580225 72 0 0
T12 649501 0 0 0
T28 248278 51 0 0
T29 0 77 0 0
T52 0 67 0 0
T53 0 65 0 0
T54 0 59 0 0
T59 0 51 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 60 0 0
T86 0 76 0 0
T87 0 92 0 0
T88 17267 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 6923 0 0
T11 12088 72 0 0
T12 25979 0 0 0
T28 5016 51 0 0
T29 0 77 0 0
T52 0 67 0 0
T53 0 65 0 0
T54 0 59 0 0
T59 0 51 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 60 0 0
T86 0 76 0 0
T87 0 92 0 0
T88 432 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 7101 0 0
SrcPulseCheck_M 1244620364 7152 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7101 0 0
T11 12088 90 0 0
T12 25979 0 0 0
T28 5016 51 0 0
T29 0 63 0 0
T52 0 86 0 0
T53 0 80 0 0
T54 0 62 0 0
T59 0 51 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 71 0 0
T86 0 77 0 0
T87 0 92 0 0
T88 432 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7152 0 0
T11 580225 90 0 0
T12 649501 0 0 0
T28 248278 51 0 0
T29 0 63 0 0
T52 0 86 0 0
T53 0 80 0 0
T54 0 62 0 0
T59 0 51 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 71 0 0
T86 0 77 0 0
T87 0 92 0 0
T88 17267 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 7145 0 0
SrcPulseCheck_M 9202852 7145 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7145 0 0
T11 580225 90 0 0
T12 649501 0 0 0
T28 248278 51 0 0
T29 0 63 0 0
T52 0 86 0 0
T53 0 80 0 0
T54 0 62 0 0
T59 0 51 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 71 0 0
T86 0 77 0 0
T87 0 92 0 0
T88 17267 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7145 0 0
T11 12088 90 0 0
T12 25979 0 0 0
T28 5016 51 0 0
T29 0 63 0 0
T52 0 86 0 0
T53 0 80 0 0
T54 0 62 0 0
T59 0 51 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 71 0 0
T86 0 77 0 0
T87 0 92 0 0
T88 432 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 6960 0 0
SrcPulseCheck_M 1244620364 7013 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 6960 0 0
T11 12088 72 0 0
T12 25979 0 0 0
T28 5016 51 0 0
T29 0 62 0 0
T52 0 73 0 0
T53 0 75 0 0
T54 0 60 0 0
T59 0 51 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 67 0 0
T86 0 61 0 0
T87 0 65 0 0
T88 432 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7013 0 0
T11 580225 72 0 0
T12 649501 0 0 0
T28 248278 51 0 0
T29 0 62 0 0
T52 0 73 0 0
T53 0 75 0 0
T54 0 60 0 0
T59 0 51 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 68 0 0
T86 0 61 0 0
T87 0 65 0 0
T88 17267 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 7003 0 0
SrcPulseCheck_M 9202852 7003 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7003 0 0
T11 580225 72 0 0
T12 649501 0 0 0
T28 248278 51 0 0
T29 0 62 0 0
T52 0 73 0 0
T53 0 75 0 0
T54 0 60 0 0
T59 0 51 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 68 0 0
T86 0 61 0 0
T87 0 65 0 0
T88 17267 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7003 0 0
T11 12088 72 0 0
T12 25979 0 0 0
T28 5016 51 0 0
T29 0 62 0 0
T52 0 73 0 0
T53 0 75 0 0
T54 0 60 0 0
T59 0 51 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 68 0 0
T86 0 61 0 0
T87 0 65 0 0
T88 432 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT69,T116,T20
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1301 0 0
SrcPulseCheck_M 1244620364 1348 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1301 0 0
T11 12088 2 0 0
T12 25979 0 0 0
T28 5016 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 432 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1348 0 0
T11 580225 2 0 0
T12 649501 0 0 0
T28 248278 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 17267 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT69,T116,T20
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1339 0 0
SrcPulseCheck_M 9202852 1340 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1339 0 0
T11 580225 2 0 0
T12 649501 0 0 0
T28 248278 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 17267 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1340 0 0
T11 12088 2 0 0
T12 25979 0 0 0
T28 5016 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 432 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT69,T116,T20
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1268 0 0
SrcPulseCheck_M 1244620364 1318 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1268 0 0
T11 12088 2 0 0
T12 25979 0 0 0
T28 5016 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 432 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1318 0 0
T11 580225 2 0 0
T12 649501 0 0 0
T28 248278 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 17267 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT69,T116,T20
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1311 0 0
SrcPulseCheck_M 9202852 1311 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1311 0 0
T11 580225 2 0 0
T12 649501 0 0 0
T28 248278 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 17267 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1311 0 0
T11 12088 2 0 0
T12 25979 0 0 0
T28 5016 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 432 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT69,T116,T20
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1306 0 0
SrcPulseCheck_M 1244620364 1357 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1306 0 0
T11 12088 2 0 0
T12 25979 0 0 0
T28 5016 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 432 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1357 0 0
T11 580225 2 0 0
T12 649501 0 0 0
T28 248278 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 17267 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT69,T116,T20
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1349 0 0
SrcPulseCheck_M 9202852 1349 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1349 0 0
T11 580225 2 0 0
T12 649501 0 0 0
T28 248278 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 17267 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1349 0 0
T11 12088 2 0 0
T12 25979 0 0 0
T28 5016 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 432 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT69,T116,T20
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1289 0 0
SrcPulseCheck_M 1244620364 1337 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1289 0 0
T11 12088 2 0 0
T12 25979 0 0 0
T28 5016 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 432 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1337 0 0
T11 580225 2 0 0
T12 649501 0 0 0
T28 248278 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 17267 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT28,T11,T29
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT28,T11,T29
10CoveredT69,T116,T20
11CoveredT28,T11,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1328 0 0
SrcPulseCheck_M 9202852 1328 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1328 0 0
T11 580225 2 0 0
T12 649501 0 0 0
T28 248278 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 22696 0 0 0
T64 57854 0 0 0
T65 260928 0 0 0
T66 234746 0 0 0
T67 117623 0 0 0
T68 258684 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 17267 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1328 0 0
T11 12088 2 0 0
T12 25979 0 0 0
T28 5016 1 0 0
T29 0 2 0 0
T52 0 2 0 0
T53 0 1 0 0
T54 0 5 0 0
T59 0 1 0 0
T63 412 0 0 0
T64 526 0 0 0
T65 521 0 0 0
T66 494 0 0 0
T67 904 0 0 0
T68 522 0 0 0
T85 0 2 0 0
T86 0 8 0 0
T87 0 7 0 0
T88 432 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT28,T11,T29
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 7715 0 0
SrcPulseCheck_M 1244620364 7766 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7715 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 74 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 51 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7766 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 74 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 51 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT28,T11,T29
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 7758 0 0
SrcPulseCheck_M 9202852 7758 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7758 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 74 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 51 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7758 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 74 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 51 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT28,T11,T29
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 7468 0 0
SrcPulseCheck_M 1244620364 7517 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7468 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 72 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 51 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7517 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 72 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 51 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT28,T11,T29
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 7509 0 0
SrcPulseCheck_M 9202852 7509 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7509 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 72 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 51 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7509 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 72 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 51 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT28,T11,T29
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 7711 0 0
SrcPulseCheck_M 1244620364 7761 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7711 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 90 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 51 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7761 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 90 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 51 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT28,T11,T29
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 7752 0 0
SrcPulseCheck_M 9202852 7752 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7752 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 90 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 51 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7752 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 90 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 51 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT28,T11,T29
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 7555 0 0
SrcPulseCheck_M 1244620364 7609 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7555 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 72 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 51 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7609 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 72 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 51 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT28,T11,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT28,T11,T29
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 7600 0 0
SrcPulseCheck_M 9202852 7600 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 7600 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 72 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 51 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 7600 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 72 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 51 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1955 0 0
SrcPulseCheck_M 1244620364 2005 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1955 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 2005 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1996 0 0
SrcPulseCheck_M 9202852 1997 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1996 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1997 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1902 0 0
SrcPulseCheck_M 1244620364 1947 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1902 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1947 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1939 0 0
SrcPulseCheck_M 9202852 1939 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1939 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1939 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1895 0 0
SrcPulseCheck_M 1244620364 1941 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1895 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1941 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1932 0 0
SrcPulseCheck_M 9202852 1933 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1932 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1933 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1882 0 0
SrcPulseCheck_M 1244620364 1931 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1882 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1931 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1921 0 0
SrcPulseCheck_M 9202852 1922 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1921 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1922 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T32
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1932 0 0
SrcPulseCheck_M 1244620364 1982 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1932 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1982 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T32
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1974 0 0
SrcPulseCheck_M 9202852 1974 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1974 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1974 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 17 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1922 0 0
SrcPulseCheck_M 1244620364 1968 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1922 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1968 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1960 0 0
SrcPulseCheck_M 9202852 1960 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1960 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1960 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1852 0 0
SrcPulseCheck_M 1244620364 1898 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1852 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1898 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1891 0 0
SrcPulseCheck_M 9202852 1891 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1891 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1891 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9202852 1924 0 0
SrcPulseCheck_M 1244620364 1974 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1924 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1974 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT5,T1,T3
11CoveredT69,T116,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT5,T1,T3
10CoveredT69,T116,T20
11CoveredT5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T1
0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1244620364 1964 0 0
SrcPulseCheck_M 9202852 1964 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1244620364 1964 0 0
T1 223838 2 0 0
T2 222286 0 0 0
T3 613112 17 0 0
T5 462207 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 185448 0 0 0
T14 345429 0 0 0
T15 98950 0 0 0
T16 53327 0 0 0
T17 49910 0 0 0
T18 98968 0 0 0
T28 0 1 0 0
T36 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9202852 1964 0 0
T1 8953 2 0 0
T2 788 0 0 0
T3 38319 17 0 0
T5 38517 16 0 0
T8 0 2 0 0
T9 0 3 0 0
T10 0 14 0 0
T11 0 2 0 0
T12 0 11 0 0
T13 402 0 0 0
T14 719 0 0 0
T15 2162 0 0 0
T16 426 0 0 0
T17 454 0 0 0
T18 404 0 0 0
T28 0 1 0 0
T36 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%