Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T23 |
9 |
|
T24 |
6 |
|
T22 |
8 |
| auto[1] |
881 |
1 |
|
|
T23 |
11 |
|
T24 |
14 |
|
T22 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T23 |
10 |
|
T24 |
13 |
|
T22 |
8 |
| auto[1] |
825 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T22 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
910 |
1 |
|
|
T23 |
11 |
|
T24 |
10 |
|
T22 |
8 |
| auto[1] |
810 |
1 |
|
|
T23 |
9 |
|
T24 |
10 |
|
T22 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T23 |
10 |
|
T24 |
12 |
|
T22 |
11 |
| auto[1] |
854 |
1 |
|
|
T23 |
10 |
|
T24 |
8 |
|
T22 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T23 |
5 |
|
T24 |
10 |
|
T22 |
10 |
| auto[1] |
862 |
1 |
|
|
T23 |
15 |
|
T24 |
10 |
|
T22 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T23 |
10 |
|
T24 |
11 |
|
T22 |
10 |
| auto[1] |
822 |
1 |
|
|
T23 |
10 |
|
T24 |
9 |
|
T22 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T23 |
10 |
|
T24 |
10 |
|
T22 |
11 |
| auto[1] |
844 |
1 |
|
|
T23 |
10 |
|
T24 |
10 |
|
T22 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
865 |
1 |
|
|
T23 |
8 |
|
T24 |
11 |
|
T22 |
8 |
| auto[1] |
855 |
1 |
|
|
T23 |
12 |
|
T24 |
9 |
|
T22 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T23 |
13 |
|
T24 |
11 |
|
T22 |
6 |
| auto[1] |
887 |
1 |
|
|
T23 |
7 |
|
T24 |
9 |
|
T22 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T23 |
12 |
|
T24 |
11 |
|
T22 |
13 |
| auto[1] |
825 |
1 |
|
|
T23 |
8 |
|
T24 |
9 |
|
T22 |
7 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T23 |
6 |
|
T24 |
13 |
|
T22 |
12 |
| auto[1] |
825 |
1 |
|
|
T23 |
14 |
|
T24 |
7 |
|
T22 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T23 |
11 |
|
T24 |
12 |
|
T22 |
11 |
| auto[1] |
842 |
1 |
|
|
T23 |
9 |
|
T24 |
8 |
|
T22 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
863 |
1 |
|
|
T23 |
8 |
|
T24 |
8 |
|
T22 |
10 |
| auto[1] |
857 |
1 |
|
|
T23 |
12 |
|
T24 |
12 |
|
T22 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T23 |
10 |
|
T24 |
13 |
|
T22 |
8 |
| auto[1] |
825 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T22 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T23 |
5 |
|
T24 |
11 |
|
T22 |
10 |
| auto[1] |
875 |
1 |
|
|
T23 |
15 |
|
T24 |
9 |
|
T22 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T23 |
12 |
|
T24 |
11 |
|
T22 |
7 |
| auto[1] |
823 |
1 |
|
|
T23 |
8 |
|
T24 |
9 |
|
T22 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
819 |
1 |
|
|
T23 |
6 |
|
T24 |
8 |
|
T22 |
8 |
| auto[1] |
901 |
1 |
|
|
T23 |
14 |
|
T24 |
12 |
|
T22 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T23 |
11 |
|
T24 |
11 |
|
T22 |
12 |
| auto[1] |
835 |
1 |
|
|
T23 |
9 |
|
T24 |
9 |
|
T22 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T23 |
11 |
|
T24 |
11 |
|
T22 |
8 |
| auto[1] |
838 |
1 |
|
|
T23 |
9 |
|
T24 |
9 |
|
T22 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T23 |
11 |
|
T24 |
10 |
|
T22 |
9 |
| auto[1] |
835 |
1 |
|
|
T23 |
9 |
|
T24 |
10 |
|
T22 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T23 |
12 |
|
T24 |
7 |
|
T22 |
12 |
| auto[1] |
848 |
1 |
|
|
T23 |
8 |
|
T24 |
13 |
|
T22 |
8 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T23 |
7 |
|
T24 |
8 |
|
T22 |
14 |
| auto[1] |
890 |
1 |
|
|
T23 |
13 |
|
T24 |
12 |
|
T22 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T23 |
9 |
|
T24 |
10 |
|
T22 |
11 |
| auto[1] |
880 |
1 |
|
|
T23 |
11 |
|
T24 |
10 |
|
T22 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T23 |
11 |
|
T24 |
12 |
|
T22 |
11 |
| auto[1] |
842 |
1 |
|
|
T23 |
9 |
|
T24 |
8 |
|
T22 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T23 |
3 |
|
T24 |
6 |
|
T22 |
5 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T23 |
2 |
|
T24 |
5 |
|
T22 |
5 |
| auto[1] |
auto[0] |
485 |
1 |
|
|
T23 |
8 |
|
T24 |
4 |
|
T22 |
3 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T22 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
429 |
1 |
|
|
T23 |
6 |
|
T24 |
7 |
|
T22 |
5 |
| auto[0] |
auto[1] |
468 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T22 |
2 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T23 |
4 |
|
T24 |
5 |
|
T22 |
6 |
| auto[1] |
auto[1] |
386 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T22 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
421 |
1 |
|
|
T24 |
4 |
|
T22 |
3 |
|
T62 |
3 |
| auto[0] |
auto[1] |
398 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T22 |
5 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T22 |
7 |
| auto[1] |
auto[1] |
464 |
1 |
|
|
T23 |
9 |
|
T24 |
6 |
|
T22 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
474 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T22 |
5 |
| auto[0] |
auto[1] |
411 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T22 |
7 |
| auto[1] |
auto[0] |
424 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T22 |
5 |
| auto[1] |
auto[1] |
411 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T22 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
452 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T22 |
5 |
| auto[0] |
auto[1] |
430 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T22 |
3 |
| auto[1] |
auto[0] |
424 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T22 |
6 |
| auto[1] |
auto[1] |
414 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T22 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
448 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T22 |
4 |
| auto[0] |
auto[1] |
437 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T22 |
5 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T23 |
3 |
|
T24 |
5 |
|
T22 |
4 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T22 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T22 |
11 |
| auto[0] |
auto[1] |
393 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T22 |
3 |
| auto[1] |
auto[0] |
458 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T22 |
2 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T22 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T23 |
3 |
|
T24 |
7 |
|
T22 |
9 |
| auto[0] |
auto[1] |
398 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T22 |
2 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T23 |
3 |
|
T24 |
6 |
|
T22 |
3 |
| auto[1] |
auto[1] |
427 |
1 |
|
|
T23 |
8 |
|
T24 |
4 |
|
T22 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T23 |
5 |
|
T24 |
3 |
|
T22 |
5 |
| auto[0] |
auto[1] |
444 |
1 |
|
|
T23 |
3 |
|
T24 |
5 |
|
T22 |
5 |
| auto[1] |
auto[0] |
420 |
1 |
|
|
T23 |
4 |
|
T24 |
3 |
|
T22 |
3 |
| auto[1] |
auto[1] |
437 |
1 |
|
|
T23 |
8 |
|
T24 |
9 |
|
T22 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
895 |
1 |
|
|
T23 |
10 |
|
T24 |
13 |
|
T22 |
8 |
| auto[1] |
auto[1] |
825 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T22 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T23 |
8 |
|
T24 |
3 |
|
T22 |
4 |
| auto[0] |
auto[1] |
442 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T22 |
8 |
| auto[1] |
auto[0] |
403 |
1 |
|
|
T23 |
5 |
|
T24 |
8 |
|
T22 |
2 |
| auto[1] |
auto[1] |
445 |
1 |
|
|
T23 |
3 |
|
T24 |
5 |
|
T22 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
878 |
1 |
|
|
T23 |
11 |
|
T24 |
12 |
|
T22 |
11 |
| auto[1] |
auto[1] |
842 |
1 |
|
|
T23 |
9 |
|
T24 |
8 |
|
T22 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T65 |
8 |
|
T77 |
11 |
|
T181 |
8 |
| auto[1] |
133 |
1 |
|
|
T65 |
12 |
|
T77 |
9 |
|
T181 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T65 |
10 |
|
T77 |
7 |
|
T181 |
12 |
| auto[1] |
144 |
1 |
|
|
T65 |
10 |
|
T77 |
13 |
|
T181 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T65 |
13 |
|
T77 |
15 |
|
T181 |
11 |
| auto[1] |
133 |
1 |
|
|
T65 |
7 |
|
T77 |
5 |
|
T181 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T65 |
10 |
|
T77 |
9 |
|
T181 |
9 |
| auto[1] |
150 |
1 |
|
|
T65 |
10 |
|
T77 |
11 |
|
T181 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T65 |
9 |
|
T77 |
11 |
|
T181 |
10 |
| auto[1] |
148 |
1 |
|
|
T65 |
11 |
|
T77 |
9 |
|
T181 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T65 |
6 |
|
T77 |
7 |
|
T181 |
10 |
| auto[1] |
158 |
1 |
|
|
T65 |
14 |
|
T77 |
13 |
|
T181 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
160 |
1 |
|
|
T65 |
8 |
|
T77 |
11 |
|
T181 |
12 |
| auto[1] |
120 |
1 |
|
|
T65 |
12 |
|
T77 |
9 |
|
T181 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T65 |
13 |
|
T77 |
7 |
|
T181 |
7 |
| auto[1] |
144 |
1 |
|
|
T65 |
7 |
|
T77 |
13 |
|
T181 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T65 |
6 |
|
T77 |
11 |
|
T181 |
10 |
| auto[1] |
131 |
1 |
|
|
T65 |
14 |
|
T77 |
9 |
|
T181 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T65 |
10 |
|
T77 |
13 |
|
T181 |
10 |
| auto[1] |
133 |
1 |
|
|
T65 |
10 |
|
T77 |
7 |
|
T181 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T65 |
10 |
|
T77 |
12 |
|
T181 |
9 |
| auto[1] |
129 |
1 |
|
|
T65 |
10 |
|
T77 |
8 |
|
T181 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T65 |
9 |
|
T77 |
8 |
|
T181 |
10 |
| auto[1] |
148 |
1 |
|
|
T65 |
11 |
|
T77 |
12 |
|
T181 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T65 |
8 |
|
T77 |
11 |
|
T181 |
5 |
| auto[1] |
145 |
1 |
|
|
T65 |
12 |
|
T77 |
9 |
|
T181 |
15 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T65 |
10 |
|
T77 |
7 |
|
T181 |
12 |
| auto[1] |
144 |
1 |
|
|
T65 |
10 |
|
T77 |
13 |
|
T181 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T65 |
11 |
|
T77 |
10 |
|
T181 |
12 |
| auto[1] |
148 |
1 |
|
|
T65 |
9 |
|
T77 |
10 |
|
T181 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T65 |
14 |
|
T77 |
8 |
|
T181 |
12 |
| auto[1] |
149 |
1 |
|
|
T65 |
6 |
|
T77 |
12 |
|
T181 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T65 |
11 |
|
T77 |
11 |
|
T181 |
11 |
| auto[1] |
127 |
1 |
|
|
T65 |
9 |
|
T77 |
9 |
|
T181 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T65 |
12 |
|
T77 |
11 |
|
T181 |
9 |
| auto[1] |
135 |
1 |
|
|
T65 |
8 |
|
T77 |
9 |
|
T181 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T65 |
8 |
|
T77 |
10 |
|
T181 |
8 |
| auto[1] |
138 |
1 |
|
|
T65 |
12 |
|
T77 |
10 |
|
T181 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T65 |
9 |
|
T77 |
10 |
|
T181 |
9 |
| auto[1] |
126 |
1 |
|
|
T65 |
11 |
|
T77 |
10 |
|
T181 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T65 |
13 |
|
T77 |
15 |
|
T181 |
8 |
| auto[1] |
130 |
1 |
|
|
T65 |
7 |
|
T77 |
5 |
|
T181 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T65 |
14 |
|
T77 |
11 |
|
T181 |
12 |
| auto[1] |
132 |
1 |
|
|
T65 |
6 |
|
T77 |
9 |
|
T181 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T65 |
6 |
|
T77 |
8 |
|
T181 |
9 |
| auto[1] |
142 |
1 |
|
|
T65 |
14 |
|
T77 |
12 |
|
T181 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T65 |
9 |
|
T77 |
8 |
|
T181 |
10 |
| auto[1] |
148 |
1 |
|
|
T65 |
11 |
|
T77 |
12 |
|
T181 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
80 |
1 |
|
|
T65 |
7 |
|
T77 |
8 |
|
T181 |
7 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T65 |
4 |
|
T77 |
2 |
|
T181 |
5 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T65 |
6 |
|
T77 |
7 |
|
T181 |
4 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T65 |
3 |
|
T77 |
3 |
|
T181 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T65 |
7 |
|
T77 |
4 |
|
T181 |
6 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T65 |
7 |
|
T77 |
4 |
|
T181 |
6 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T65 |
3 |
|
T77 |
5 |
|
T181 |
3 |
| auto[1] |
auto[1] |
90 |
1 |
|
|
T65 |
3 |
|
T77 |
7 |
|
T181 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T65 |
6 |
|
T77 |
6 |
|
T181 |
7 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T65 |
5 |
|
T77 |
5 |
|
T181 |
4 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T65 |
3 |
|
T77 |
5 |
|
T181 |
3 |
| auto[1] |
auto[1] |
65 |
1 |
|
|
T65 |
6 |
|
T77 |
4 |
|
T181 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T65 |
5 |
|
T77 |
4 |
|
T181 |
6 |
| auto[0] |
auto[1] |
84 |
1 |
|
|
T65 |
7 |
|
T77 |
7 |
|
T181 |
3 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T65 |
1 |
|
T77 |
3 |
|
T181 |
4 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T65 |
7 |
|
T77 |
6 |
|
T181 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T65 |
3 |
|
T77 |
6 |
|
T181 |
4 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T65 |
5 |
|
T77 |
4 |
|
T181 |
4 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T65 |
5 |
|
T77 |
5 |
|
T181 |
8 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T65 |
7 |
|
T77 |
5 |
|
T181 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
78 |
1 |
|
|
T65 |
6 |
|
T77 |
4 |
|
T181 |
2 |
| auto[0] |
auto[1] |
76 |
1 |
|
|
T65 |
3 |
|
T77 |
6 |
|
T181 |
7 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T65 |
7 |
|
T77 |
3 |
|
T181 |
5 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T65 |
4 |
|
T77 |
7 |
|
T181 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
75 |
1 |
|
|
T65 |
8 |
|
T77 |
6 |
|
T181 |
7 |
| auto[0] |
auto[1] |
73 |
1 |
|
|
T65 |
6 |
|
T77 |
5 |
|
T181 |
5 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T65 |
2 |
|
T77 |
7 |
|
T181 |
3 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T65 |
4 |
|
T77 |
2 |
|
T181 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T65 |
4 |
|
T77 |
4 |
|
T181 |
5 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T65 |
2 |
|
T77 |
4 |
|
T181 |
4 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T65 |
6 |
|
T77 |
8 |
|
T181 |
4 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T65 |
8 |
|
T77 |
4 |
|
T181 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
68 |
1 |
|
|
T65 |
4 |
|
T77 |
6 |
|
T181 |
1 |
| auto[0] |
auto[1] |
67 |
1 |
|
|
T65 |
4 |
|
T77 |
5 |
|
T181 |
4 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T65 |
4 |
|
T77 |
5 |
|
T181 |
7 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T65 |
8 |
|
T77 |
4 |
|
T181 |
8 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
136 |
1 |
|
|
T65 |
10 |
|
T77 |
7 |
|
T181 |
12 |
| auto[1] |
auto[1] |
144 |
1 |
|
|
T65 |
10 |
|
T77 |
13 |
|
T181 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
77 |
1 |
|
|
T65 |
4 |
|
T77 |
8 |
|
T181 |
3 |
| auto[0] |
auto[1] |
73 |
1 |
|
|
T65 |
9 |
|
T77 |
7 |
|
T181 |
5 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T65 |
2 |
|
T77 |
3 |
|
T181 |
7 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T65 |
5 |
|
T77 |
2 |
|
T181 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
132 |
1 |
|
|
T65 |
9 |
|
T77 |
8 |
|
T181 |
10 |
| auto[1] |
auto[1] |
148 |
1 |
|
|
T65 |
11 |
|
T77 |
12 |
|
T181 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
31 |
1 |
|
|
T91 |
7 |
|
T165 |
14 |
|
T380 |
10 |
| auto[1] |
29 |
1 |
|
|
T91 |
13 |
|
T165 |
6 |
|
T380 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
28 |
1 |
|
|
T91 |
10 |
|
T165 |
9 |
|
T380 |
9 |
| auto[1] |
32 |
1 |
|
|
T91 |
10 |
|
T165 |
11 |
|
T380 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
28 |
1 |
|
|
T91 |
7 |
|
T165 |
11 |
|
T380 |
10 |
| auto[1] |
32 |
1 |
|
|
T91 |
13 |
|
T165 |
9 |
|
T380 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
23 |
1 |
|
|
T91 |
7 |
|
T165 |
8 |
|
T380 |
8 |
| auto[1] |
37 |
1 |
|
|
T91 |
13 |
|
T165 |
12 |
|
T380 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
30 |
1 |
|
|
T91 |
11 |
|
T165 |
10 |
|
T380 |
9 |
| auto[1] |
30 |
1 |
|
|
T91 |
9 |
|
T165 |
10 |
|
T380 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
28 |
1 |
|
|
T91 |
12 |
|
T165 |
10 |
|
T380 |
6 |
| auto[1] |
32 |
1 |
|
|
T91 |
8 |
|
T165 |
10 |
|
T380 |
14 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
25 |
1 |
|
|
T91 |
12 |
|
T165 |
5 |
|
T380 |
8 |
| auto[1] |
35 |
1 |
|
|
T91 |
8 |
|
T165 |
15 |
|
T380 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T91 |
10 |
|
T165 |
11 |
|
T380 |
8 |
| auto[1] |
31 |
1 |
|
|
T91 |
10 |
|
T165 |
9 |
|
T380 |
12 |