Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.25	99.42	96.83	100.00	98.72	98.85	99.81	94.08

Total tests in report: 915

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
52.52	52.52	72.07	72.07	59.07	59.07	83.56	83.56	5.13	5.13	74.01	74.01	57.42	57.42	16.41	16.41	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1033532391
64.69	12.17	84.83	12.76	76.37	17.29	88.13	4.57	19.23	14.10	84.95	10.94	73.99	16.57	25.34	8.93	/workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.471673038
75.73	11.04	90.24	5.41	80.99	4.63	88.13	0.00	60.26	41.03	89.72	4.77	87.57	13.58	33.23	7.89	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.4103939072
79.47	3.73	92.93	2.69	84.83	3.84	88.81	0.68	64.74	4.49	92.35	2.62	90.85	3.28	41.74	8.52	/workspace/coverage/default/41.sysrst_ctrl_stress_all.3559768444
83.11	3.64	95.88	2.95	89.11	4.27	89.27	0.46	71.79	7.05	95.75	3.40	92.87	2.02	47.09	5.35	/workspace/coverage/default/3.sysrst_ctrl_stress_all.1533925552
85.44	2.34	96.16	0.28	89.43	0.33	89.27	0.00	73.72	1.92	95.97	0.22	93.55	0.67	60.02	12.93	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.4110071748
87.44	1.99	97.20	1.04	90.98	1.54	89.27	0.00	83.97	10.26	97.08	1.11	93.55	0.00	60.02	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.2526443829
89.12	1.68	97.72	0.52	91.71	0.73	92.69	3.42	87.18	3.21	97.34	0.26	94.80	1.25	62.41	2.39	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1692043901
90.45	1.33	97.80	0.07	93.00	1.29	93.38	0.68	87.18	0.00	97.45	0.11	94.89	0.10	69.47	7.06	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2129408546
91.68	1.22	97.93	0.13	93.23	0.23	93.84	0.46	88.46	1.28	97.63	0.18	95.47	0.58	75.18	5.71	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.4039148591
92.57	0.90	97.98	0.06	93.48	0.25	99.32	5.48	88.46	0.00	97.63	0.00	95.76	0.29	75.39	0.21	/workspace/coverage/default/49.sysrst_ctrl_alert_test.1093834888
93.42	0.84	98.30	0.32	93.73	0.25	99.32	0.00	89.74	1.28	97.93	0.30	96.24	0.48	78.66	3.27	/workspace/coverage/default/10.sysrst_ctrl_stress_all.33539914
94.04	0.62	98.43	0.13	94.01	0.28	99.54	0.23	89.74	0.00	97.97	0.04	97.21	0.96	81.36	2.70	/workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2139951216
94.42	0.39	98.43	0.00	94.01	0.00	99.54	0.00	89.74	0.00	97.97	0.00	97.21	0.00	84.06	2.70	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.2029410380
94.79	0.37	98.56	0.13	94.08	0.08	99.54	0.00	91.67	1.92	98.11	0.15	97.50	0.29	84.06	0.00	/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1352892643
95.10	0.31	98.68	0.11	94.16	0.08	99.54	0.00	92.31	0.64	98.15	0.04	97.69	0.19	85.20	1.14	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3020628922
95.34	0.24	98.75	0.07	94.21	0.05	99.54	0.00	93.59	1.28	98.23	0.07	97.88	0.19	85.20	0.00	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3261273446
95.54	0.20	98.84	0.09	94.31	0.10	99.54	0.00	93.59	0.00	98.23	0.00	97.88	0.00	86.40	1.19	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3873505334
95.73	0.18	98.88	0.04	94.74	0.43	99.54	0.00	94.23	0.64	98.26	0.04	97.98	0.10	86.45	0.05	/workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.852655186
95.90	0.17	98.92	0.04	94.82	0.08	99.54	0.00	94.87	0.64	98.30	0.04	98.07	0.10	86.76	0.31	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4230345546
96.06	0.16	98.92	0.00	94.82	0.00	99.54	0.00	94.87	0.00	98.30	0.00	98.07	0.00	87.90	1.14	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.190140173
96.22	0.16	98.99	0.07	94.89	0.08	99.54	0.00	95.51	0.64	98.34	0.04	98.17	0.10	88.11	0.21	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3015830935
96.36	0.13	99.05	0.06	94.92	0.03	99.54	0.00	96.15	0.64	98.41	0.07	98.27	0.10	88.16	0.05	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1638268807
96.48	0.13	99.05	0.00	95.02	0.10	99.54	0.00	96.15	0.00	98.41	0.00	98.84	0.58	88.37	0.21	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2951830031
96.61	0.13	99.09	0.04	95.05	0.03	99.54	0.00	96.15	0.00	98.45	0.04	98.84	0.00	89.15	0.78	/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.4290232850
96.73	0.12	99.09	0.00	95.60	0.56	99.54	0.00	96.15	0.00	98.45	0.00	98.94	0.10	89.36	0.21	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3066231381
96.85	0.12	99.12	0.04	95.63	0.03	99.54	0.00	96.79	0.64	98.48	0.04	99.04	0.10	89.36	0.00	/workspace/coverage/default/29.sysrst_ctrl_edge_detect.3104011327
96.97	0.12	99.16	0.04	95.65	0.03	99.54	0.00	97.44	0.64	98.52	0.04	99.13	0.10	89.36	0.00	/workspace/coverage/default/32.sysrst_ctrl_edge_detect.3799458192
97.09	0.12	99.20	0.04	95.68	0.03	99.54	0.00	98.08	0.64	98.56	0.04	99.23	0.10	89.36	0.00	/workspace/coverage/default/37.sysrst_ctrl_edge_detect.4161820522
97.21	0.12	99.23	0.04	95.70	0.03	99.54	0.00	98.72	0.64	98.60	0.04	99.33	0.10	89.36	0.00	/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2604469858
97.31	0.10	99.27	0.04	95.70	0.00	99.54	0.00	98.72	0.00	98.60	0.00	99.33	0.00	90.03	0.67	/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.127999751
97.41	0.10	99.27	0.00	95.73	0.03	100.00	0.46	98.72	0.00	98.60	0.00	99.42	0.10	90.13	0.10	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.4174515827
97.48	0.07	99.29	0.02	95.73	0.00	100.00	0.00	98.72	0.00	98.60	0.00	99.42	0.00	90.60	0.47	/workspace/coverage/default/12.sysrst_ctrl_combo_detect.1010512982
97.55	0.07	99.29	0.00	95.73	0.00	100.00	0.00	98.72	0.00	98.60	0.00	99.42	0.00	91.07	0.47	/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3587338413
97.61	0.06	99.31	0.02	95.75	0.03	100.00	0.00	98.72	0.00	98.60	0.00	99.52	0.10	91.38	0.31	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3629002683
97.67	0.06	99.31	0.00	96.18	0.43	100.00	0.00	98.72	0.00	98.60	0.00	99.52	0.00	91.38	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.1890887572
97.73	0.05	99.31	0.00	96.41	0.23	100.00	0.00	98.72	0.00	98.60	0.00	99.61	0.10	91.43	0.05	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1946401778
97.78	0.05	99.31	0.00	96.41	0.00	100.00	0.00	98.72	0.00	98.60	0.00	99.61	0.00	91.80	0.36	/workspace/coverage/default/11.sysrst_ctrl_stress_all.1617814810
97.83	0.05	99.35	0.04	96.56	0.15	100.00	0.00	98.72	0.00	98.67	0.07	99.71	0.10	91.80	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3845176897
97.87	0.04	99.35	0.00	96.56	0.00	100.00	0.00	98.72	0.00	98.67	0.00	99.71	0.00	92.11	0.31	/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3824685526
97.90	0.03	99.35	0.00	96.56	0.00	100.00	0.00	98.72	0.00	98.67	0.00	99.71	0.00	92.32	0.21	/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.829767124
97.93	0.03	99.35	0.00	96.59	0.03	100.00	0.00	98.72	0.00	98.67	0.00	99.71	0.00	92.47	0.16	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3070448761
97.95	0.02	99.40	0.06	96.59	0.00	100.00	0.00	98.72	0.00	98.78	0.11	99.71	0.00	92.47	0.00	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3598079609
97.98	0.02	99.40	0.00	96.59	0.00	100.00	0.00	98.72	0.00	98.78	0.00	99.71	0.00	92.63	0.16	/workspace/coverage/default/25.sysrst_ctrl_stress_all.2490696593
98.00	0.02	99.40	0.00	96.59	0.00	100.00	0.00	98.72	0.00	98.78	0.00	99.71	0.00	92.78	0.16	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.880106745
98.02	0.02	99.40	0.00	96.59	0.00	100.00	0.00	98.72	0.00	98.78	0.00	99.71	0.00	92.94	0.16	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.1669141654
98.04	0.02	99.40	0.00	96.74	0.15	100.00	0.00	98.72	0.00	98.78	0.00	99.71	0.00	92.94	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.526460301
98.06	0.02	99.42	0.02	96.74	0.00	100.00	0.00	98.72	0.00	98.82	0.04	99.71	0.00	92.99	0.05	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3560202148
98.07	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.82	0.00	99.71	0.00	93.09	0.10	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.1586414561
98.09	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.82	0.00	99.71	0.00	93.20	0.10	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2940059102
98.10	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.82	0.00	99.71	0.00	93.30	0.10	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2057520766
98.12	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.82	0.00	99.71	0.00	93.41	0.10	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.445000622
98.13	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.82	0.00	99.71	0.00	93.51	0.10	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2229671788
98.14	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.82	0.00	99.81	0.10	93.51	0.00	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1213939265
98.16	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.04	99.81	0.00	93.56	0.05	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1574331088
98.16	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	93.61	0.05	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.4070173835
98.17	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	93.67	0.05	/workspace/coverage/default/2.sysrst_ctrl_stress_all.1956640790
98.18	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	93.72	0.05	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.3883207352
98.19	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	93.77	0.05	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1528779104
98.19	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	93.82	0.05	/workspace/coverage/default/40.sysrst_ctrl_combo_detect.1971991919
98.20	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	93.87	0.05	/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.4135505619
98.21	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	93.93	0.05	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.725891991
98.22	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	93.98	0.05	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4125770248
98.22	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	94.03	0.05	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4156100880
98.23	0.01	99.42	0.00	96.74	0.00	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	94.08	0.05	/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.805715600
98.24	0.01	99.42	0.00	96.76	0.03	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	94.08	0.00	/workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.4159616189
98.24	0.01	99.42	0.00	96.79	0.03	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	94.08	0.00	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1105737653
98.24	0.01	99.42	0.00	96.81	0.03	100.00	0.00	98.72	0.00	98.85	0.00	99.81	0.00	94.08	0.00	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1255673948

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2260344999
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4262178752
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.992796116
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2242535454
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.666533110
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.820986763
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4266264812
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2106811514
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2563233996
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3836684309
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1996218315
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3613690116
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2439044407
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.382643680
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.569585962
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3984249204
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2684328000
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2011941253
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3479804543
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3988384635
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2933001217
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2029028937
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.777462988
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1544110432
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4105691313
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2320062235
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3093302536
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2401951016
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1109101272
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1042045889
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.505658093
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2561199233
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3648914403
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1839870868
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2821142965
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1428953507
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.591251509
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1858926495
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2489581265
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4270002610
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2095508661
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1192838324
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2609907957
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3242608693
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3611718395
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3486444879
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2545006619
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/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3822900849
/workspace/coverage/default/4.sysrst_ctrl_combo_detect.1340193743
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3327752201
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.689075335
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2307381046
/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2343484262
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.1834862437
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1325109527
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2829169131
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2875204539
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.337317034
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.255305626
/workspace/coverage/default/4.sysrst_ctrl_smoke.669198514
/workspace/coverage/default/4.sysrst_ctrl_stress_all.1264534002
/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1798349114
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.636772565
/workspace/coverage/default/40.sysrst_ctrl_alert_test.2665095713
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2553786105
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.893636717
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.3231058083
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1341661551
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3428107814
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3043558558
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2738001914
/workspace/coverage/default/40.sysrst_ctrl_smoke.4108042618
/workspace/coverage/default/40.sysrst_ctrl_stress_all.2811802770
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3265490556
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3779095047
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3322614557
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.813748400
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.667890871
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.932183829
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.1016383773
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.970857407
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1360419158
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2565676919
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3478498610
/workspace/coverage/default/41.sysrst_ctrl_smoke.1903183192
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2245680973
/workspace/coverage/default/42.sysrst_ctrl_alert_test.2730880327
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3427939002
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2095755737
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1686070228
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2386208819
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2879443433
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4228469372
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3186132761
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3348298633
/workspace/coverage/default/42.sysrst_ctrl_smoke.2672577959
/workspace/coverage/default/42.sysrst_ctrl_stress_all.3020112832
/workspace/coverage/default/43.sysrst_ctrl_alert_test.706867224
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1170613917
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.913688281
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.4183538874
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1089189787
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3791749805
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.935929095
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1329887433
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1285019029
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.477485644
/workspace/coverage/default/43.sysrst_ctrl_smoke.2765747699
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3335549867
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3835966649
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3764644692
/workspace/coverage/default/44.sysrst_ctrl_alert_test.4027694227
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3728520870
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1867535631
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3845370622
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1503294086
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2827095571
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1961482919
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3200183043
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4139782107
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.580480770
/workspace/coverage/default/44.sysrst_ctrl_smoke.3584287268
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1492927597
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3314656949
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3540961837
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4103164202
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3700296334
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2464697176
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2075379537
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.115016141
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.647105539
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2463811750
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2748039400
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1109704717
/workspace/coverage/default/45.sysrst_ctrl_smoke.3464868958
/workspace/coverage/default/45.sysrst_ctrl_stress_all.691589304
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.372626727
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3944782856
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.4294167727
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2335734619
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3170236009
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3180066956
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3129083395
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1305519439
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2922021575
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1182005947
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3035786456
/workspace/coverage/default/46.sysrst_ctrl_smoke.2719333072
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3294221682
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.216005215
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3949014017
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2413057627
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.775554587
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2304757825
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.837743757
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.310806780
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2740342137
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3947654599
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2899119290
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.590601609
/workspace/coverage/default/47.sysrst_ctrl_smoke.775183661
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1790956657
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2902221892
/workspace/coverage/default/48.sysrst_ctrl_alert_test.554226619
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.118424836
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.557515776
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3983565237
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3471774554
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3974518005
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.4004081728
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2412530800
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.188530346
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.135651973
/workspace/coverage/default/48.sysrst_ctrl_smoke.539142061
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2700994689
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1787609553
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4109796435
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1721558056
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.2448637892
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.354593067
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3560917865
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2596016549
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3899934447
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3829965365
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3218366580
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1886817596
/workspace/coverage/default/49.sysrst_ctrl_smoke.1392209899
/workspace/coverage/default/49.sysrst_ctrl_stress_all.3746602951
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.201989612
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1355594409
/workspace/coverage/default/5.sysrst_ctrl_alert_test.2743010458
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3835600112
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.4291398486
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3662655173
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.473499499
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.834123161
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1753146508
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3682353790
/workspace/coverage/default/5.sysrst_ctrl_smoke.292962344
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3797092294
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2112535026
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1442645430
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2489178575
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.27141549
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1578525503
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1067873011
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1617843073
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3531279855
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2858838381
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1214622542
/workspace/coverage/default/6.sysrst_ctrl_alert_test.18357539
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1789146388
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.229786873
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1392205522
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1468061779
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.986379722
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.178014155
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1069071542
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2562676838
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2301094302
/workspace/coverage/default/6.sysrst_ctrl_smoke.3286129335
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1051337328
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1785120787
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2464634247
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.792202160
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1341151643
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3406482638
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.464708993
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3253290711
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3317409092
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.152616883
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3836103848
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3480505929
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1373748741
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3158695262
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.853240084
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2993396529
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1355457569
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.4011472658
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3208839483
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2010956728
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2365033235
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2941359649
/workspace/coverage/default/7.sysrst_ctrl_smoke.157979978
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3355257145
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1244041833
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3326410005
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1832533387
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.685118065
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.652659953
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4094901502
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3381690640
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2886286315
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2847219994
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1950225506
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.679055448
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2538214327
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3589094571
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1101386864
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2437019523
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2315261142
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3047274968
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.4094832317
/workspace/coverage/default/8.sysrst_ctrl_smoke.2018700310
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1167535474
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1918438359
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.300248389
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3077351496
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3049462695
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.384051520
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2774327634
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3147723475
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.178932085
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1695312650
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2413430763
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2402412505
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.3642109553
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1463145371
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1501549046
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2051623860
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3379026024
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2964249619
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3342617581
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3731803184
/workspace/coverage/default/9.sysrst_ctrl_smoke.2377099894
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2728581350
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.416641253
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1606358769
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1861046731
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3964358929
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3415523687
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.181438884
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3875787
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2773682390
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.483152259

Total test records in report: 915

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/28.sysrst_ctrl_stress_all.1491359323	May 26 01:10:37 PM PDT 24	May 26 01:10:52 PM PDT 24	11132927179 ps
T5	/workspace/coverage/default/12.sysrst_ctrl_alert_test.3650228624	May 26 01:10:13 PM PDT 24	May 26 01:10:20 PM PDT 24	2012692745 ps
T2	/workspace/coverage/default/20.sysrst_ctrl_edge_detect.2681179438	May 26 01:10:08 PM PDT 24	May 26 01:10:13 PM PDT 24	2676305728 ps
T12	/workspace/coverage/default/49.sysrst_ctrl_alert_test.1093834888	May 26 01:11:12 PM PDT 24	May 26 01:11:19 PM PDT 24	2012778440 ps
T13	/workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3699558832	May 26 01:10:31 PM PDT 24	May 26 01:10:38 PM PDT 24	3417211936 ps
T14	/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1281280701	May 26 01:10:41 PM PDT 24	May 26 01:10:48 PM PDT 24	5646926976 ps
T3	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1033532391	May 26 01:10:31 PM PDT 24	May 26 01:11:26 PM PDT 24	22308806174 ps
T15	/workspace/coverage/default/14.sysrst_ctrl_smoke.215575373	May 26 01:09:55 PM PDT 24	May 26 01:10:01 PM PDT 24	2119130191 ps
T16	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3868122137	May 26 01:10:17 PM PDT 24	May 26 01:10:33 PM PDT 24	4922538729 ps
T17	/workspace/coverage/default/36.sysrst_ctrl_smoke.217208252	May 26 01:10:42 PM PDT 24	May 26 01:10:48 PM PDT 24	2113255363 ps
T23	/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2463811750	May 26 01:10:59 PM PDT 24	May 26 01:11:07 PM PDT 24	2457676413 ps
T32	/workspace/coverage/default/18.sysrst_ctrl_stress_all.3148775796	May 26 01:10:10 PM PDT 24	May 26 01:10:23 PM PDT 24	13594341440 ps
T28	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1574331088	May 26 01:09:49 PM PDT 24	May 26 01:10:46 PM PDT 24	92917673162 ps
T4	/workspace/coverage/default/28.sysrst_ctrl_combo_detect.1215900445	May 26 01:10:31 PM PDT 24	May 26 01:16:46 PM PDT 24	141367195315 ps
T6	/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2538214327	May 26 01:09:55 PM PDT 24	May 26 01:11:12 PM PDT 24	104019237617 ps
T25	/workspace/coverage/default/22.sysrst_ctrl_stress_all.2581828206	May 26 01:10:18 PM PDT 24	May 26 01:10:27 PM PDT 24	18518028765 ps
T55	/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2748039400	May 26 01:11:04 PM PDT 24	May 26 01:11:11 PM PDT 24	2212568150 ps
T26	/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.935929095	May 26 01:10:54 PM PDT 24	May 26 01:10:59 PM PDT 24	2617857530 ps
T7	/workspace/coverage/default/23.sysrst_ctrl_stress_all.2142682202	May 26 01:10:20 PM PDT 24	May 26 01:12:45 PM PDT 24	109286833473 ps
T24	/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1988836551	May 26 01:10:13 PM PDT 24	May 26 01:10:16 PM PDT 24	2491255506 ps
T56	/workspace/coverage/default/30.sysrst_ctrl_smoke.3014414136	May 26 01:10:32 PM PDT 24	May 26 01:10:40 PM PDT 24	2114969863 ps
T48	/workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.760870082	May 26 01:10:42 PM PDT 24	May 26 01:10:53 PM PDT 24	3623486008 ps
T57	/workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.4257337050	May 26 01:10:32 PM PDT 24	May 26 01:10:41 PM PDT 24	2609163963 ps
T8	/workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.852655186	May 26 01:10:17 PM PDT 24	May 26 01:10:20 PM PDT 24	11446442062 ps
T60	/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3817626419	May 26 01:09:47 PM PDT 24	May 26 01:09:57 PM PDT 24	3155570281 ps
T9	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.2029410380	May 26 01:10:03 PM PDT 24	May 26 01:14:39 PM PDT 24	102721424781 ps
T29	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2929479402	May 26 01:09:33 PM PDT 24	May 26 01:11:13 PM PDT 24	38134363790 ps
T10	/workspace/coverage/default/11.sysrst_ctrl_combo_detect.1798570586	May 26 01:09:49 PM PDT 24	May 26 01:11:46 PM PDT 24	149310907471 ps
T81	/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1089189787	May 26 01:10:54 PM PDT 24	May 26 01:11:04 PM PDT 24	5443752556 ps
T11	/workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.471673038	May 26 01:10:42 PM PDT 24	May 26 01:13:26 PM PDT 24	61792868061 ps
T82	/workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1521773888	May 26 01:10:37 PM PDT 24	May 26 01:10:42 PM PDT 24	4957099174 ps
T45	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3020628922	May 26 01:10:20 PM PDT 24	May 26 01:12:25 PM PDT 24	161558410653 ps
T69	/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3731803184	May 26 01:10:02 PM PDT 24	May 26 01:10:08 PM PDT 24	2521791770 ps
T256	/workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.111036947	May 26 01:10:29 PM PDT 24	May 26 01:10:32 PM PDT 24	3811640387 ps
T257	/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2408686498	May 26 01:10:18 PM PDT 24	May 26 01:10:26 PM PDT 24	2901728735 ps
T49	/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.4290232850	May 26 01:10:41 PM PDT 24	May 26 01:10:45 PM PDT 24	3234061575 ps
T258	/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2343484262	May 26 01:09:54 PM PDT 24	May 26 01:10:08 PM PDT 24	4212338035 ps
T21	/workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2523434076	May 26 01:10:30 PM PDT 24	May 26 01:10:34 PM PDT 24	10703729140 ps
T22	/workspace/coverage/default/41.sysrst_ctrl_stress_all.3559768444	May 26 01:10:56 PM PDT 24	May 26 01:11:21 PM PDT 24	11489747663 ps
T33	/workspace/coverage/default/2.sysrst_ctrl_combo_detect.3046949887	May 26 01:09:48 PM PDT 24	May 26 01:13:30 PM PDT 24	87283729901 ps
T127	/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3667365721	May 26 01:10:10 PM PDT 24	May 26 01:10:17 PM PDT 24	2030881640 ps
T27	/workspace/coverage/default/36.sysrst_ctrl_edge_detect.3433412522	May 26 01:10:42 PM PDT 24	May 26 01:10:46 PM PDT 24	3866835290 ps
T47	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1067873011	May 26 01:11:11 PM PDT 24	May 26 01:15:20 PM PDT 24	162849148126 ps
T36	/workspace/coverage/default/13.sysrst_ctrl_stress_all.2692088216	May 26 01:10:01 PM PDT 24	May 26 01:10:33 PM PDT 24	1292612326386 ps
T34	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1392205522	May 26 01:09:39 PM PDT 24	May 26 01:13:22 PM PDT 24	88995287691 ps
T50	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3158695262	May 26 01:09:32 PM PDT 24	May 26 01:09:45 PM PDT 24	3438911549 ps
T46	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1692043901	May 26 01:11:15 PM PDT 24	May 26 01:13:39 PM PDT 24	112942124689 ps
T70	/workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3599279859	May 26 01:10:27 PM PDT 24	May 26 01:10:29 PM PDT 24	2740609550 ps
T186	/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3998527659	May 26 01:09:56 PM PDT 24	May 26 01:10:01 PM PDT 24	2234819772 ps
T61	/workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1233895433	May 26 01:10:44 PM PDT 24	May 26 01:11:13 PM PDT 24	11996725370 ps
T71	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2940059102	May 26 01:10:37 PM PDT 24	May 26 01:10:43 PM PDT 24	2518763492 ps
T72	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2437019523	May 26 01:09:45 PM PDT 24	May 26 01:09:48 PM PDT 24	2647291322 ps
T62	/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4228469372	May 26 01:11:05 PM PDT 24	May 26 01:11:13 PM PDT 24	2448249010 ps
T73	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2993396529	May 26 01:10:00 PM PDT 24	May 26 01:10:48 PM PDT 24	34382698718 ps
T384	/workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.4259680421	May 26 01:10:37 PM PDT 24	May 26 01:10:40 PM PDT 24	2620188797 ps
T76	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.553124848	May 26 01:10:08 PM PDT 24	May 26 01:11:12 PM PDT 24	24668055778 ps
T382	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3682353790	May 26 01:09:35 PM PDT 24	May 26 01:09:38 PM PDT 24	2576642529 ps
T126	/workspace/coverage/default/46.sysrst_ctrl_stress_all.3294221682	May 26 01:11:17 PM PDT 24	May 26 01:21:29 PM PDT 24	228497523370 ps
T35	/workspace/coverage/default/3.sysrst_ctrl_stress_all.1533925552	May 26 01:09:38 PM PDT 24	May 26 01:18:15 PM PDT 24	200583539071 ps
T111	/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1177082518	May 26 01:10:37 PM PDT 24	May 26 01:10:45 PM PDT 24	2510460675 ps
T112	/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.425212230	May 26 01:10:42 PM PDT 24	May 26 01:10:48 PM PDT 24	8287944331 ps
T37	/workspace/coverage/default/6.sysrst_ctrl_edge_detect.986379722	May 26 01:09:49 PM PDT 24	May 26 01:09:56 PM PDT 24	4475582520 ps
T113	/workspace/coverage/default/38.sysrst_ctrl_combo_detect.3805902350	May 26 01:10:44 PM PDT 24	May 26 01:16:38 PM PDT 24	129046514513 ps
T40	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.873417132	May 26 01:10:37 PM PDT 24	May 26 01:10:43 PM PDT 24	4701636390 ps
T114	/workspace/coverage/default/46.sysrst_ctrl_alert_test.3944782856	May 26 01:11:13 PM PDT 24	May 26 01:11:20 PM PDT 24	2009081094 ps
T115	/workspace/coverage/default/26.sysrst_ctrl_alert_test.3626620126	May 26 01:10:32 PM PDT 24	May 26 01:10:36 PM PDT 24	2041003598 ps
T116	/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2298807357	May 26 01:10:26 PM PDT 24	May 26 01:10:34 PM PDT 24	2508374805 ps
T63	/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2287980614	May 26 01:10:29 PM PDT 24	May 26 01:10:34 PM PDT 24	2466375833 ps
T227	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2738001914	May 26 01:10:44 PM PDT 24	May 26 01:10:47 PM PDT 24	2595255484 ps
T228	/workspace/coverage/default/15.sysrst_ctrl_alert_test.2428615519	May 26 01:09:53 PM PDT 24	May 26 01:10:00 PM PDT 24	2010276266 ps
T229	/workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1051662657	May 26 01:10:15 PM PDT 24	May 26 01:10:25 PM PDT 24	3485078823 ps
T74	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3317409092	May 26 01:11:13 PM PDT 24	May 26 01:11:31 PM PDT 24	25098133747 ps
T250	/workspace/coverage/default/25.sysrst_ctrl_alert_test.4250394589	May 26 01:10:19 PM PDT 24	May 26 01:10:22 PM PDT 24	2032750066 ps
T385	/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3560917865	May 26 01:11:20 PM PDT 24	May 26 01:11:35 PM PDT 24	4328292876 ps
T386	/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3342617581	May 26 01:10:16 PM PDT 24	May 26 01:10:21 PM PDT 24	2144567745 ps
T312	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1105737653	May 26 01:10:10 PM PDT 24	May 26 01:10:18 PM PDT 24	2511985824 ps
T387	/workspace/coverage/default/13.sysrst_ctrl_smoke.1098077684	May 26 01:10:04 PM PDT 24	May 26 01:10:08 PM PDT 24	2129869183 ps
T96	/workspace/coverage/default/48.sysrst_ctrl_combo_detect.557515776	May 26 01:11:10 PM PDT 24	May 26 01:13:33 PM PDT 24	109921543897 ps
T388	/workspace/coverage/default/35.sysrst_ctrl_smoke.518308674	May 26 01:10:41 PM PDT 24	May 26 01:10:44 PM PDT 24	2123827964 ps
T75	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1299586907	May 26 01:10:39 PM PDT 24	May 26 01:10:50 PM PDT 24	37589044763 ps
T51	/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2077550472	May 26 01:10:14 PM PDT 24	May 26 01:10:25 PM PDT 24	3647413178 ps
T389	/workspace/coverage/default/16.sysrst_ctrl_alert_test.4250345093	May 26 01:09:55 PM PDT 24	May 26 01:10:00 PM PDT 24	2051153211 ps
T52	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2402412505	May 26 01:09:58 PM PDT 24	May 26 01:10:10 PM PDT 24	3515680322 ps
T64	/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.834123161	May 26 01:09:33 PM PDT 24	May 26 01:09:43 PM PDT 24	2475496379 ps
T53	/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.295072220	May 26 01:10:37 PM PDT 24	May 26 01:10:43 PM PDT 24	3731159154 ps
T383	/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.799907240	May 26 01:10:51 PM PDT 24	May 26 01:10:53 PM PDT 24	2563575624 ps
T267	/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2095755737	May 26 01:10:51 PM PDT 24	May 26 01:11:22 PM PDT 24	64110947263 ps
T390	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1324247064	May 26 01:10:37 PM PDT 24	May 26 01:10:41 PM PDT 24	2632434765 ps
T65	/workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2139951216	May 26 01:09:50 PM PDT 24	May 26 01:10:50 PM PDT 24	104065869479 ps
T263	/workspace/coverage/default/12.sysrst_ctrl_combo_detect.1010512982	May 26 01:10:06 PM PDT 24	May 26 01:12:54 PM PDT 24	127787878826 ps
T66	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1497762835	May 26 01:10:15 PM PDT 24	May 26 01:10:20 PM PDT 24	2471522733 ps
T41	/workspace/coverage/default/26.sysrst_ctrl_edge_detect.3015751028	May 26 01:10:20 PM PDT 24	May 26 01:10:32 PM PDT 24	3900894692 ps
T304	/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1747889737	May 26 01:09:29 PM PDT 24	May 26 01:09:32 PM PDT 24	2624108157 ps
T97	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3234612147	May 26 01:10:10 PM PDT 24	May 26 01:10:31 PM PDT 24	26855362295 ps
T42	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2596016549	May 26 01:11:15 PM PDT 24	May 26 01:11:19 PM PDT 24	2600233048 ps
T305	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.647105539	May 26 01:10:57 PM PDT 24	May 26 01:11:00 PM PDT 24	2630331536 ps
T306	/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.674942907	May 26 01:09:53 PM PDT 24	May 26 01:09:58 PM PDT 24	2106556852 ps
T307	/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.881509807	May 26 01:09:52 PM PDT 24	May 26 01:09:57 PM PDT 24	4402281847 ps
T391	/workspace/coverage/default/19.sysrst_ctrl_smoke.4126624046	May 26 01:10:03 PM PDT 24	May 26 01:10:07 PM PDT 24	2129367863 ps
T275	/workspace/coverage/default/5.sysrst_ctrl_combo_detect.4291398486	May 26 01:09:40 PM PDT 24	May 26 01:10:43 PM PDT 24	141369114471 ps
T392	/workspace/coverage/default/2.sysrst_ctrl_alert_test.3166941228	May 26 01:09:52 PM PDT 24	May 26 01:09:56 PM PDT 24	2034076254 ps
T393	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.16270905	May 26 01:10:46 PM PDT 24	May 26 01:10:53 PM PDT 24	2118537691 ps
T94	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3677376214	May 26 01:10:36 PM PDT 24	May 26 01:11:18 PM PDT 24	57850786912 ps
T67	/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.306023572	May 26 01:09:56 PM PDT 24	May 26 01:10:00 PM PDT 24	2492340097 ps
T394	/workspace/coverage/default/16.sysrst_ctrl_smoke.4102572110	May 26 01:09:51 PM PDT 24	May 26 01:09:58 PM PDT 24	2110318266 ps
T98	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3765425108	May 26 01:09:49 PM PDT 24	May 26 01:10:07 PM PDT 24	24853311213 ps
T395	/workspace/coverage/default/48.sysrst_ctrl_smoke.539142061	May 26 01:10:59 PM PDT 24	May 26 01:11:03 PM PDT 24	2136949810 ps
T54	/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1721558056	May 26 01:11:09 PM PDT 24	May 26 01:11:11 PM PDT 24	3538561602 ps
T343	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.1586414561	May 26 01:10:30 PM PDT 24	May 26 01:10:48 PM PDT 24	58053957315 ps
T396	/workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3571831733	May 26 01:10:36 PM PDT 24	May 26 01:10:48 PM PDT 24	4079458775 ps
T315	/workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2979805584	May 26 01:10:30 PM PDT 24	May 26 01:10:45 PM PDT 24	1218300749436 ps
T68	/workspace/coverage/default/14.sysrst_ctrl_stress_all.3827733446	May 26 01:09:54 PM PDT 24	May 26 01:10:03 PM PDT 24	9213879825 ps
T397	/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2677374289	May 26 01:10:31 PM PDT 24	May 26 01:10:36 PM PDT 24	4258138015 ps
T398	/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3200183043	May 26 01:10:58 PM PDT 24	May 26 01:11:05 PM PDT 24	2467493356 ps
T86	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3873505334	May 26 01:11:16 PM PDT 24	May 26 01:17:45 PM PDT 24	165965280788 ps
T38	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3015830935	May 26 01:10:52 PM PDT 24	May 26 01:11:15 PM PDT 24	18660954290 ps
T201	/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2075379537	May 26 01:11:15 PM PDT 24	May 26 01:11:26 PM PDT 24	3669959235 ps
T202	/workspace/coverage/default/15.sysrst_ctrl_stress_all.3436198509	May 26 01:09:56 PM PDT 24	May 26 01:10:09 PM PDT 24	13863975349 ps
T155	/workspace/coverage/default/4.sysrst_ctrl_stress_all.1264534002	May 26 01:09:43 PM PDT 24	May 26 01:10:25 PM PDT 24	24429129269 ps
T203	/workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2758045503	May 26 01:10:56 PM PDT 24	May 26 01:11:04 PM PDT 24	2695714127 ps
T95	/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.4230557849	May 26 01:10:21 PM PDT 24	May 26 01:19:04 PM PDT 24	211903020125 ps
T77	/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.201989612	May 26 01:11:15 PM PDT 24	May 26 01:12:11 PM PDT 24	48390132021 ps
T204	/workspace/coverage/default/36.sysrst_ctrl_combo_detect.942476379	May 26 01:10:44 PM PDT 24	May 26 01:13:58 PM PDT 24	158341645764 ps
T44	/workspace/coverage/default/10.sysrst_ctrl_stress_all.33539914	May 26 01:10:00 PM PDT 24	May 26 01:12:04 PM PDT 24	97889290682 ps
T172	/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1957048741	May 26 01:10:37 PM PDT 24	May 26 01:10:46 PM PDT 24	2439649546 ps
T173	/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2879443433	May 26 01:10:52 PM PDT 24	May 26 01:11:01 PM PDT 24	2614851083 ps
T174	/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1386016366	May 26 01:10:32 PM PDT 24	May 26 01:10:41 PM PDT 24	2610288360 ps
T175	/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1443113106	May 26 01:10:29 PM PDT 24	May 26 01:10:37 PM PDT 24	2510277624 ps
T78	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3265490556	May 26 01:10:54 PM PDT 24	May 26 01:11:30 PM PDT 24	59615319397 ps
T99	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.3210203319	May 26 01:09:38 PM PDT 24	May 26 01:10:18 PM PDT 24	30450059310 ps
T176	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1753146508	May 26 01:09:40 PM PDT 24	May 26 01:09:50 PM PDT 24	2234723787 ps
T177	/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1329887433	May 26 01:10:51 PM PDT 24	May 26 01:10:59 PM PDT 24	2457309832 ps
T178	/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.4011500140	May 26 01:10:38 PM PDT 24	May 26 01:10:42 PM PDT 24	2531130181 ps
T79	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3662033904	May 26 01:10:15 PM PDT 24	May 26 01:10:37 PM PDT 24	85267259794 ps
T317	/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.94323224	May 26 01:10:35 PM PDT 24	May 26 01:10:38 PM PDT 24	2639727400 ps
T43	/workspace/coverage/default/35.sysrst_ctrl_edge_detect.1593061167	May 26 01:10:43 PM PDT 24	May 26 01:10:52 PM PDT 24	5583238274 ps
T318	/workspace/coverage/default/9.sysrst_ctrl_alert_test.2413430763	May 26 01:10:08 PM PDT 24	May 26 01:10:16 PM PDT 24	2010986922 ps
T277	/workspace/coverage/default/3.sysrst_ctrl_sec_cm.2099774832	May 26 01:09:38 PM PDT 24	May 26 01:10:41 PM PDT 24	22009686398 ps
T296	/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.473499499	May 26 01:09:54 PM PDT 24	May 26 01:09:58 PM PDT 24	2631180556 ps
T84	/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2886286315	May 26 01:11:06 PM PDT 24	May 26 01:11:56 PM PDT 24	36594623402 ps
T297	/workspace/coverage/default/2.sysrst_ctrl_pin_override_test.20015557	May 26 01:09:37 PM PDT 24	May 26 01:09:42 PM PDT 24	2542663489 ps
T298	/workspace/coverage/default/4.sysrst_ctrl_smoke.669198514	May 26 01:09:51 PM PDT 24	May 26 01:09:54 PM PDT 24	2135413930 ps
T299	/workspace/coverage/default/36.sysrst_ctrl_alert_test.870966088	May 26 01:10:53 PM PDT 24	May 26 01:10:56 PM PDT 24	2054496704 ps
T39	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2216349771	May 26 01:10:51 PM PDT 24	May 26 01:14:01 PM PDT 24	69762524614 ps
T300	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1341661551	May 26 01:10:42 PM PDT 24	May 26 01:10:49 PM PDT 24	2618247123 ps
T301	/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2315261142	May 26 01:10:05 PM PDT 24	May 26 01:10:14 PM PDT 24	2471140414 ps
T100	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.190140173	May 26 01:10:01 PM PDT 24	May 26 01:10:34 PM PDT 24	25189128252 ps
T90	/workspace/coverage/default/32.sysrst_ctrl_edge_detect.3799458192	May 26 01:10:37 PM PDT 24	May 26 01:10:43 PM PDT 24	3430775318 ps
T101	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3870750475	May 26 01:09:52 PM PDT 24	May 26 01:12:05 PM PDT 24	216128263101 ps
T239	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1606358769	May 26 01:11:20 PM PDT 24	May 26 01:12:10 PM PDT 24	34539393591 ps
T80	/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3764644692	May 26 01:10:54 PM PDT 24	May 26 01:11:03 PM PDT 24	6631784069 ps
T240	/workspace/coverage/default/3.sysrst_ctrl_alert_test.2136385457	May 26 01:09:36 PM PDT 24	May 26 01:09:44 PM PDT 24	2011882344 ps
T87	/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3779095047	May 26 01:10:46 PM PDT 24	May 26 01:10:54 PM PDT 24	4962359589 ps
T138	/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3427939002	May 26 01:10:54 PM PDT 24	May 26 01:10:58 PM PDT 24	3384060068 ps
T139	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3700296334	May 26 01:11:08 PM PDT 24	May 26 01:12:16 PM PDT 24	115193736249 ps
T140	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.580480770	May 26 01:11:08 PM PDT 24	May 26 01:11:16 PM PDT 24	2508094306 ps
T85	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.588987418	May 26 01:10:16 PM PDT 24	May 26 01:10:26 PM PDT 24	3283439418 ps
T102	/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.4135505619	May 26 01:10:51 PM PDT 24	May 26 01:12:31 PM PDT 24	36295851862 ps
T141	/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2010956728	May 26 01:09:49 PM PDT 24	May 26 01:09:57 PM PDT 24	2454197329 ps
T142	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1286483998	May 26 01:10:25 PM PDT 24	May 26 01:13:03 PM PDT 24	59670093311 ps
T143	/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.1931053652	May 26 01:10:36 PM PDT 24	May 26 01:10:44 PM PDT 24	2189273845 ps
T144	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1503294086	May 26 01:10:58 PM PDT 24	May 26 01:11:08 PM PDT 24	3604476950 ps
T219	/workspace/coverage/default/6.sysrst_ctrl_alert_test.18357539	May 26 01:09:36 PM PDT 24	May 26 01:09:43 PM PDT 24	2009227776 ps
T220	/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2335734619	May 26 01:11:10 PM PDT 24	May 26 01:17:37 PM PDT 24	138641444158 ps
T221	/workspace/coverage/default/27.sysrst_ctrl_combo_detect.2717744875	May 26 01:10:30 PM PDT 24	May 26 01:13:59 PM PDT 24	101722188196 ps
T222	/workspace/coverage/default/15.sysrst_ctrl_smoke.2966262208	May 26 01:10:07 PM PDT 24	May 26 01:10:15 PM PDT 24	2109288284 ps
T399	/workspace/coverage/default/43.sysrst_ctrl_smoke.2765747699	May 26 01:10:51 PM PDT 24	May 26 01:10:58 PM PDT 24	2109066931 ps
T400	/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1468061779	May 26 01:09:49 PM PDT 24	May 26 01:09:52 PM PDT 24	2627359007 ps
T181	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.4110071748	May 26 01:10:30 PM PDT 24	May 26 01:12:02 PM PDT 24	137430134588 ps
T401	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3435252958	May 26 01:09:38 PM PDT 24	May 26 01:09:42 PM PDT 24	2422288086 ps
T128	/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1950225506	May 26 01:09:40 PM PDT 24	May 26 01:09:52 PM PDT 24	3333253293 ps
T208	/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2827095571	May 26 01:10:58 PM PDT 24	May 26 01:11:04 PM PDT 24	2860841529 ps
T402	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4139782107	May 26 01:10:58 PM PDT 24	May 26 01:11:05 PM PDT 24	2221160203 ps
T403	/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1182005947	May 26 01:11:16 PM PDT 24	May 26 01:11:19 PM PDT 24	2038998443 ps
T302	/workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3120524410	May 26 01:10:00 PM PDT 24	May 26 01:10:11 PM PDT 24	3570032590 ps
T404	/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.337317034	May 26 01:09:46 PM PDT 24	May 26 01:09:50 PM PDT 24	2531543575 ps
T405	/workspace/coverage/default/24.sysrst_ctrl_alert_test.3446716967	May 26 01:10:18 PM PDT 24	May 26 01:10:25 PM PDT 24	2014207312 ps
T406	/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.970857407	May 26 01:10:51 PM PDT 24	May 26 01:10:54 PM PDT 24	2627740983 ps
T407	/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3932986301	May 26 01:10:58 PM PDT 24	May 26 01:11:02 PM PDT 24	2669174189 ps
T93	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.4103939072	May 26 01:10:57 PM PDT 24	May 26 01:12:06 PM PDT 24	115293113988 ps
T408	/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.879826081	May 26 01:10:26 PM PDT 24	May 26 01:10:28 PM PDT 24	2139590210 ps
T409	/workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2047136028	May 26 01:10:31 PM PDT 24	May 26 01:10:37 PM PDT 24	5231599052 ps
T410	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3758132834	May 26 01:09:43 PM PDT 24	May 26 01:09:51 PM PDT 24	2406425760 ps
T411	/workspace/coverage/default/37.sysrst_ctrl_smoke.412150961	May 26 01:10:45 PM PDT 24	May 26 01:10:53 PM PDT 24	2111662848 ps
T103	/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.464708993	May 26 01:11:14 PM PDT 24	May 26 01:12:12 PM PDT 24	21828926094 ps
T88	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3581049189	May 26 01:10:17 PM PDT 24	May 26 01:10:21 PM PDT 24	8405078407 ps
T412	/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1244041833	May 26 01:09:39 PM PDT 24	May 26 01:09:49 PM PDT 24	2612932538 ps
T413	/workspace/coverage/default/21.sysrst_ctrl_alert_test.3182162795	May 26 01:10:18 PM PDT 24	May 26 01:10:26 PM PDT 24	2013343466 ps
T199	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.1753203127	May 26 01:10:05 PM PDT 24	May 26 01:10:15 PM PDT 24	3165813725 ps
T414	/workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2586534011	May 26 01:10:01 PM PDT 24	May 26 01:10:06 PM PDT 24	2642510268 ps
T415	/workspace/coverage/default/10.sysrst_ctrl_alert_test.2484265343	May 26 01:09:51 PM PDT 24	May 26 01:09:58 PM PDT 24	2013931406 ps
T129	/workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.725397357	May 26 01:10:32 PM PDT 24	May 26 01:11:21 PM PDT 24	36593218805 ps
T416	/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2816388125	May 26 01:10:41 PM PDT 24	May 26 01:10:48 PM PDT 24	3254899979 ps
T417	/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.385583878	May 26 01:10:42 PM PDT 24	May 26 01:10:47 PM PDT 24	2080655007 ps
T346	/workspace/coverage/default/26.sysrst_ctrl_combo_detect.1425607668	May 26 01:10:18 PM PDT 24	May 26 01:18:47 PM PDT 24	188954336906 ps
T418	/workspace/coverage/default/45.sysrst_ctrl_stress_all.691589304	May 26 01:11:17 PM PDT 24	May 26 01:18:04 PM PDT 24	165509765966 ps
T344	/workspace/coverage/default/32.sysrst_ctrl_combo_detect.3317082064	May 26 01:10:39 PM PDT 24	May 26 01:17:48 PM PDT 24	159977374561 ps
T419	/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.525543987	May 26 01:10:16 PM PDT 24	May 26 01:10:18 PM PDT 24	4067598750 ps
T420	/workspace/coverage/default/32.sysrst_ctrl_stress_all.2160557147	May 26 01:10:42 PM PDT 24	May 26 01:10:48 PM PDT 24	6309289809 ps
T171	/workspace/coverage/default/47.sysrst_ctrl_edge_detect.310806780	May 26 01:11:14 PM PDT 24	May 26 01:11:17 PM PDT 24	3820556771 ps
T421	/workspace/coverage/default/11.sysrst_ctrl_smoke.1160779368	May 26 01:09:59 PM PDT 24	May 26 01:10:05 PM PDT 24	2107585760 ps
T209	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.1834862437	May 26 01:09:29 PM PDT 24	May 26 01:09:33 PM PDT 24	2685112794 ps
T422	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.126247147	May 26 01:09:56 PM PDT 24	May 26 01:10:07 PM PDT 24	2614170013 ps
T423	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.404029917	May 26 01:10:09 PM PDT 24	May 26 01:10:13 PM PDT 24	2475770000 ps
T200	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2613439870	May 26 01:10:16 PM PDT 24	May 26 01:11:18 PM PDT 24	24036825748 ps
T252	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2329527246	May 26 01:10:35 PM PDT 24	May 26 01:11:22 PM PDT 24	90739576210 ps
T424	/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2929943495	May 26 01:10:37 PM PDT 24	May 26 01:10:41 PM PDT 24	2628498152 ps
T425	/workspace/coverage/default/39.sysrst_ctrl_alert_test.3409523581	May 26 01:10:40 PM PDT 24	May 26 01:10:44 PM PDT 24	2020768527 ps
T426	/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1252198061	May 26 01:10:00 PM PDT 24	May 26 01:10:03 PM PDT 24	3229487189 ps
T427	/workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2296336075	May 26 01:10:15 PM PDT 24	May 26 01:10:19 PM PDT 24	2040089645 ps
T130	/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.636022911	May 26 01:10:31 PM PDT 24	May 26 01:11:09 PM PDT 24	61836910816 ps
T313	/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1804906195	May 26 01:10:43 PM PDT 24	May 26 01:10:53 PM PDT 24	2510929729 ps
T428	/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2553786105	May 26 01:10:43 PM PDT 24	May 26 01:12:37 PM PDT 24	173467142068 ps
T429	/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.2033390173	May 26 01:10:42 PM PDT 24	May 26 01:10:50 PM PDT 24	2048758585 ps
T146	/workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1461116269	May 26 01:10:11 PM PDT 24	May 26 01:14:19 PM PDT 24	1574516794858 ps
T261	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4156100880	May 26 01:11:11 PM PDT 24	May 26 01:16:56 PM PDT 24	121257306564 ps
T430	/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3274424392	May 26 01:10:19 PM PDT 24	May 26 01:10:22 PM PDT 24	2047037662 ps
T431	/workspace/coverage/default/39.sysrst_ctrl_smoke.2813478747	May 26 01:10:43 PM PDT 24	May 26 01:10:48 PM PDT 24	2113295375 ps
T156	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.3252398142	May 26 01:09:40 PM PDT 24	May 26 01:09:49 PM PDT 24	3479589017 ps
T262	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3326410005	May 26 01:11:12 PM PDT 24	May 26 01:11:26 PM PDT 24	47728680377 ps
T104	/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.792202160	May 26 01:11:14 PM PDT 24	May 26 01:12:40 PM PDT 24	64054971377 ps
T432	/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1069071542	May 26 01:09:52 PM PDT 24	May 26 01:10:07 PM PDT 24	2453402986 ps
T147	/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.916780668	May 26 01:09:51 PM PDT 24	May 26 01:09:54 PM PDT 24	14609872762 ps
T433	/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.624660068	May 26 01:11:02 PM PDT 24	May 26 01:11:07 PM PDT 24	6085037627 ps
T314	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1639187005	May 26 01:10:18 PM PDT 24	May 26 01:10:26 PM PDT 24	2511954073 ps
T255	/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.652659953	May 26 01:11:14 PM PDT 24	May 26 01:12:58 PM PDT 24	160736137058 ps
T371	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2057520766	May 26 01:10:53 PM PDT 24	May 26 01:18:30 PM PDT 24	168973846869 ps
T434	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3501284802	May 26 01:10:08 PM PDT 24	May 26 01:10:14 PM PDT 24	2616119994 ps
T435	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.4240167586	May 26 01:10:56 PM PDT 24	May 26 01:10:59 PM PDT 24	2640141766 ps
T271	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3983565237	May 26 01:11:12 PM PDT 24	May 26 01:12:16 PM PDT 24	25831335787 ps
T436	/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1109704717	May 26 01:10:58 PM PDT 24	May 26 01:11:01 PM PDT 24	2705819556 ps
T105	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.2956415986	May 26 01:10:30 PM PDT 24	May 26 01:12:00 PM PDT 24	133042357733 ps
T437	/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3589094571	May 26 01:10:02 PM PDT 24	May 26 01:10:07 PM PDT 24	3861590937 ps
T272	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3629002683	May 26 01:09:54 PM PDT 24	May 26 01:10:34 PM PDT 24	119927279679 ps
T311	/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3947654599	May 26 01:11:13 PM PDT 24	May 26 01:11:18 PM PDT 24	2475557601 ps
T372	/workspace/coverage/default/3.sysrst_ctrl_combo_detect.2913042602	May 26 01:09:47 PM PDT 24	May 26 01:13:03 PM PDT 24	148923038779 ps
T438	/workspace/coverage/default/23.sysrst_ctrl_pin_override_test.3995721436	May 26 01:10:20 PM PDT 24	May 26 01:10:28 PM PDT 24	2512810180 ps
T439	/workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.869292240	May 26 01:09:49 PM PDT 24	May 26 01:09:57 PM PDT 24	2613694263 ps
T309	/workspace/coverage/default/9.sysrst_ctrl_stress_all.2728581350	May 26 01:09:54 PM PDT 24	May 26 01:14:27 PM PDT 24	417245053479 ps
T440	/workspace/coverage/default/9.sysrst_ctrl_smoke.2377099894	May 26 01:10:01 PM PDT 24	May 26 01:10:05 PM PDT 24	2146135663 ps
T441	/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.4004081728	May 26 01:10:58 PM PDT 24	May 26 01:11:03 PM PDT 24	2622875342 ps
T442	/workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2511396620	May 26 01:10:07 PM PDT 24	May 26 01:10:10 PM PDT 24	2632300579 ps
T182	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.573167055	May 26 01:10:10 PM PDT 24	May 26 01:10:19 PM PDT 24	3256714313 ps
T443	/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3671267515	May 26 01:10:37 PM PDT 24	May 26 01:10:42 PM PDT 24	2227870463 ps
T444	/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.200343162	May 26 01:09:54 PM PDT 24	May 26 01:10:50 PM PDT 24	97247933536 ps
T445	/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1572483400	May 26 01:10:28 PM PDT 24	May 26 01:10:33 PM PDT 24	2465885248 ps
T446	/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2922021575	May 26 01:11:10 PM PDT 24	May 26 01:11:21 PM PDT 24	2471367028 ps
T345	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.853240084	May 26 01:09:38 PM PDT 24	May 26 01:11:54 PM PDT 24	63081933985 ps
T447	/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3835600112	May 26 01:09:49 PM PDT 24	May 26 01:10:00 PM PDT 24	3052992286 ps
T448	/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3556210264	May 26 01:10:43 PM PDT 24	May 26 01:10:49 PM PDT 24	8002735877 ps