Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T25 |
7 |
|
T11 |
7 |
|
T26 |
9 |
| auto[1] |
910 |
1 |
|
|
T25 |
13 |
|
T11 |
13 |
|
T26 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T25 |
11 |
|
T11 |
12 |
|
T26 |
13 |
| auto[1] |
861 |
1 |
|
|
T25 |
9 |
|
T11 |
8 |
|
T26 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T25 |
11 |
|
T11 |
9 |
|
T26 |
14 |
| auto[1] |
861 |
1 |
|
|
T25 |
9 |
|
T11 |
11 |
|
T26 |
6 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T25 |
11 |
|
T11 |
9 |
|
T26 |
6 |
| auto[1] |
880 |
1 |
|
|
T25 |
9 |
|
T11 |
11 |
|
T26 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
873 |
1 |
|
|
T25 |
12 |
|
T11 |
12 |
|
T26 |
8 |
| auto[1] |
867 |
1 |
|
|
T25 |
8 |
|
T11 |
8 |
|
T26 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
905 |
1 |
|
|
T25 |
9 |
|
T11 |
7 |
|
T26 |
7 |
| auto[1] |
835 |
1 |
|
|
T25 |
11 |
|
T11 |
13 |
|
T26 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
869 |
1 |
|
|
T25 |
10 |
|
T11 |
12 |
|
T26 |
10 |
| auto[1] |
871 |
1 |
|
|
T25 |
10 |
|
T11 |
8 |
|
T26 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T25 |
8 |
|
T11 |
13 |
|
T26 |
10 |
| auto[1] |
886 |
1 |
|
|
T25 |
12 |
|
T11 |
7 |
|
T26 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
827 |
1 |
|
|
T25 |
14 |
|
T11 |
12 |
|
T26 |
12 |
| auto[1] |
913 |
1 |
|
|
T25 |
6 |
|
T11 |
8 |
|
T26 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T25 |
9 |
|
T11 |
9 |
|
T26 |
8 |
| auto[1] |
857 |
1 |
|
|
T25 |
11 |
|
T11 |
11 |
|
T26 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T25 |
11 |
|
T11 |
8 |
|
T26 |
6 |
| auto[1] |
865 |
1 |
|
|
T25 |
9 |
|
T11 |
12 |
|
T26 |
14 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T25 |
10 |
|
T11 |
10 |
|
T26 |
8 |
| auto[1] |
907 |
1 |
|
|
T25 |
10 |
|
T11 |
10 |
|
T26 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
838 |
1 |
|
|
T25 |
8 |
|
T11 |
13 |
|
T26 |
11 |
| auto[1] |
902 |
1 |
|
|
T25 |
12 |
|
T11 |
7 |
|
T26 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T25 |
11 |
|
T11 |
12 |
|
T26 |
13 |
| auto[1] |
861 |
1 |
|
|
T25 |
9 |
|
T11 |
8 |
|
T26 |
7 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T25 |
10 |
|
T11 |
11 |
|
T26 |
6 |
| auto[1] |
887 |
1 |
|
|
T25 |
10 |
|
T11 |
9 |
|
T26 |
14 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
850 |
1 |
|
|
T25 |
10 |
|
T11 |
11 |
|
T26 |
8 |
| auto[1] |
890 |
1 |
|
|
T25 |
10 |
|
T11 |
9 |
|
T26 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
869 |
1 |
|
|
T25 |
12 |
|
T11 |
8 |
|
T26 |
9 |
| auto[1] |
871 |
1 |
|
|
T25 |
8 |
|
T11 |
12 |
|
T26 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T25 |
11 |
|
T11 |
9 |
|
T26 |
8 |
| auto[1] |
827 |
1 |
|
|
T25 |
9 |
|
T11 |
11 |
|
T26 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T25 |
9 |
|
T11 |
12 |
|
T26 |
9 |
| auto[1] |
901 |
1 |
|
|
T25 |
11 |
|
T11 |
8 |
|
T26 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T25 |
9 |
|
T11 |
7 |
|
T26 |
7 |
| auto[1] |
886 |
1 |
|
|
T25 |
11 |
|
T11 |
13 |
|
T26 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T25 |
12 |
|
T11 |
12 |
|
T26 |
7 |
| auto[1] |
836 |
1 |
|
|
T25 |
8 |
|
T11 |
8 |
|
T26 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T25 |
12 |
|
T11 |
11 |
|
T26 |
11 |
| auto[1] |
847 |
1 |
|
|
T25 |
8 |
|
T11 |
9 |
|
T26 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
865 |
1 |
|
|
T25 |
18 |
|
T11 |
12 |
|
T26 |
9 |
| auto[1] |
875 |
1 |
|
|
T25 |
2 |
|
T11 |
8 |
|
T26 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T25 |
10 |
|
T11 |
10 |
|
T26 |
8 |
| auto[1] |
907 |
1 |
|
|
T25 |
10 |
|
T11 |
10 |
|
T26 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T25 |
6 |
|
T11 |
5 |
|
T26 |
5 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T25 |
4 |
|
T11 |
6 |
|
T26 |
1 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T25 |
5 |
|
T11 |
4 |
|
T26 |
9 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T25 |
5 |
|
T11 |
5 |
|
T26 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T25 |
6 |
|
T11 |
5 |
|
T26 |
2 |
| auto[0] |
auto[1] |
428 |
1 |
|
|
T25 |
4 |
|
T11 |
6 |
|
T26 |
6 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T25 |
5 |
|
T11 |
4 |
|
T26 |
4 |
| auto[1] |
auto[1] |
452 |
1 |
|
|
T25 |
5 |
|
T11 |
5 |
|
T26 |
8 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
429 |
1 |
|
|
T25 |
5 |
|
T11 |
5 |
|
T26 |
4 |
| auto[0] |
auto[1] |
440 |
1 |
|
|
T25 |
7 |
|
T11 |
3 |
|
T26 |
5 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T25 |
7 |
|
T11 |
7 |
|
T26 |
4 |
| auto[1] |
auto[1] |
427 |
1 |
|
|
T25 |
1 |
|
T11 |
5 |
|
T26 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
467 |
1 |
|
|
T25 |
3 |
|
T11 |
3 |
|
T26 |
3 |
| auto[0] |
auto[1] |
446 |
1 |
|
|
T25 |
8 |
|
T11 |
6 |
|
T26 |
5 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T25 |
6 |
|
T11 |
4 |
|
T26 |
4 |
| auto[1] |
auto[1] |
389 |
1 |
|
|
T25 |
3 |
|
T11 |
7 |
|
T26 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
421 |
1 |
|
|
T25 |
3 |
|
T11 |
8 |
|
T26 |
5 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T25 |
6 |
|
T11 |
4 |
|
T26 |
4 |
| auto[1] |
auto[0] |
448 |
1 |
|
|
T25 |
7 |
|
T11 |
4 |
|
T26 |
5 |
| auto[1] |
auto[1] |
453 |
1 |
|
|
T25 |
4 |
|
T11 |
4 |
|
T26 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
421 |
1 |
|
|
T25 |
2 |
|
T11 |
6 |
|
T26 |
4 |
| auto[0] |
auto[1] |
433 |
1 |
|
|
T25 |
7 |
|
T11 |
1 |
|
T26 |
3 |
| auto[1] |
auto[0] |
433 |
1 |
|
|
T25 |
6 |
|
T11 |
7 |
|
T26 |
6 |
| auto[1] |
auto[1] |
453 |
1 |
|
|
T25 |
5 |
|
T11 |
6 |
|
T26 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
454 |
1 |
|
|
T25 |
5 |
|
T11 |
5 |
|
T26 |
4 |
| auto[0] |
auto[1] |
439 |
1 |
|
|
T25 |
7 |
|
T11 |
6 |
|
T26 |
7 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T25 |
4 |
|
T11 |
4 |
|
T26 |
4 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T25 |
4 |
|
T11 |
5 |
|
T26 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
436 |
1 |
|
|
T25 |
9 |
|
T11 |
5 |
|
T26 |
2 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T25 |
9 |
|
T11 |
7 |
|
T26 |
7 |
| auto[1] |
auto[0] |
439 |
1 |
|
|
T25 |
2 |
|
T11 |
3 |
|
T26 |
4 |
| auto[1] |
auto[1] |
436 |
1 |
|
|
T11 |
5 |
|
T26 |
7 |
|
T71 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
390 |
1 |
|
|
T11 |
4 |
|
T26 |
3 |
|
T71 |
7 |
| auto[0] |
auto[1] |
448 |
1 |
|
|
T25 |
8 |
|
T11 |
9 |
|
T26 |
8 |
| auto[1] |
auto[0] |
440 |
1 |
|
|
T25 |
7 |
|
T11 |
3 |
|
T26 |
6 |
| auto[1] |
auto[1] |
462 |
1 |
|
|
T25 |
5 |
|
T11 |
4 |
|
T26 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
879 |
1 |
|
|
T25 |
11 |
|
T11 |
12 |
|
T26 |
13 |
| auto[1] |
auto[1] |
861 |
1 |
|
|
T25 |
9 |
|
T11 |
8 |
|
T26 |
7 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T25 |
8 |
|
T11 |
8 |
|
T26 |
4 |
| auto[0] |
auto[1] |
454 |
1 |
|
|
T25 |
4 |
|
T11 |
4 |
|
T26 |
3 |
| auto[1] |
auto[0] |
377 |
1 |
|
|
T25 |
6 |
|
T11 |
4 |
|
T26 |
8 |
| auto[1] |
auto[1] |
459 |
1 |
|
|
T25 |
2 |
|
T11 |
4 |
|
T26 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
833 |
1 |
|
|
T25 |
10 |
|
T11 |
10 |
|
T26 |
8 |
| auto[1] |
auto[1] |
907 |
1 |
|
|
T25 |
10 |
|
T11 |
10 |
|
T26 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T11 |
10 |
|
T39 |
10 |
|
T100 |
10 |
| auto[1] |
196 |
1 |
|
|
T11 |
10 |
|
T39 |
10 |
|
T100 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T11 |
13 |
|
T39 |
10 |
|
T100 |
12 |
| auto[1] |
178 |
1 |
|
|
T11 |
7 |
|
T39 |
10 |
|
T100 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T11 |
10 |
|
T39 |
8 |
|
T100 |
7 |
| auto[1] |
189 |
1 |
|
|
T11 |
10 |
|
T39 |
12 |
|
T100 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
180 |
1 |
|
|
T11 |
7 |
|
T39 |
8 |
|
T100 |
9 |
| auto[1] |
180 |
1 |
|
|
T11 |
13 |
|
T39 |
12 |
|
T100 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
168 |
1 |
|
|
T11 |
12 |
|
T39 |
11 |
|
T100 |
8 |
| auto[1] |
192 |
1 |
|
|
T11 |
8 |
|
T39 |
9 |
|
T100 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
185 |
1 |
|
|
T11 |
8 |
|
T39 |
10 |
|
T100 |
13 |
| auto[1] |
175 |
1 |
|
|
T11 |
12 |
|
T39 |
10 |
|
T100 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T11 |
13 |
|
T39 |
7 |
|
T100 |
9 |
| auto[1] |
195 |
1 |
|
|
T11 |
7 |
|
T39 |
13 |
|
T100 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
188 |
1 |
|
|
T11 |
8 |
|
T39 |
10 |
|
T100 |
9 |
| auto[1] |
172 |
1 |
|
|
T11 |
12 |
|
T39 |
10 |
|
T100 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T11 |
8 |
|
T39 |
13 |
|
T100 |
10 |
| auto[1] |
186 |
1 |
|
|
T11 |
12 |
|
T39 |
7 |
|
T100 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
185 |
1 |
|
|
T11 |
7 |
|
T39 |
8 |
|
T100 |
8 |
| auto[1] |
175 |
1 |
|
|
T11 |
13 |
|
T39 |
12 |
|
T100 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
195 |
1 |
|
|
T11 |
15 |
|
T39 |
12 |
|
T100 |
15 |
| auto[1] |
165 |
1 |
|
|
T11 |
5 |
|
T39 |
8 |
|
T100 |
5 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T11 |
11 |
|
T39 |
8 |
|
T100 |
12 |
| auto[1] |
179 |
1 |
|
|
T11 |
9 |
|
T39 |
12 |
|
T100 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
185 |
1 |
|
|
T11 |
9 |
|
T39 |
9 |
|
T100 |
10 |
| auto[1] |
175 |
1 |
|
|
T11 |
11 |
|
T39 |
11 |
|
T100 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T11 |
13 |
|
T39 |
10 |
|
T100 |
12 |
| auto[1] |
178 |
1 |
|
|
T11 |
7 |
|
T39 |
10 |
|
T100 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T11 |
10 |
|
T39 |
10 |
|
T100 |
12 |
| auto[1] |
197 |
1 |
|
|
T11 |
10 |
|
T39 |
10 |
|
T100 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
190 |
1 |
|
|
T11 |
9 |
|
T39 |
10 |
|
T100 |
10 |
| auto[1] |
170 |
1 |
|
|
T11 |
11 |
|
T39 |
10 |
|
T100 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
194 |
1 |
|
|
T11 |
7 |
|
T39 |
14 |
|
T100 |
10 |
| auto[1] |
166 |
1 |
|
|
T11 |
13 |
|
T39 |
6 |
|
T100 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
201 |
1 |
|
|
T11 |
15 |
|
T39 |
11 |
|
T100 |
13 |
| auto[1] |
159 |
1 |
|
|
T11 |
5 |
|
T39 |
9 |
|
T100 |
7 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T11 |
9 |
|
T39 |
15 |
|
T100 |
11 |
| auto[1] |
178 |
1 |
|
|
T11 |
11 |
|
T39 |
5 |
|
T100 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T11 |
10 |
|
T39 |
10 |
|
T100 |
9 |
| auto[1] |
177 |
1 |
|
|
T11 |
10 |
|
T39 |
10 |
|
T100 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T11 |
5 |
|
T39 |
7 |
|
T100 |
10 |
| auto[1] |
201 |
1 |
|
|
T11 |
15 |
|
T39 |
13 |
|
T100 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T11 |
12 |
|
T39 |
12 |
|
T100 |
11 |
| auto[1] |
186 |
1 |
|
|
T11 |
8 |
|
T39 |
8 |
|
T100 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T11 |
10 |
|
T39 |
8 |
|
T100 |
10 |
| auto[1] |
186 |
1 |
|
|
T11 |
10 |
|
T39 |
12 |
|
T100 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T11 |
11 |
|
T39 |
8 |
|
T100 |
12 |
| auto[1] |
179 |
1 |
|
|
T11 |
9 |
|
T39 |
12 |
|
T100 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T11 |
6 |
|
T39 |
5 |
|
T100 |
3 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T11 |
4 |
|
T39 |
5 |
|
T100 |
9 |
| auto[1] |
auto[0] |
99 |
1 |
|
|
T11 |
4 |
|
T39 |
3 |
|
T100 |
4 |
| auto[1] |
auto[1] |
98 |
1 |
|
|
T11 |
6 |
|
T39 |
7 |
|
T100 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T11 |
4 |
|
T39 |
5 |
|
T100 |
3 |
| auto[0] |
auto[1] |
100 |
1 |
|
|
T11 |
5 |
|
T39 |
5 |
|
T100 |
7 |
| auto[1] |
auto[0] |
90 |
1 |
|
|
T11 |
3 |
|
T39 |
3 |
|
T100 |
6 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T11 |
8 |
|
T39 |
7 |
|
T100 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
97 |
1 |
|
|
T11 |
4 |
|
T39 |
7 |
|
T100 |
6 |
| auto[0] |
auto[1] |
97 |
1 |
|
|
T11 |
3 |
|
T39 |
7 |
|
T100 |
4 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T11 |
8 |
|
T39 |
4 |
|
T100 |
2 |
| auto[1] |
auto[1] |
95 |
1 |
|
|
T11 |
5 |
|
T39 |
2 |
|
T100 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
109 |
1 |
|
|
T11 |
6 |
|
T39 |
5 |
|
T100 |
10 |
| auto[0] |
auto[1] |
92 |
1 |
|
|
T11 |
9 |
|
T39 |
6 |
|
T100 |
3 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T11 |
2 |
|
T39 |
5 |
|
T100 |
3 |
| auto[1] |
auto[1] |
83 |
1 |
|
|
T11 |
3 |
|
T39 |
4 |
|
T100 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T11 |
5 |
|
T39 |
6 |
|
T100 |
6 |
| auto[0] |
auto[1] |
92 |
1 |
|
|
T11 |
4 |
|
T39 |
9 |
|
T100 |
5 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T11 |
8 |
|
T39 |
1 |
|
T100 |
3 |
| auto[1] |
auto[1] |
103 |
1 |
|
|
T11 |
3 |
|
T39 |
4 |
|
T100 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
102 |
1 |
|
|
T11 |
3 |
|
T39 |
5 |
|
T100 |
5 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T11 |
7 |
|
T39 |
5 |
|
T100 |
4 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T11 |
5 |
|
T39 |
5 |
|
T100 |
4 |
| auto[1] |
auto[1] |
91 |
1 |
|
|
T11 |
5 |
|
T39 |
5 |
|
T100 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
94 |
1 |
|
|
T11 |
4 |
|
T39 |
4 |
|
T100 |
6 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T11 |
8 |
|
T39 |
8 |
|
T100 |
5 |
| auto[1] |
auto[0] |
91 |
1 |
|
|
T11 |
3 |
|
T39 |
4 |
|
T100 |
2 |
| auto[1] |
auto[1] |
95 |
1 |
|
|
T11 |
5 |
|
T39 |
4 |
|
T100 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
99 |
1 |
|
|
T11 |
7 |
|
T39 |
4 |
|
T100 |
9 |
| auto[0] |
auto[1] |
75 |
1 |
|
|
T11 |
3 |
|
T39 |
4 |
|
T100 |
1 |
| auto[1] |
auto[0] |
96 |
1 |
|
|
T11 |
8 |
|
T39 |
8 |
|
T100 |
6 |
| auto[1] |
auto[1] |
90 |
1 |
|
|
T11 |
2 |
|
T39 |
4 |
|
T100 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T11 |
5 |
|
T39 |
5 |
|
T100 |
6 |
| auto[0] |
auto[1] |
102 |
1 |
|
|
T11 |
4 |
|
T39 |
4 |
|
T100 |
4 |
| auto[1] |
auto[0] |
81 |
1 |
|
|
T11 |
5 |
|
T39 |
5 |
|
T100 |
4 |
| auto[1] |
auto[1] |
94 |
1 |
|
|
T11 |
6 |
|
T39 |
6 |
|
T100 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
182 |
1 |
|
|
T11 |
13 |
|
T39 |
10 |
|
T100 |
12 |
| auto[1] |
auto[1] |
178 |
1 |
|
|
T11 |
7 |
|
T39 |
10 |
|
T100 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T11 |
1 |
|
T39 |
5 |
|
T100 |
5 |
| auto[0] |
auto[1] |
78 |
1 |
|
|
T11 |
4 |
|
T39 |
2 |
|
T100 |
5 |
| auto[1] |
auto[0] |
93 |
1 |
|
|
T11 |
7 |
|
T39 |
8 |
|
T100 |
5 |
| auto[1] |
auto[1] |
108 |
1 |
|
|
T11 |
8 |
|
T39 |
5 |
|
T100 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
181 |
1 |
|
|
T11 |
11 |
|
T39 |
8 |
|
T100 |
12 |
| auto[1] |
auto[1] |
179 |
1 |
|
|
T11 |
9 |
|
T39 |
12 |
|
T100 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T100 |
11 |
|
T106 |
12 |
|
T269 |
11 |
| auto[1] |
44 |
1 |
|
|
T100 |
9 |
|
T106 |
8 |
|
T269 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T100 |
12 |
|
T106 |
11 |
|
T269 |
10 |
| auto[1] |
45 |
1 |
|
|
T100 |
8 |
|
T106 |
9 |
|
T269 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T100 |
9 |
|
T106 |
12 |
|
T269 |
10 |
| auto[1] |
52 |
1 |
|
|
T100 |
11 |
|
T106 |
8 |
|
T269 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T100 |
12 |
|
T106 |
9 |
|
T269 |
12 |
| auto[1] |
45 |
1 |
|
|
T100 |
8 |
|
T106 |
11 |
|
T269 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T100 |
8 |
|
T106 |
10 |
|
T269 |
10 |
| auto[1] |
57 |
1 |
|
|
T100 |
12 |
|
T106 |
10 |
|
T269 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T100 |
4 |
|
T106 |
10 |
|
T269 |
13 |
| auto[1] |
55 |
1 |
|
|
T100 |
16 |
|
T106 |
10 |
|
T269 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T100 |
5 |
|
T106 |
9 |
|
T269 |
10 |
| auto[1] |
57 |
1 |
|
|
T100 |
15 |
|
T106 |
11 |
|
T269 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
58 |
1 |
|
|
T100 |
14 |
|
T106 |
8 |
|
T269 |
11 |
| auto[1] |
42 |
1 |
|
|
T100 |
6 |
|
T106 |
12 |
|
T269 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T100 |
13 |
|
T106 |
12 |
|
T269 |
9 |
| auto[1] |
45 |
1 |
|
|
T100 |
7 |
|
T106 |
8 |
|
T269 |
11 |