Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1924

1

T1

5

T33

10

T34

38

auto[1]

648

1

T1

3

T6

4

T42

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1955

1

T33

8

T34

34

T44

6

auto[1]

617

1

T1

8

T6

4

T42

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1990

1

T1

8

T6

4

T33

8

auto[1]

582

1

T42

1

T33

4

T34

18

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1979

1

T1

3

T34

32

T44

4

auto[1]

593

1

T1

5

T6

4

T42

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2341

1

T1

8

T6

4

T42

1

auto[1]

231

1

T34

14

T44

4

T45

10

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2340

1

T1

8

T6

4

T42

1

auto[1]

232

1

T45

10

T90

5

T92

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2263

1

T1

8

T6

4

T42

1

auto[1]

309

1

T34

16

T90

3

T156

13

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2313

1

T1

8

T6

4

T42

1

auto[1]

259

1

T44

2

T45

24

T90

12

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2307

1

T1

8

T6

4

T42

1

auto[1]

265

1

T34

16

T44

4

T72

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1995

1

T1

5

T42

1

T33

10

auto[1]

577

1

T1

3

T6

4

T33

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	749	1			T1	8		T6	4		T42	1
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	27	1			T34	5		T44	1		T341	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	76	1			T34	9		T240	4		T236	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	28	1			T44	1		T343	4		T235	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	100	1			T241	2		T247	5		T342	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	23	1			T45	10		T90	6		T83	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	33	1			T44	1		T45	4		T338	13
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	8	1			T355	2		T356	4		T357	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	98	1			T34	9		T156	7		T358	7
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	30	1			T343	3		T236	1		T359	6
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	48	1			T90	1		T241	1		T360	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T34	5		T361	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	15	1			T338	10		T80	2		T362	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T84	2		T363	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	43	1			T240	2		T341	6		T364	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	27	1			T240	2		T247	4		T341	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	18	1			T153	2		T236	1		T344	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	20	1			T93	20		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	37	1			T45	10		T90	4		T92	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	3	1			T357	2		T365	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T366	5		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T367	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	45	1			T156	6		T93	9		T247	8
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T344	2		T355	3		T346	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	8	1			T361	1		T84	4		T181	1
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T351	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T363	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

110

1

T44

1

T125

11

T111

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

93

1

T45

10

T247

4

T98

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

89

1

T93

9

T247

4

T242

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

106

1

T33

8

T35

1

T153

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

73

1

T85

1

T219

4

T248

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55

1

T34

9

T340

6

T162

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T36

2

T125

1

T350

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

109

1

T85

2

T153

2

T248

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

74

1

T34

9

T35

1

T219

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T45

10

T90

4

T240

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

35

1

T92

3

T219

1

T247

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T44

1

T93

10

T76

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T76

3

T77

1

T236

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T339

2

T358

4

T368

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T262

5

T162

1

T337

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

100

1

T45

4

T240

2

T343

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

78

1

T219

5

T340

5

T338

19

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T1

2

T90

6

T111

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T1

1

T255

3

T81

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

96

1

T1

3

T34

5

T77

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T1

2

T90

1

T240

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T255

4

T174

2

T369

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T6

4

T76

1

T174

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T34

5

T36

3

T355

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

52

1

T36

3

T125

1

T78

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

7

1

T226

2

T256

4

T370

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T241

2

T261

3

T371

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

10

1

T33

2

T76

1

T77

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T42

1

T203

1

T372

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T44

1

T242

3

T105

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T33

2

T242

2

T368

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded