Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T17

14

T26

12

T25

12

auto[1]

979

1

T17

6

T26

8

T25

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

478

1

T17

4

T26

5

T25

5

from_0to1

468

1

T17

4

T26

6

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

929

1

T17

8

T26

11

T25

9

auto[1]

1056

1

T17

12

T26

9

T25

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T17

9

T26

8

T25

11

auto[1]

999

1

T17

11

T26

12

T25

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T25

1

T200

2

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

44

1

T26

2

T25

1

T200

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T17

1

T26

1

T200

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T172

1

T68

3

T313

1

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T17

1

T25

2

T46

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T46

2

T200

1

T312

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T17

1

T26

2

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T17

1

T25

2

T46

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T17

1

T46

3

T172

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T25

1

T46

1

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T25

2

T46

1

T172

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T17

2

T26

2

T46

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T26

1

T46

2

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T26

3

T200

2

T68

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T200

1

T172

2

T68

2

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T17

1

T200

1

T172

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

974

1

T17

11

T26

10

T25

8

auto[1]

1011

1

T17

9

T26

10

T25

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

474

1

T17

5

T26

4

T25

5

from_0to1

464

1

T17

4

T26

4

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T17

12

T26

11

T25

12

auto[1]

980

1

T17

8

T26

9

T25

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T17

6

T26

13

T25

9

auto[1]

991

1

T17

14

T26

7

T25

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T26

1

T46

1

T200

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T17

1

T26

1

T25

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T17

1

T26

1

T46

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T17

1

T25

1

T46

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T25

1

T46

2

T311

3

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T17

2

T26

1

T25

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T26

2

T200

2

T68

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T200

1

T172

1

T383

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T25

1

T46

1

T383

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T26

1

T25

2

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T17

1

T46

2

T200

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T17

1

T200

1

T172

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T46

1

T172

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T17

2

T46

1

T200

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T26

1

T25

1

T46

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T25

2

T172

2

T313

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

962

1

T17

11

T26

10

T25

8

auto[1]

1023

1

T17

9

T26

10

T25

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

477

1

T17

5

T26

4

T25

5

from_0to1

479

1

T17

5

T26

4

T25

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T17

8

T26

8

T25

10

auto[1]

999

1

T17

12

T26

12

T25

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T17

9

T26

8

T25

10

auto[1]

990

1

T17

11

T26

12

T25

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T17

1

T26

1

T25

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T17

1

T172

2

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T17

1

T46

1

T200

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T17

2

T26

1

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T172

1

T311

2

T383

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T26

2

T172

1

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T17

1

T25

1

T46

2

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T17

1

T172

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T25

1

T172

1

T312

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T200

1

T68

1

T311

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T26

1

T25

1

T200

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T26

1

T25

1

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T17

2

T26

1

T46

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T17

1

T25

2

T200

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T46

1

T200

1

T172

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T26

1

T25

1

T46

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T17

6

T26

10

T25

11

auto[1]

964

1

T17

14

T26

10

T25

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

470

1

T17

4

T26

6

T25

7

from_0to1

472

1

T17

4

T26

6

T25

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T17

6

T26

11

T25

9

auto[1]

945

1

T17

14

T26

9

T25

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

982

1

T17

9

T26

10

T25

8

auto[1]

1003

1

T17

11

T26

10

T25

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T311

1

T313

1

T85

2

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T26

1

T25

2

T172

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T17

1

T26

1

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T25

2

T200

2

T312

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T26

1

T25

1

T311

3

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T26

3

T25

1

T46

2

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T26

1

T25

1

T200

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T17

1

T25

1

T68

2

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T26

1

T200

1

T172

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T17

1

T26

2

T46

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T17

1

T25

2

T46

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T17

1

T26

1

T25

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T172

1

T68

2

T383

2

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T17

1

T25

1

T200

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T17

1

T26

1

T25

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T17

1

T200

1

T172

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T17

11

T26

10

T25

10

auto[1]

980

1

T17

9

T26

10

T25

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

479

1

T17

4

T26

5

T25

5

from_0to1

475

1

T17

4

T26

4

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T17

10

T26

13

T25

10

auto[1]

1027

1

T17

10

T26

7

T25

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

960

1

T17

9

T26

11

T25

12

auto[1]

1025

1

T17

11

T26

9

T25

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T25

2

T46

1

T172

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T26

1

T68

1

T311

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T26

1

T25

1

T200

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T17

1

T25

1

T200

3

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T17

1

T26

1

T46

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T26

1

T311

1

T312

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T17

1

T25

1

T200

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T17

2

T25

1

T46

2

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T17

1

T26

2

T25

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T46

1

T313

2

T209

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T17

1

T26

1

T46

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T17

1

T46

2

T172

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T26

1

T46

1

T200

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T25

1

T200

1

T172

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T25

1

T200

2

T172

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T26

1

T25

1

T46

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

993

1

T17

9

T26

12

T25

8

auto[1]

992

1

T17

11

T26

8

T25

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

472

1

T17

5

T26

6

T25

5

from_0to1

484

1

T17

5

T26

5

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

957

1

T17

12

T26

11

T25

6

auto[1]

1028

1

T17

8

T26

9

T25

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T17

7

T26

7

T25

8

auto[1]

1002

1

T17

13

T26

13

T25

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T26

1

T68

2

T313

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T17

2

T26

2

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T17

1

T25

2

T46

2

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T26

1

T313

1

T85

4

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T26

1

T25

1

T200

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T17

1

T172

1

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T46

1

T200

1

T172

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T17

1

T46

1

T200

2

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T17

1

T172

1

T313

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T26

1

T25

1

T46

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T25

1

T172

1

T311

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T17

1

T26

1

T25

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T17

1

T25

1

T68

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T17

1

T311

1

T313

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T17

1

T26

1

T25

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T26

3

T25

2

T46

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

982

1

T17

8

T26

10

T25

11

auto[1]

1003

1

T17

12

T26

10

T25

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

471

1

T17

5

T26

6

T25

6

from_0to1

464

1

T17

5

T26

5

T25

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

973

1

T17

10

T26

8

T25

7

auto[1]

1012

1

T17

10

T26

12

T25

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T17

10

T26

5

T25

10

auto[1]

985

1

T17

10

T26

15

T25

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T26

1

T25

1

T46

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T26

2

T25

1

T46

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T17

1

T46

2

T172

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T26

1

T25

1

T200

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T25

2

T200

1

T311

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T17

1

T25

1

T46

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T25

2

T46

2

T200

1

auto[0]

from_0to1

auto[1]

auto[1]

48

1

T17

1

T26

1

T25

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T17

1

T26

1

T200

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T17

1

T25

1

T172

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T17

2

T25

2

T46

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T26

1

T46

1

T200

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T17

1

T200

1

T313

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T17

1

T26

3

T46

2

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T25

1

T46

1

T172

2

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T17

1

T26

1

T172

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1017

1

T17

15

T26

12

T25

11

auto[1]

968

1

T17

5

T26

8

T25

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

478

1

T17

5

T26

6

T25

5

from_0to1

474

1

T17

5

T26

5

T25

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

989

1

T17

12

T26

6

T25

12

auto[1]

996

1

T17

8

T26

14

T25

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T17

12

T26

10

T25

8

auto[1]

980

1

T17

8

T26

10

T25

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T25

1

T46

1

T200

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T46

1

T68

1

T311

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T17

2

T26

1

T25

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T17

2

T26

2

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T17

1

T26

1

T25

2

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T17

1

T200

1

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T26

1

T25

1

T172

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T26

1

T68

2

T313

2

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T26

1

T46

2

T200

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T313

1

T85

2

T301

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T17

1

T25

1

T46

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T26

2

T25

1

T46

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T17

2

T46

2

T311

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T17

1

T25

1

T200

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T26

1

T46

1

T200

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T26

1

T200

1

T172

1