Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150821	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113486

1

T4

8

T5

24

T1

229

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	135490	1			T4	8		T5	45		T1	395
values[0x0]	64245	1			T4	4		T1	52		T13	47
values[0x1]	64572	1			T4	3		T1	36		T13	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

142091

1

T4

11

T5

31

T1

277

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	866	1			T1	2		T13	2		T15	3
valid_sources[0x01]	805	1			T13	2		T15	1		T17	3
valid_sources[0x02]	2300	1			T1	1		T6	1		T7	1
valid_sources[0x03]	903	1			T5	1		T1	1		T13	2
valid_sources[0x04]	1000	1			T1	3		T15	1		T17	1
valid_sources[0x05]	1393	1			T1	2		T13	2		T15	1
valid_sources[0x06]	1143	1			T6	3		T27	2		T24	1
valid_sources[0x07]	974	1			T2	2		T15	3		T17	2
valid_sources[0x08]	1123	1			T15	2		T17	2		T6	2
valid_sources[0x09]	836	1			T1	2		T13	2		T15	1
valid_sources[0x0a]	1393	1			T4	3		T1	1		T15	1
valid_sources[0x0b]	1124	1			T1	1		T15	1		T17	1
valid_sources[0x0c]	1157	1			T1	3		T15	1		T6	1
valid_sources[0x0d]	987	1			T1	1		T13	1		T25	1
valid_sources[0x0e]	1075	1			T6	3		T9	3		T25	2
valid_sources[0x0f]	965	1			T15	1		T6	2		T27	3
valid_sources[0x10]	2461	1			T1	3		T13	2		T15	1
valid_sources[0x11]	1334	1			T1	4		T13	2		T9	2
valid_sources[0x12]	697	1			T5	1		T1	3		T15	2
valid_sources[0x13]	1054	1			T1	2		T15	2		T6	1
valid_sources[0x14]	1163	1			T5	1		T1	1		T15	1
valid_sources[0x15]	1449	1			T1	3		T7	1		T27	1
valid_sources[0x16]	844	1			T1	4		T15	1		T27	1
valid_sources[0x17]	798	1			T5	1		T1	4		T6	1
valid_sources[0x18]	916	1			T1	2		T13	1		T15	2
valid_sources[0x19]	960	1			T1	2		T13	2		T15	3
valid_sources[0x1a]	775	1			T1	1		T13	2		T15	1
valid_sources[0x1b]	876	1			T1	4		T15	5		T17	2
valid_sources[0x1c]	902	1			T4	1		T1	3		T15	3
valid_sources[0x1d]	1419	1			T1	3		T15	2		T17	2
valid_sources[0x1e]	981	1			T1	2		T15	2		T6	2
valid_sources[0x1f]	937	1			T15	1		T7	2		T27	6
valid_sources[0x20]	917	1			T1	2		T6	2		T9	2
valid_sources[0x21]	1021	1			T6	2		T27	2		T9	1
valid_sources[0x22]	977	1			T1	3		T15	2		T6	1
valid_sources[0x23]	1570	1			T1	5		T15	2		T17	1
valid_sources[0x24]	727	1			T1	2		T13	1		T15	3
valid_sources[0x25]	788	1			T1	4		T15	2		T17	1
valid_sources[0x26]	798	1			T1	1		T17	1		T27	3
valid_sources[0x27]	985	1			T1	1		T13	3		T15	2
valid_sources[0x28]	918	1			T14	2		T15	3		T17	3
valid_sources[0x29]	756	1			T13	1		T14	1		T15	1
valid_sources[0x2a]	1382	1			T1	4		T13	4		T15	3
valid_sources[0x2b]	1287	1			T1	3		T15	1		T6	1
valid_sources[0x2c]	933	1			T1	4		T13	5		T15	1
valid_sources[0x2d]	1430	1			T4	1		T1	6		T15	1
valid_sources[0x2e]	913	1			T1	2		T15	1		T6	2
valid_sources[0x2f]	830	1			T6	6		T55	2		T9	1
valid_sources[0x30]	1972	1			T1	1		T15	2		T6	2
valid_sources[0x31]	1010	1			T1	1		T15	1		T6	1
valid_sources[0x32]	892	1			T13	3		T15	3		T6	1
valid_sources[0x33]	973	1			T13	1		T15	3		T6	4
valid_sources[0x34]	890	1			T5	1		T1	1		T15	3
valid_sources[0x35]	920	1			T1	3		T15	5		T25	1
valid_sources[0x36]	1140	1			T1	4		T15	1		T6	5
valid_sources[0x37]	938	1			T1	2		T15	3		T6	1
valid_sources[0x38]	946	1			T1	2		T13	2		T15	1
valid_sources[0x39]	792	1			T1	1		T15	7		T17	1
valid_sources[0x3a]	811	1			T1	6		T15	1		T17	1
valid_sources[0x3b]	903	1			T15	2		T17	1		T6	1
valid_sources[0x3c]	998	1			T1	1		T15	4		T17	2
valid_sources[0x3d]	893	1			T1	1		T15	2		T6	2
valid_sources[0x3e]	1000	1			T4	1		T1	3		T15	2
valid_sources[0x3f]	925	1			T15	2		T17	1		T6	5
valid_sources[0x40]	795	1			T1	1		T15	2		T6	3
valid_sources[0x41]	1028	1			T1	1		T17	1		T19	1
valid_sources[0x42]	720	1			T4	2		T1	5		T15	2
valid_sources[0x43]	818	1			T5	1		T1	2		T13	1
valid_sources[0x44]	1748	1			T5	1		T1	3		T13	1
valid_sources[0x45]	952	1			T5	1		T1	3		T13	1
valid_sources[0x46]	949	1			T15	3		T6	1		T27	1
valid_sources[0x47]	766	1			T1	3		T15	1		T9	1
valid_sources[0x48]	925	1			T1	1		T6	1		T27	9
valid_sources[0x49]	977	1			T4	1		T1	2		T13	1
valid_sources[0x4a]	958	1			T5	2		T13	1		T6	5
valid_sources[0x4b]	1119	1			T5	1		T1	2		T13	1
valid_sources[0x4c]	948	1			T1	2		T15	4		T6	1
valid_sources[0x4d]	834	1			T1	2		T13	2		T15	5
valid_sources[0x4e]	933	1			T1	5		T15	3		T27	3
valid_sources[0x4f]	864	1			T1	3		T13	2		T15	6
valid_sources[0x50]	1041	1			T1	1		T15	3		T6	1
valid_sources[0x51]	942	1			T15	2		T6	1		T27	6
valid_sources[0x52]	995	1			T5	1		T15	1		T6	1
valid_sources[0x53]	952	1			T5	1		T1	3		T15	3
valid_sources[0x54]	885	1			T1	3		T2	1		T6	1
valid_sources[0x55]	840	1			T1	3		T6	1		T7	1
valid_sources[0x56]	940	1			T5	1		T1	2		T17	1
valid_sources[0x57]	997	1			T13	1		T15	3		T17	1
valid_sources[0x58]	809	1			T5	1		T1	1		T13	1
valid_sources[0x59]	1014	1			T1	1		T15	4		T6	1
valid_sources[0x5a]	850	1			T15	1		T6	3		T23	1
valid_sources[0x5b]	897	1			T1	4		T15	1		T6	2
valid_sources[0x5c]	705	1			T1	1		T13	1		T6	2
valid_sources[0x5d]	1452	1			T1	2		T15	2		T17	1
valid_sources[0x5e]	1194	1			T1	2		T2	3		T16	6
valid_sources[0x5f]	1309	1			T1	2		T15	2		T6	3
valid_sources[0x60]	881	1			T1	1		T6	1		T24	1
valid_sources[0x61]	960	1			T1	5		T15	2		T17	2
valid_sources[0x62]	773	1			T1	1		T15	4		T17	4
valid_sources[0x63]	944	1			T1	1		T6	2		T9	1
valid_sources[0x64]	845	1			T5	2		T1	2		T15	1
valid_sources[0x65]	855	1			T1	1		T13	1		T15	2
valid_sources[0x66]	1882	1			T1	3		T15	1		T17	1
valid_sources[0x67]	692	1			T1	1		T15	1		T17	1
valid_sources[0x68]	1059	1			T1	2		T15	1		T6	1
valid_sources[0x69]	1203	1			T15	1		T6	1		T27	2
valid_sources[0x6a]	992	1			T1	2		T13	2		T6	1
valid_sources[0x6b]	925	1			T5	1		T15	1		T6	2
valid_sources[0x6c]	1150	1			T1	3		T13	1		T15	1
valid_sources[0x6d]	956	1			T1	3		T15	3		T17	1
valid_sources[0x6e]	836	1			T5	1		T1	2		T15	3
valid_sources[0x6f]	768	1			T1	2		T13	3		T6	1
valid_sources[0x70]	837	1			T1	1		T17	1		T6	1
valid_sources[0x71]	697	1			T1	1		T15	1		T17	2
valid_sources[0x72]	2060	1			T1	1		T15	3		T6	2
valid_sources[0x73]	789	1			T1	2		T15	1		T17	1
valid_sources[0x74]	843	1			T1	1		T13	3		T15	2
valid_sources[0x75]	868	1			T1	1		T15	1		T6	2
valid_sources[0x76]	890	1			T1	2		T13	3		T6	2
valid_sources[0x77]	1769	1			T5	1		T1	3		T6	1
valid_sources[0x78]	871	1			T1	3		T13	1		T15	1
valid_sources[0x79]	1055	1			T15	1		T6	1		T9	2
valid_sources[0x7a]	828	1			T1	2		T15	2		T17	1
valid_sources[0x7b]	905	1			T1	3		T6	1		T46	1
valid_sources[0x7c]	804	1			T1	1		T13	1		T15	1
valid_sources[0x7d]	1471	1			T1	1		T15	1		T6	3
valid_sources[0x7e]	845	1			T1	1		T13	1		T27	5
valid_sources[0x7f]	851	1			T5	1		T1	2		T13	1
valid_sources[0x80]	809	1			T4	1		T1	3		T15	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60801

1

T4

3

T5

24

T1

188

values[0x0]

all_enables

biggest_size

31060

1

T4

4

T1

32

T13

24

values[0x1]

all_enables

biggest_size

21625

1

T4

1

T1

9

T13

12