Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T13,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T13,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T13,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T9
1	0	Covered	T5,T1,T13
1	1	Covered	T4,T13,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T9
0	1	Covered	T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T9
0	1	Covered	T4,T13,T9
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T13,T9
1	-	Covered	T4,T13,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T13,T9
DetectSt	168	Covered	T4,T13,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T13,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T13,T9
DebounceSt->IdleSt	163	Covered	T135,T77,T136
DetectSt->IdleSt	186	Covered	T103
DetectSt->StableSt	191	Covered	T4,T13,T9
IdleSt->DebounceSt	148	Covered	T4,T13,T9
StableSt->IdleSt	206	Covered	T4,T13,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T13,T9
0	1	Covered	T4,T13,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T13,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T57
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T13,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T135,T136,T137
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T13,T9
DetectSt	-	-	-	-	1	-	-	Covered	T103
DetectSt	-	-	-	-	0	1	-	Covered	T4,T13,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T13,T9
StableSt	-	-	-	-	-	-	0	Covered	T4,T13,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	343	0	0
CntIncr_A	6869939	346135	0	0
CntNoWrap_A	6869939	6223097	0	0
DetectStDropOut_A	6869939	1	0	0
DetectedOut_A	6869939	1072	0	0
DetectedPulseOut_A	6869939	161	0	0
DisabledIdleSt_A	6869939	5869364	0	0
DisabledNoDetection_A	6869939	5871565	0	0
EnterDebounceSt_A	6869939	186	0	0
EnterDetectSt_A	6869939	162	0	0
EnterStableSt_A	6869939	161	0	0
PulseIsPulse_A	6869939	161	0	0
StayInStableSt	6869939	911	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	6962	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	160	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	343	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	6	0	0
T5	445	0	0	0
T9	0	4	0	0
T13	50321	10	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	6	0	0
T46	0	4	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	4	0	0
T51	0	2	0	0
T52	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	346135	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	175	0	0
T5	445	0	0	0
T9	0	41	0	0
T13	50321	47600	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	133	0	0
T46	0	162	0	0
T48	0	207	0	0
T49	0	61	0	0
T50	0	80	0	0
T51	0	57934	0	0
T52	0	163	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223097	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	306	0	0
T5	445	44	0	0
T13	50321	48307	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1	0	0
T103	711	1	0	0
T116	431	0	0	0
T117	422	0	0	0
T118	525	0	0	0
T119	521	0	0	0
T120	10289	0	0	0
T121	655	0	0	0
T122	502	0	0	0
T123	415	0	0	0
T124	778	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1072	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	20	0	0
T5	445	0	0	0
T9	0	11	0	0
T13	50321	35	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	21	0	0
T46	0	15	0	0
T48	0	22	0	0
T49	0	8	0	0
T50	0	11	0	0
T51	0	9	0	0
T52	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	161	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	3	0	0
T5	445	0	0	0
T9	0	2	0	0
T13	50321	5	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	3	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5869364	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	4	0	0
T5	445	44	0	0
T13	50321	518	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5871565	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	4	0	0
T5	445	45	0	0
T13	50321	521	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	186	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	3	0	0
T5	445	0	0	0
T9	0	2	0	0
T13	50321	5	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	3	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	162	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	3	0	0
T5	445	0	0	0
T9	0	2	0	0
T13	50321	5	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	3	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	161	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	3	0	0
T5	445	0	0	0
T9	0	2	0	0
T13	50321	5	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	3	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	161	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	3	0	0
T5	445	0	0	0
T9	0	2	0	0
T13	50321	5	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	3	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	911	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	17	0	0
T5	445	0	0	0
T9	0	9	0	0
T13	50321	30	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	18	0	0
T46	0	13	0	0
T48	0	19	0	0
T49	0	7	0	0
T50	0	9	0	0
T51	0	8	0	0
T52	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6962	0	0
T1	19091	7	0	0
T2	694	0	0	0
T3	746	1	0	0
T4	713	3	0	0
T5	445	8	0	0
T6	0	9	0	0
T13	50321	14	0	0
T14	422	2	0	0
T15	5016	20	0	0
T16	620	0	0	0
T17	505	5	0	0
T26	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	160	0	0
T1	19091	0	0	0
T2	694	0	0	0
T3	746	0	0	0
T4	713	3	0	0
T5	445	0	0	0
T9	0	2	0	0
T13	50321	5	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T42	0	3	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T9,T63,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T9
DetectSt	168	Covered	T7,T8,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T9
DebounceSt->IdleSt	163	Covered	T60,T63,T74
DetectSt->IdleSt	186	Covered	T9,T63,T89
DetectSt->StableSt	191	Covered	T7,T8,T9
IdleSt->DebounceSt	148	Covered	T7,T8,T9
StableSt->IdleSt	206	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T60,T63,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T63,T89
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	175	0	0
CntIncr_A	6869939	81696	0	0
CntNoWrap_A	6869939	6223265	0	0
DetectStDropOut_A	6869939	11	0	0
DetectedOut_A	6869939	310624	0	0
DetectedPulseOut_A	6869939	53	0	0
DisabledIdleSt_A	6869939	4740265	0	0
DisabledNoDetection_A	6869939	4742527	0	0
EnterDebounceSt_A	6869939	111	0	0
EnterDetectSt_A	6869939	64	0	0
EnterStableSt_A	6869939	53	0	0
PulseIsPulse_A	6869939	53	0	0
StayInStableSt	6869939	310571	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	6962	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_sticky_sva.StableStDropOut_A	6869939	1003954	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	175	0	0
T7	1006	4	0	0
T8	732	2	0	0
T9	506794	8	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	2	0	0
T59	0	4	0	0
T60	0	3	0	0
T63	0	3	0	0
T64	0	2	0	0
T65	522	0	0	0
T74	0	1	0	0
T75	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	81696	0	0
T7	1006	166	0	0
T8	732	11	0	0
T9	506794	263	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	64	0	0
T59	0	106	0	0
T60	0	34	0	0
T63	0	26	0	0
T64	0	94	0	0
T65	522	0	0	0
T74	0	62	0	0
T75	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223265	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	11	0	0
T9	506794	3	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T63	0	1	0	0
T89	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	310624	0	0
T7	1006	219	0	0
T8	732	46	0	0
T9	506794	469	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	480	0	0
T59	0	486	0	0
T60	0	36	0	0
T64	0	27	0	0
T65	522	0	0	0
T75	0	347	0	0
T76	0	139229	0	0
T109	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	53	0	0
T7	1006	2	0	0
T8	732	1	0	0
T9	506794	1	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T64	0	1	0	0
T65	522	0	0	0
T75	0	3	0	0
T76	0	3	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	4740265	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	4742527	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	111	0	0
T7	1006	2	0	0
T8	732	1	0	0
T9	506794	4	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	522	0	0	0
T74	0	1	0	0
T75	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	64	0	0
T7	1006	2	0	0
T8	732	1	0	0
T9	506794	4	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	522	0	0	0
T75	0	3	0	0
T76	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	53	0	0
T7	1006	2	0	0
T8	732	1	0	0
T9	506794	1	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T64	0	1	0	0
T65	522	0	0	0
T75	0	3	0	0
T76	0	3	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	53	0	0
T7	1006	2	0	0
T8	732	1	0	0
T9	506794	1	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T64	0	1	0	0
T65	522	0	0	0
T75	0	3	0	0
T76	0	3	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	310571	0	0
T7	1006	217	0	0
T8	732	45	0	0
T9	506794	468	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	479	0	0
T59	0	484	0	0
T60	0	35	0	0
T64	0	26	0	0
T65	522	0	0	0
T75	0	344	0	0
T76	0	139226	0	0
T109	0	100	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6962	0	0
T1	19091	7	0	0
T2	694	0	0	0
T3	746	1	0	0
T4	713	3	0	0
T5	445	8	0	0
T6	0	9	0	0
T13	50321	14	0	0
T14	422	2	0	0
T15	5016	20	0	0
T16	620	0	0	0
T17	505	5	0	0
T26	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1003954	0	0
T7	1006	139	0	0
T8	732	226	0	0
T9	506794	499836	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	175	0	0
T59	0	638	0	0
T60	0	236	0	0
T64	0	46	0	0
T65	522	0	0	0
T75	0	1370	0	0
T76	0	180	0	0
T109	0	161	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T13,T2
1	1	Covered	T5,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T13,T2
1	1	Covered	T7,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T8,T77,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T9
DetectSt	168	Covered	T7,T8,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T9
DebounceSt->IdleSt	163	Covered	T8,T58,T63
DetectSt->IdleSt	186	Covered	T8,T77,T88
DetectSt->StableSt	191	Covered	T7,T8,T9
IdleSt->DebounceSt	148	Covered	T7,T8,T9
StableSt->IdleSt	206	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T58,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T8,T77,T88
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	187	0	0
CntIncr_A	6869939	62904	0	0
CntNoWrap_A	6869939	6223253	0	0
DetectStDropOut_A	6869939	18	0	0
DetectedOut_A	6869939	458941	0	0
DetectedPulseOut_A	6869939	51	0	0
DisabledIdleSt_A	6869939	4740265	0	0
DisabledNoDetection_A	6869939	4742527	0	0
EnterDebounceSt_A	6869939	118	0	0
EnterDetectSt_A	6869939	69	0	0
EnterStableSt_A	6869939	51	0	0
PulseIsPulse_A	6869939	51	0	0
StayInStableSt	6869939	458890	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_sticky_sva.StableStDropOut_A	6869939	955622	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	187	0	0
T7	1006	4	0	0
T8	732	5	0	0
T9	506794	4	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	7	0	0
T59	0	4	0	0
T60	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	522	0	0	0
T74	0	2	0	0
T75	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	62904	0	0
T7	1006	146	0	0
T8	732	144	0	0
T9	506794	50396	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	247	0	0
T59	0	190	0	0
T60	0	39	0	0
T63	0	56	0	0
T64	0	56	0	0
T65	522	0	0	0
T74	0	59	0	0
T75	0	138	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223253	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	18	0	0
T8	732	1	0	0
T9	506794	0	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T65	522	0	0	0
T77	0	1	0	0
T81	0	1	0	0
T88	0	4	0	0
T141	0	3	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	458941	0	0
T7	1006	285	0	0
T8	732	51	0	0
T9	506794	449828	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	17	0	0
T59	0	892	0	0
T60	0	187	0	0
T65	522	0	0	0
T74	0	40	0	0
T75	0	608	0	0
T76	0	542	0	0
T109	0	149	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	51	0	0
T7	1006	2	0	0
T8	732	1	0	0
T9	506794	2	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T65	522	0	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	3	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	4740265	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	4742527	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	118	0	0
T7	1006	2	0	0
T8	732	3	0	0
T9	506794	2	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	6	0	0
T59	0	2	0	0
T60	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	522	0	0	0
T74	0	1	0	0
T75	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	69	0	0
T7	1006	2	0	0
T8	732	2	0	0
T9	506794	2	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T65	522	0	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	3	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	51	0	0
T7	1006	2	0	0
T8	732	1	0	0
T9	506794	2	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T65	522	0	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	3	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	51	0	0
T7	1006	2	0	0
T8	732	1	0	0
T9	506794	2	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T65	522	0	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	3	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	458890	0	0
T7	1006	283	0	0
T8	732	50	0	0
T9	506794	449826	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	16	0	0
T59	0	890	0	0
T60	0	186	0	0
T65	522	0	0	0
T74	0	39	0	0
T75	0	605	0	0
T76	0	539	0	0
T109	0	148	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	955622	0	0
T7	1006	91	0	0
T8	732	49	0	0
T9	506794	533	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	32	0	0
T59	0	153	0	0
T60	0	163	0	0
T65	522	0	0	0
T74	0	26	0	0
T75	0	1019	0	0
T76	0	167952	0	0
T109	0	84	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T1,T13
1	1	Covered	T7,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T59,T63
0	1	Covered	T8,T58,T74
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T59,T63
0	1	Unreachable
1	0	Covered	T7,T59,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T9
DetectSt	168	Covered	T7,T8,T58
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T59,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T58
DebounceSt->IdleSt	163	Covered	T9,T58,T60
DetectSt->IdleSt	186	Covered	T8,T58,T74
DetectSt->StableSt	191	Covered	T7,T59,T63
IdleSt->DebounceSt	148	Covered	T7,T8,T9
StableSt->IdleSt	206	Covered	T7,T59,T63

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T58
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T58,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T8,T58,T74
DetectSt	-	-	-	-	0	1	-	Covered	T7,T59,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T59,T63
StableSt	-	-	-	-	-	-	0	Covered	T7,T59,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	201	0	0
CntIncr_A	6869939	229087	0	0
CntNoWrap_A	6869939	6223239	0	0
DetectStDropOut_A	6869939	22	0	0
DetectedOut_A	6869939	356233	0	0
DetectedPulseOut_A	6869939	43	0	0
DisabledIdleSt_A	6869939	4740265	0	0
DisabledNoDetection_A	6869939	4742527	0	0
EnterDebounceSt_A	6869939	136	0	0
EnterDetectSt_A	6869939	65	0	0
EnterStableSt_A	6869939	43	0	0
PulseIsPulse_A	6869939	43	0	0
StayInStableSt	6869939	356190	0	0
gen_high_event_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_sticky_sva.StableStDropOut_A	6869939	384014	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	201	0	0
T7	1006	4	0	0
T8	732	8	0	0
T9	506794	8	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	10	0	0
T59	0	4	0	0
T60	0	4	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	522	0	0	0
T74	0	2	0	0
T75	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	229087	0	0
T7	1006	122	0	0
T8	732	212	0	0
T9	506794	623	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	278	0	0
T59	0	50	0	0
T60	0	104	0	0
T63	0	55	0	0
T64	0	42	0	0
T65	522	0	0	0
T74	0	28	0	0
T75	0	1023	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223239	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	22	0	0
T8	732	4	0	0
T9	506794	0	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	0	4	0	0
T65	522	0	0	0
T74	0	1	0	0
T77	0	3	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	356233	0	0
T7	1006	202	0	0
T8	732	0	0	0
T9	506794	0	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T59	0	217	0	0
T63	0	110	0	0
T65	522	0	0	0
T76	0	546	0	0
T77	0	741	0	0
T109	0	153	0	0
T131	0	589	0	0
T132	0	157	0	0
T133	0	336	0	0
T134	0	170	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	43	0	0
T7	1006	2	0	0
T8	732	0	0	0
T9	506794	0	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T59	0	2	0	0
T63	0	1	0	0
T65	522	0	0	0
T76	0	3	0	0
T77	0	2	0	0
T109	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	3	0	0
T134	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	4740265	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	4742527	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	136	0	0
T7	1006	2	0	0
T8	732	4	0	0
T9	506794	8	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	6	0	0
T59	0	2	0	0
T60	0	4	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	522	0	0	0
T74	0	1	0	0
T75	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	65	0	0
T7	1006	2	0	0
T8	732	4	0	0
T9	506794	0	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T58	0	4	0	0
T59	0	2	0	0
T63	0	1	0	0
T65	522	0	0	0
T74	0	1	0	0
T76	0	3	0	0
T109	0	1	0	0
T131	0	1	0	0
T146	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	43	0	0
T7	1006	2	0	0
T8	732	0	0	0
T9	506794	0	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T59	0	2	0	0
T63	0	1	0	0
T65	522	0	0	0
T76	0	3	0	0
T77	0	2	0	0
T109	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	3	0	0
T134	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	43	0	0
T7	1006	2	0	0
T8	732	0	0	0
T9	506794	0	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T59	0	2	0	0
T63	0	1	0	0
T65	522	0	0	0
T76	0	3	0	0
T77	0	2	0	0
T109	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	3	0	0
T134	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	356190	0	0
T7	1006	200	0	0
T8	732	0	0	0
T9	506794	0	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T59	0	215	0	0
T63	0	109	0	0
T65	522	0	0	0
T76	0	543	0	0
T77	0	739	0	0
T109	0	152	0	0
T131	0	588	0	0
T132	0	156	0	0
T133	0	333	0	0
T134	0	169	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	384014	0	0
T7	1006	219	0	0
T8	732	0	0	0
T9	506794	0	0	0
T23	499	0	0	0
T24	493	0	0	0
T25	2313	0	0	0
T27	4968	0	0	0
T54	411	0	0	0
T55	439	0	0	0
T59	0	979	0	0
T63	0	58	0	0
T65	522	0	0	0
T76	0	167973	0	0
T77	0	215	0	0
T109	0	102	0	0
T131	0	43	0	0
T132	0	96	0	0
T133	0	273	0	0
T134	0	349	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T86,T150
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T9,T39,T87
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T10
1	-	Covered	T9,T39,T87

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T10
DetectSt	168	Covered	T2,T9,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T10
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T86,T150
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T2,T9,T10
StableSt->IdleSt	206	Covered	T9,T39,T85

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T10
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T86,T150
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T39,T87
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	94	0	0
CntIncr_A	6869939	182605	0	0
CntNoWrap_A	6869939	6223346	0	0
DetectStDropOut_A	6869939	2	0	0
DetectedOut_A	6869939	3474	0	0
DetectedPulseOut_A	6869939	45	0	0
DisabledIdleSt_A	6869939	5826786	0	0
DisabledNoDetection_A	6869939	5828990	0	0
EnterDebounceSt_A	6869939	47	0	0
EnterDetectSt_A	6869939	47	0	0
EnterStableSt_A	6869939	45	0	0
PulseIsPulse_A	6869939	45	0	0
StayInStableSt	6869939	3406	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	94	0	0
T2	694	2	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	2	0	0
T39	0	6	0	0
T53	402	0	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	4	0	0
T151	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	182605	0	0
T2	694	91	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	36	0	0
T10	0	86	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	30	0	0
T39	0	135303	0	0
T53	402	0	0	0
T85	0	77	0	0
T86	0	15	0	0
T87	0	170	0	0
T151	0	82	0	0
T152	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223346	0	0
T1	19091	18665	0	0
T2	694	291	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2	0	0
T86	541	1	0	0
T87	1128	0	0	0
T150	0	1	0	0
T152	608	0	0	0
T153	12630	0	0	0
T154	490	0	0	0
T155	1332	0	0	0
T156	14859	0	0	0
T157	425	0	0	0
T158	498	0	0	0
T159	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3474	0	0
T2	694	48	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	42	0	0
T10	0	203	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	173	0	0
T39	0	120	0	0
T53	402	0	0	0
T76	0	165	0	0
T85	0	41	0	0
T87	0	357	0	0
T151	0	269	0	0
T152	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	45	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T53	402	0	0	0
T76	0	2	0	0
T85	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5826786	0	0
T1	19091	18665	0	0
T2	694	4	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5828990	0	0
T1	19091	18670	0	0
T2	694	4	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T53	402	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T53	402	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	45	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T53	402	0	0	0
T76	0	2	0	0
T85	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	45	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T53	402	0	0	0
T76	0	2	0	0
T85	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3406	0	0
T2	694	46	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	41	0	0
T10	0	201	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	171	0	0
T39	0	116	0	0
T53	402	0	0	0
T76	0	163	0	0
T85	0	39	0	0
T87	0	354	0	0
T151	0	267	0	0
T152	0	69	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	20	0	0
T9	506794	1	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T87	0	1	0	0
T152	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	1	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T5,T1,T13
1	1	Covered	T2,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T39,T82,T164
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T10
1	-	Covered	T2,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T10
DetectSt	168	Covered	T2,T9,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T10
DebounceSt->IdleSt	163	Covered	T85,T161,T82
DetectSt->IdleSt	186	Covered	T39,T82,T164
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T2,T9,T10
StableSt->IdleSt	206	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T161,T82
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T39,T82,T164
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	148	0	0
CntIncr_A	6869939	138762	0	0
CntNoWrap_A	6869939	6223292	0	0
DetectStDropOut_A	6869939	6	0	0
DetectedOut_A	6869939	21250	0	0
DetectedPulseOut_A	6869939	66	0	0
DisabledIdleSt_A	6869939	5920027	0	0
DisabledNoDetection_A	6869939	5922239	0	0
EnterDebounceSt_A	6869939	76	0	0
EnterDetectSt_A	6869939	72	0	0
EnterStableSt_A	6869939	66	0	0
PulseIsPulse_A	6869939	66	0	0
StayInStableSt	6869939	21158	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	2754	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	148	0	0
T2	694	2	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	6	0	0
T10	0	2	0	0
T11	0	4	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	6	0	0
T53	402	0	0	0
T85	0	1	0	0
T86	0	4	0	0
T152	0	4	0	0
T165	0	2	0	0
T166	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	138762	0	0
T2	694	91	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	101	0	0
T10	0	86	0	0
T11	0	78	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	135303	0	0
T53	402	0	0	0
T85	0	77	0	0
T86	0	30	0	0
T152	0	52	0	0
T165	0	45	0	0
T166	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223292	0	0
T1	19091	18665	0	0
T2	694	291	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6	0	0
T39	287320	2	0	0
T41	795	0	0	0
T45	27882	0	0	0
T62	519	0	0	0
T71	626	0	0	0
T72	7434	0	0	0
T82	0	1	0	0
T164	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	403	0	0	0
T170	405	0	0	0
T171	422	0	0	0
T172	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	21250	0	0
T2	694	53	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	105	0	0
T10	0	153	0	0
T11	0	80	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	16180	0	0
T53	402	0	0	0
T86	0	80	0	0
T152	0	49	0	0
T165	0	111	0	0
T166	0	84	0	0
T173	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	66	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	1	0	0
T53	402	0	0	0
T86	0	2	0	0
T152	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T173	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5920027	0	0
T1	19091	18665	0	0
T2	694	4	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5922239	0	0
T1	19091	18670	0	0
T2	694	4	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	76	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	3	0	0
T53	402	0	0	0
T85	0	1	0	0
T86	0	2	0	0
T152	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	72	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	3	0	0
T53	402	0	0	0
T86	0	2	0	0
T152	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T173	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	66	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	1	0	0
T53	402	0	0	0
T86	0	2	0	0
T152	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T173	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	66	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	1	0	0
T53	402	0	0	0
T86	0	2	0	0
T152	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T173	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	21158	0	0
T2	694	52	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	101	0	0
T10	0	152	0	0
T11	0	78	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	16179	0	0
T53	402	0	0	0
T86	0	77	0	0
T152	0	46	0	0
T165	0	110	0	0
T166	0	81	0	0
T173	0	105	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2754	0	0
T1	19091	0	0	0
T2	694	1	0	0
T3	746	1	0	0
T5	445	4	0	0
T13	50321	6	0	0
T14	422	3	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	6	0	0
T18	736	0	0	0
T23	0	7	0	0
T26	0	6	0	0
T54	0	1	0	0
T55	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	38	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	1	0	0
T53	402	0	0	0
T86	0	1	0	0
T152	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T173	0	1	0	0