Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T10,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T10,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T10,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T38
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T10,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T38
0	1	Covered	T3,T10,T38
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T38
1	-	Covered	T3,T10,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T38
DetectSt	168	Covered	T3,T10,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T38
DebounceSt->IdleSt	163	Covered	T41
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T10,T38
IdleSt->DebounceSt	148	Covered	T3,T10,T38
StableSt->IdleSt	206	Covered	T3,T10,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T38
0	1	Covered	T3,T10,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T41
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	95	0	0
CntIncr_A	6869939	47403	0	0
CntNoWrap_A	6869939	6223345	0	0
DetectStDropOut_A	6869939	0	0	0
DetectedOut_A	6869939	3085	0	0
DetectedPulseOut_A	6869939	47	0	0
DisabledIdleSt_A	6869939	5827304	0	0
DisabledNoDetection_A	6869939	5829513	0	0
EnterDebounceSt_A	6869939	48	0	0
EnterDetectSt_A	6869939	47	0	0
EnterStableSt_A	6869939	47	0	0
PulseIsPulse_A	6869939	47	0	0
StayInStableSt	6869939	3015	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	95	0	0
T3	746	2	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	4	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	2	0	0
T86	0	2	0	0
T137	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47403	0	0
T3	746	59	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	172	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	13	0	0
T39	0	45101	0	0
T40	0	93	0	0
T41	0	76	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	69	0	0
T86	0	15	0	0
T137	0	50	0	0
T151	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223345	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	343	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3085	0	0
T3	746	131	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	193	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	43	0	0
T39	0	39	0	0
T40	0	137	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	43	0	0
T86	0	39	0	0
T137	0	127	0	0
T151	0	142	0	0
T174	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	2	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T86	0	1	0	0
T137	0	1	0	0
T151	0	1	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5827304	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	4	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5829513	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	4	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	48	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	2	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T86	0	1	0	0
T137	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	2	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T86	0	1	0	0
T137	0	1	0	0
T151	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	2	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T86	0	1	0	0
T137	0	1	0	0
T151	0	1	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	2	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T86	0	1	0	0
T137	0	1	0	0
T151	0	1	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3015	0	0
T3	746	130	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	190	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	42	0	0
T39	0	38	0	0
T40	0	136	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	41	0	0
T86	0	37	0	0
T137	0	125	0	0
T151	0	140	0	0
T174	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	22	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T10	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T160	0	2	0	0
T166	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T5,T1,T13
1	1	Covered	T2,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T177
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T9,T10
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T9
1	-	Covered	T2,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T9
DetectSt	168	Covered	T2,T3,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T9
DebounceSt->IdleSt	163	Covered	T3,T40,T178
DetectSt->IdleSt	186	Covered	T177
DetectSt->StableSt	191	Covered	T2,T3,T9
IdleSt->DebounceSt	148	Covered	T2,T3,T9
StableSt->IdleSt	206	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T40,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T177
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	143	0	0
CntIncr_A	6869939	94256	0	0
CntNoWrap_A	6869939	6223297	0	0
DetectStDropOut_A	6869939	1	0	0
DetectedOut_A	6869939	157108	0	0
DetectedPulseOut_A	6869939	66	0	0
DisabledIdleSt_A	6869939	5817479	0	0
DisabledNoDetection_A	6869939	5819682	0	0
EnterDebounceSt_A	6869939	76	0	0
EnterDetectSt_A	6869939	67	0	0
EnterStableSt_A	6869939	66	0	0
PulseIsPulse_A	6869939	66	0	0
StayInStableSt	6869939	157015	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	3081	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	143	0	0
T2	694	2	0	0
T3	746	3	0	0
T6	10166	0	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	4	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	4	0	0
T40	0	3	0	0
T53	402	0	0	0
T71	0	2	0	0
T87	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	94256	0	0
T2	694	91	0	0
T3	746	118	0	0
T6	10166	0	0	0
T9	0	65	0	0
T10	0	172	0	0
T11	0	78	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	90202	0	0
T40	0	186	0	0
T53	402	0	0	0
T71	0	83	0	0
T87	0	85	0	0
T151	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223297	0	0
T1	19091	18665	0	0
T2	694	291	0	0
T3	746	342	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1	0	0
T143	1205	0	0	0
T149	1431	0	0	0
T177	3622	1	0	0
T179	35515	0	0	0
T180	500	0	0	0
T181	21738	0	0	0
T182	784	0	0	0
T183	4973	0	0	0
T184	504	0	0	0
T185	7335	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	157108	0	0
T2	694	53	0	0
T3	746	39	0	0
T6	10166	0	0	0
T9	0	25	0	0
T10	0	134	0	0
T11	0	110	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	151567	0	0
T40	0	41	0	0
T53	402	0	0	0
T71	0	50	0	0
T87	0	510	0	0
T151	0	183	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	66	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T71	0	1	0	0
T87	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5817479	0	0
T1	19091	18665	0	0
T2	694	4	0	0
T3	746	4	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5819682	0	0
T1	19091	18670	0	0
T2	694	4	0	0
T3	746	4	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	76	0	0
T2	694	1	0	0
T3	746	2	0	0
T6	10166	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T53	402	0	0	0
T71	0	1	0	0
T87	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	67	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T71	0	1	0	0
T87	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	66	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T71	0	1	0	0
T87	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	66	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T71	0	1	0	0
T87	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	157015	0	0
T2	694	52	0	0
T3	746	37	0	0
T6	10166	0	0	0
T9	0	23	0	0
T10	0	132	0	0
T11	0	108	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	151564	0	0
T40	0	39	0	0
T53	402	0	0	0
T71	0	48	0	0
T87	0	509	0	0
T151	0	182	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3081	0	0
T1	19091	0	0	0
T2	694	1	0	0
T3	746	2	0	0
T5	445	6	0	0
T13	50321	5	0	0
T14	422	4	0	0
T15	5016	0	0	0
T16	620	5	0	0
T17	505	6	0	0
T18	736	2	0	0
T19	0	3	0	0
T26	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T39	0	1	0	0
T53	402	0	0	0
T87	0	1	0	0
T137	0	1	0	0
T151	0	1	0	0
T166	0	2	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T13
1	1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T5,T1,T13
1	1	Covered	T3,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T166,T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T11
1	-	Covered	T3,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T11
DetectSt	168	Covered	T3,T9,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T11
DebounceSt->IdleSt	163	Covered	T166,T161,T187
DetectSt->IdleSt	186	Covered	T166,T186
DetectSt->StableSt	191	Covered	T3,T9,T11
IdleSt->DebounceSt	148	Covered	T3,T9,T11
StableSt->IdleSt	206	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T166,T161,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T166,T186
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	117	0	0
CntIncr_A	6869939	6536	0	0
CntNoWrap_A	6869939	6223323	0	0
DetectStDropOut_A	6869939	2	0	0
DetectedOut_A	6869939	8145	0	0
DetectedPulseOut_A	6869939	54	0	0
DisabledIdleSt_A	6869939	6202435	0	0
DisabledNoDetection_A	6869939	6204653	0	0
EnterDebounceSt_A	6869939	61	0	0
EnterDetectSt_A	6869939	56	0	0
EnterStableSt_A	6869939	54	0	0
PulseIsPulse_A	6869939	54	0	0
StayInStableSt	6869939	8069	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	117	0	0
T3	746	4	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	6	0	0
T11	0	2	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	4	0	0
T41	0	4	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	2	0	0
T76	0	8	0	0
T85	0	2	0	0
T151	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6536	0	0
T3	746	118	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	101	0	0
T11	0	39	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	60	0	0
T41	0	152	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	83	0	0
T76	0	218	0	0
T85	0	77	0	0
T151	0	82	0	0
T188	0	3534	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223323	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	341	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2	0	0
T166	820	1	0	0
T175	1555	0	0	0
T186	0	1	0	0
T189	405	0	0	0
T190	448	0	0	0
T191	4402	0	0	0
T192	640	0	0	0
T193	429	0	0	0
T194	423	0	0	0
T195	434	0	0	0
T196	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	8145	0	0
T3	746	127	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	124	0	0
T11	0	89	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	30	0	0
T41	0	115	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	50	0	0
T76	0	620	0	0
T85	0	1	0	0
T151	0	12	0	0
T188	0	4626	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T3	746	2	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	3	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	2	0	0
T41	0	2	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	1	0	0
T76	0	4	0	0
T85	0	1	0	0
T151	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6202435	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	4	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6204653	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	4	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	61	0	0
T3	746	2	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	3	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	2	0	0
T41	0	2	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	1	0	0
T76	0	4	0	0
T85	0	1	0	0
T151	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	56	0	0
T3	746	2	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	3	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	2	0	0
T41	0	2	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	1	0	0
T76	0	4	0	0
T85	0	1	0	0
T151	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T3	746	2	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	3	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	2	0	0
T41	0	2	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	1	0	0
T76	0	4	0	0
T85	0	1	0	0
T151	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T3	746	2	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	3	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	2	0	0
T41	0	2	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	1	0	0
T76	0	4	0	0
T85	0	1	0	0
T151	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	8069	0	0
T3	746	124	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	119	0	0
T11	0	88	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	28	0	0
T41	0	112	0	0
T53	402	0	0	0
T54	411	0	0	0
T71	0	48	0	0
T76	0	614	0	0
T151	0	11	0	0
T166	0	38	0	0
T188	0	4624	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	30	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	2	0	0
T41	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	2	0	0
T85	0	1	0	0
T151	0	1	0	0
T166	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T11,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T11,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T11,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T5,T1,T13
1	1	Covered	T10,T11,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T40
0	1	Covered	T40,T39,T37
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T40
1	-	Covered	T40,T39,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T40
DetectSt	168	Covered	T10,T11,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T11,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T40
DebounceSt->IdleSt	163	Covered	T168
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T11,T40
IdleSt->DebounceSt	148	Covered	T10,T11,T40
StableSt->IdleSt	206	Covered	T40,T39,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T40
0	1	Covered	T10,T11,T40
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T40
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T168
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T39,T37
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	79	0	0
CntIncr_A	6869939	46946	0	0
CntNoWrap_A	6869939	6223361	0	0
DetectStDropOut_A	6869939	0	0	0
DetectedOut_A	6869939	18971	0	0
DetectedPulseOut_A	6869939	39	0	0
DisabledIdleSt_A	6869939	5922519	0	0
DisabledNoDetection_A	6869939	5924735	0	0
EnterDebounceSt_A	6869939	40	0	0
EnterDetectSt_A	6869939	39	0	0
EnterStableSt_A	6869939	39	0	0
PulseIsPulse_A	6869939	39	0	0
StayInStableSt	6869939	18911	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	6639	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	79	0	0
T10	1083	2	0	0
T11	801	2	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	4	0	0
T38	620	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T86	0	4	0	0
T87	0	4	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	46946	0	0
T10	1083	86	0	0
T11	801	39	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	60	0	0
T38	620	0	0	0
T39	0	45101	0	0
T40	0	186	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	69	0	0
T86	0	30	0	0
T87	0	170	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	50	0	0
T152	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223361	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	18971	0	0
T10	1083	317	0	0
T11	801	104	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	82	0	0
T38	620	0	0	0
T39	0	16180	0	0
T40	0	82	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	67	0	0
T86	0	80	0	0
T87	0	166	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	128	0	0
T152	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	39	0	0
T10	1083	1	0	0
T11	801	1	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	1	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5922519	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5924735	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	40	0	0
T10	1083	1	0	0
T11	801	1	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	39	0	0
T10	1083	1	0	0
T11	801	1	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	1	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	39	0	0
T10	1083	1	0	0
T11	801	1	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	1	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	39	0	0
T10	1083	1	0	0
T11	801	1	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	1	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	18911	0	0
T10	1083	315	0	0
T11	801	102	0	0
T12	507	0	0	0
T28	7476	0	0	0
T37	0	79	0	0
T38	620	0	0	0
T39	0	16179	0	0
T40	0	79	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	66	0	0
T86	0	77	0	0
T87	0	164	0	0
T126	450	0	0	0
T127	425	0	0	0
T137	0	126	0	0
T152	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6639	0	0
T1	19091	12	0	0
T2	694	0	0	0
T3	746	1	0	0
T5	445	8	0	0
T6	0	14	0	0
T7	0	4	0	0
T13	50321	3	0	0
T14	422	4	0	0
T15	5016	20	0	0
T16	620	0	0	0
T17	505	4	0	0
T18	736	0	0	0
T26	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	16	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	813	1	0	0
T43	6337	0	0	0
T44	10265	0	0	0
T49	33866	0	0	0
T60	2282	0	0	0
T76	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T152	0	1	0	0
T174	0	2	0	0
T178	0	1	0	0
T197	0	1	0	0
T198	421	0	0	0
T199	523	0	0	0
T200	505	0	0	0
T201	407	0	0	0
T202	425	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T13
1	1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T38,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T38,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T38,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T38,T40
1	0	Covered	T5,T1,T13
1	1	Covered	T10,T38,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T38,T40
0	1	Covered	T85,T192,T163
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T38,T40
0	1	Covered	T10,T38,T40
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T38,T40
1	-	Covered	T10,T38,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T38,T40
DetectSt	168	Covered	T10,T38,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T38,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T38,T40
DebounceSt->IdleSt	163	Covered	T38,T176,T203
DetectSt->IdleSt	186	Covered	T85,T192,T163
DetectSt->StableSt	191	Covered	T10,T38,T40
IdleSt->DebounceSt	148	Covered	T10,T38,T40
StableSt->IdleSt	206	Covered	T10,T38,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T38,T40
0	1	Covered	T10,T38,T40
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T38,T40
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T38,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T38,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T176,T203
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T38,T40
DetectSt	-	-	-	-	1	-	-	Covered	T85,T192,T163
DetectSt	-	-	-	-	0	1	-	Covered	T10,T38,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T38,T40
StableSt	-	-	-	-	-	-	0	Covered	T10,T38,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	136	0	0
CntIncr_A	6869939	94040	0	0
CntNoWrap_A	6869939	6223304	0	0
DetectStDropOut_A	6869939	6	0	0
DetectedOut_A	6869939	20240	0	0
DetectedPulseOut_A	6869939	60	0	0
DisabledIdleSt_A	6869939	5828299	0	0
DisabledNoDetection_A	6869939	5830508	0	0
EnterDebounceSt_A	6869939	70	0	0
EnterDetectSt_A	6869939	66	0	0
EnterStableSt_A	6869939	60	0	0
PulseIsPulse_A	6869939	60	0	0
StayInStableSt	6869939	20160	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	136	0	0
T10	1083	2	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	3	0	0
T39	0	4	0	0
T40	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	2	0	0
T76	0	4	0	0
T85	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	2	0	0
T165	0	2	0	0
T204	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	94040	0	0
T10	1083	86	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	26	0	0
T39	0	90202	0	0
T40	0	93	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	83	0	0
T76	0	80	0	0
T85	0	77	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	82	0	0
T165	0	45	0	0
T204	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223304	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6	0	0
T85	18922	1	0	0
T92	12405	0	0	0
T125	28949	0	0	0
T151	1805	0	0	0
T163	0	1	0	0
T167	0	1	0	0
T192	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	410	0	0	0
T208	404	0	0	0
T209	515	0	0	0
T210	494	0	0	0
T211	733	0	0	0
T212	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	20240	0	0
T10	1083	428	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	60	0	0
T39	0	16181	0	0
T40	0	138	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	49	0	0
T76	0	163	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	13	0	0
T165	0	228	0	0
T204	0	97	0	0
T213	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	60	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	1	0	0
T76	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	1	0	0
T165	0	1	0	0
T204	0	1	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5828299	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5830508	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	70	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	1	0	0
T76	0	2	0	0
T85	0	1	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	1	0	0
T165	0	1	0	0
T204	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	66	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	1	0	0
T76	0	2	0	0
T85	0	1	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	1	0	0
T165	0	1	0	0
T204	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	60	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	1	0	0
T76	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	1	0	0
T165	0	1	0	0
T204	0	1	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	60	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	1	0	0
T76	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	1	0	0
T165	0	1	0	0
T204	0	1	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	20160	0	0
T10	1083	427	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	59	0	0
T39	0	16179	0	0
T40	0	137	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T71	0	47	0	0
T76	0	161	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	12	0	0
T165	0	226	0	0
T204	0	95	0	0
T213	0	97	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	38	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T10,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T10,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T10,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T5,T1,T13
1	1	Covered	T9,T10,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T39
0	1	Covered	T39,T137,T174
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T39
1	-	Covered	T39,T137,T174

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T10,T39
DetectSt	168	Covered	T9,T10,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T10,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T39
DebounceSt->IdleSt	163	Covered	T162,T164,T215
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T10,T39
IdleSt->DebounceSt	148	Covered	T9,T10,T39
StableSt->IdleSt	206	Covered	T9,T39,T76

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T10,T39
0	1	Covered	T9,T10,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T10,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T162,T164,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T10,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T137,T174
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	77	0	0
CntIncr_A	6869939	92145	0	0
CntNoWrap_A	6869939	6223363	0	0
DetectStDropOut_A	6869939	0	0	0
DetectedOut_A	6869939	92219	0	0
DetectedPulseOut_A	6869939	37	0	0
DisabledIdleSt_A	6869939	5921924	0	0
DisabledNoDetection_A	6869939	5924139	0	0
EnterDebounceSt_A	6869939	40	0	0
EnterDetectSt_A	6869939	37	0	0
EnterStableSt_A	6869939	37	0	0
PulseIsPulse_A	6869939	37	0	0
StayInStableSt	6869939	92160	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	6234	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	77	0	0
T9	506794	2	0	0
T10	1083	2	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	4	0	0
T41	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T137	0	2	0	0
T160	0	4	0	0
T174	0	4	0	0
T175	0	2	0	0
T192	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	92145	0	0
T9	506794	36	0	0
T10	1083	86	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	90202	0	0
T41	0	76	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	69	0	0
T137	0	50	0	0
T160	0	116	0	0
T174	0	55	0	0
T175	0	15	0	0
T192	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223363	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	92219	0	0
T9	506794	41	0	0
T10	1083	72	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	90323	0	0
T41	0	110	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	43	0	0
T137	0	40	0	0
T160	0	86	0	0
T174	0	85	0	0
T175	0	4	0	0
T192	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T9	506794	1	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T137	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T175	0	1	0	0
T192	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5921924	0	0
T1	19091	18665	0	0
T2	694	4	0	0
T3	746	4	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5924139	0	0
T1	19091	18670	0	0
T2	694	4	0	0
T3	746	4	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	40	0	0
T9	506794	1	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T137	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T175	0	1	0	0
T192	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T9	506794	1	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T137	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T175	0	1	0	0
T192	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T9	506794	1	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T137	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T175	0	1	0	0
T192	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T9	506794	1	0	0
T10	1083	1	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T137	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T175	0	1	0	0
T192	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	92160	0	0
T9	506794	39	0	0
T10	1083	70	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T39	0	90320	0	0
T41	0	108	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	41	0	0
T137	0	39	0	0
T160	0	83	0	0
T174	0	82	0	0
T175	0	3	0	0
T192	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6234	0	0
T1	19091	7	0	0
T2	694	0	0	0
T3	746	0	0	0
T5	445	7	0	0
T6	0	13	0	0
T13	50321	4	0	0
T14	422	1	0	0
T15	5016	24	0	0
T16	620	0	0	0
T17	505	7	0	0
T18	736	0	0	0
T23	0	7	0	0
T26	0	5	0	0
T27	0	17	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	13	0	0
T39	287320	1	0	0
T41	795	0	0	0
T45	27882	0	0	0
T62	519	0	0	0
T71	626	0	0	0
T72	7434	0	0	0
T137	0	1	0	0
T160	0	1	0	0
T162	0	2	0	0
T169	403	0	0	0
T170	405	0	0	0
T171	422	0	0	0
T172	505	0	0	0
T174	0	1	0	0
T175	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0