Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T13
1	1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T5,T1,T13
1	1	Covered	T3,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T9,T10,T11
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T10
1	-	Covered	T9,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T10
DetectSt	168	Covered	T3,T9,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T10
DebounceSt->IdleSt	163	Covered	T3,T10,T38
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T9,T10
IdleSt->DebounceSt	148	Covered	T3,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T10
0	1	Covered	T3,T9,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T10,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	114	0	0
CntIncr_A	6869939	2896	0	0
CntNoWrap_A	6869939	6223326	0	0
DetectStDropOut_A	6869939	0	0	0
DetectedOut_A	6869939	3741	0	0
DetectedPulseOut_A	6869939	54	0	0
DisabledIdleSt_A	6869939	6210337	0	0
DisabledNoDetection_A	6869939	6212557	0	0
EnterDebounceSt_A	6869939	60	0	0
EnterDetectSt_A	6869939	54	0	0
EnterStableSt_A	6869939	54	0	0
PulseIsPulse_A	6869939	54	0	0
StayInStableSt	6869939	3666	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	114	0	0
T3	746	3	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	4	0	0
T10	0	3	0	0
T11	0	2	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	2	0	0
T38	0	5	0	0
T40	0	2	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	2	0	0
T137	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2896	0	0
T3	746	118	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	72	0	0
T10	0	172	0	0
T11	0	39	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	30	0	0
T38	0	39	0	0
T40	0	93	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	77	0	0
T137	0	50	0	0
T165	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223326	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	342	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3741	0	0
T3	746	38	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	120	0	0
T10	0	298	0	0
T11	0	271	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	39	0	0
T38	0	11	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	119	0	0
T137	0	31	0	0
T165	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	1	0	0
T137	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6210337	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	4	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6212557	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	4	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	60	0	0
T3	746	2	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	1	0	0
T137	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	1	0	0
T137	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	1	0	0
T137	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	1	0	0
T137	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3666	0	0
T3	746	36	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T9	0	117	0	0
T10	0	297	0	0
T11	0	270	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	37	0	0
T38	0	9	0	0
T53	402	0	0	0
T54	411	0	0	0
T85	0	117	0	0
T137	0	30	0	0
T165	0	41	0	0
T174	0	71	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	31	0	0
T9	506794	1	0	0
T10	1083	1	0	0
T11	801	1	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	2	0	0
T40	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T137	0	1	0	0
T173	0	2	0	0
T174	0	3	0	0
T175	0	2	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T11,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T5,T1,T13
1	1	Covered	T3,T11,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T38
0	1	Covered	T39
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T38
0	1	Covered	T3,T38,T87
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T38
1	-	Covered	T3,T38,T87

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T38
DetectSt	168	Covered	T3,T11,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T11,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T38
DebounceSt->IdleSt	163	Covered	T173,T185
DetectSt->IdleSt	186	Covered	T39
DetectSt->StableSt	191	Covered	T3,T11,T38
IdleSt->DebounceSt	148	Covered	T3,T11,T38
StableSt->IdleSt	206	Covered	T3,T38,T87

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T38
0	1	Covered	T3,T11,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T173,T185
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T38
DetectSt	-	-	-	-	1	-	-	Covered	T39
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T38,T87
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	100	0	0
CntIncr_A	6869939	47690	0	0
CntNoWrap_A	6869939	6223340	0	0
DetectStDropOut_A	6869939	1	0	0
DetectedOut_A	6869939	3427	0	0
DetectedPulseOut_A	6869939	48	0	0
DisabledIdleSt_A	6869939	5910211	0	0
DisabledNoDetection_A	6869939	5912418	0	0
EnterDebounceSt_A	6869939	51	0	0
EnterDetectSt_A	6869939	49	0	0
EnterStableSt_A	6869939	48	0	0
PulseIsPulse_A	6869939	48	0	0
StayInStableSt	6869939	3354	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	6262	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	100	0	0
T3	746	2	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	2	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	6	0	0
T39	0	2	0	0
T41	0	2	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	2	0	0
T87	0	4	0	0
T151	0	2	0	0
T166	0	4	0	0
T174	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47690	0	0
T3	746	59	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	39	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	39	0	0
T39	0	45101	0	0
T41	0	76	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	69	0	0
T87	0	170	0	0
T151	0	82	0	0
T166	0	90	0	0
T174	0	121	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223340	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	343	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1	0	0
T39	287320	1	0	0
T41	795	0	0	0
T45	27882	0	0	0
T62	519	0	0	0
T71	626	0	0	0
T72	7434	0	0	0
T169	403	0	0	0
T170	405	0	0	0
T171	422	0	0	0
T172	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3427	0	0
T3	746	131	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	42	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	129	0	0
T41	0	46	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	42	0	0
T87	0	104	0	0
T151	0	47	0	0
T166	0	220	0	0
T173	0	6	0	0
T174	0	267	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	48	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0
T173	0	1	0	0
T174	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5910211	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	4	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5912418	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	4	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	51	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0
T174	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	49	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0
T174	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	48	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0
T173	0	1	0	0
T174	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	48	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	1	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0
T173	0	1	0	0
T174	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3354	0	0
T3	746	130	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T11	0	40	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	125	0	0
T41	0	44	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	40	0	0
T87	0	101	0	0
T151	0	45	0	0
T166	0	217	0	0
T173	0	5	0	0
T174	0	261	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6262	0	0
T1	19091	9	0	0
T2	694	1	0	0
T3	746	1	0	0
T5	445	7	0	0
T6	0	9	0	0
T13	50321	5	0	0
T14	422	2	0	0
T15	5016	23	0	0
T16	620	0	0	0
T17	505	6	0	0
T18	736	0	0	0
T26	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	21	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T38	0	2	0	0
T53	402	0	0	0
T54	411	0	0	0
T87	0	1	0	0
T164	0	1	0	0
T166	0	1	0	0
T173	0	1	0	0
T174	0	2	0	0
T187	0	1	0	0
T197	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T13
1	1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T38,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T38,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T38,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T38,T41
1	0	Covered	T5,T1,T13
1	1	Covered	T9,T38,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T41
0	1	Covered	T87,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T41
0	1	Covered	T41,T37,T87
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T38,T41
1	-	Covered	T41,T37,T87

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T38,T41
DetectSt	168	Covered	T9,T38,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T38,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T38,T41
DebounceSt->IdleSt	163	Covered	T38,T76,T203
DetectSt->IdleSt	186	Covered	T87,T206
DetectSt->StableSt	191	Covered	T9,T38,T41
IdleSt->DebounceSt	148	Covered	T9,T38,T41
StableSt->IdleSt	206	Covered	T9,T41,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T38,T41
0	1	Covered	T9,T38,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T38,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T38,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T38,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T76,T203
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T38,T41
DetectSt	-	-	-	-	1	-	-	Covered	T87,T206
DetectSt	-	-	-	-	0	1	-	Covered	T9,T38,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T37,T87
StableSt	-	-	-	-	-	-	0	Covered	T9,T38,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	105	0	0
CntIncr_A	6869939	2871	0	0
CntNoWrap_A	6869939	6223335	0	0
DetectStDropOut_A	6869939	2	0	0
DetectedOut_A	6869939	4302	0	0
DetectedPulseOut_A	6869939	49	0	0
DisabledIdleSt_A	6869939	6210518	0	0
DisabledNoDetection_A	6869939	6212742	0	0
EnterDebounceSt_A	6869939	54	0	0
EnterDetectSt_A	6869939	51	0	0
EnterStableSt_A	6869939	49	0	0
PulseIsPulse_A	6869939	49	0	0
StayInStableSt	6869939	4227	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	105	0	0
T9	506794	2	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	4	0	0
T38	620	3	0	0
T41	0	4	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	7	0	0
T87	0	4	0	0
T152	0	2	0	0
T178	0	2	0	0
T214	0	2	0	0
T219	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2871	0	0
T9	506794	29	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	60	0	0
T38	620	26	0	0
T41	0	152	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	218	0	0
T87	0	170	0	0
T152	0	26	0	0
T178	0	75	0	0
T214	0	13	0	0
T219	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223335	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2	0	0
T87	1128	1	0	0
T152	608	0	0	0
T153	12630	0	0	0
T154	490	0	0	0
T155	1332	0	0	0
T156	14859	0	0	0
T157	425	0	0	0
T158	498	0	0	0
T159	505	0	0	0
T206	0	1	0	0
T220	688	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	4302	0	0
T9	506794	41	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	41	0	0
T38	620	116	0	0
T41	0	86	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	436	0	0
T87	0	65	0	0
T152	0	143	0	0
T178	0	281	0	0
T214	0	68	0	0
T219	0	134	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	49	0	0
T9	506794	1	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	1	0	0
T41	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	3	0	0
T87	0	1	0	0
T152	0	1	0	0
T178	0	1	0	0
T214	0	1	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6210518	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6212742	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T9	506794	1	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	2	0	0
T41	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	4	0	0
T87	0	2	0	0
T152	0	1	0	0
T178	0	1	0	0
T214	0	1	0	0
T219	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	51	0	0
T9	506794	1	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	1	0	0
T41	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	3	0	0
T87	0	2	0	0
T152	0	1	0	0
T178	0	1	0	0
T214	0	1	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	49	0	0
T9	506794	1	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	1	0	0
T41	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	3	0	0
T87	0	1	0	0
T152	0	1	0	0
T178	0	1	0	0
T214	0	1	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	49	0	0
T9	506794	1	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	1	0	0
T41	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	3	0	0
T87	0	1	0	0
T152	0	1	0	0
T178	0	1	0	0
T214	0	1	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	4227	0	0
T9	506794	39	0	0
T10	1083	0	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	38	0	0
T38	620	114	0	0
T41	0	83	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	432	0	0
T87	0	64	0	0
T152	0	141	0	0
T178	0	279	0	0
T214	0	67	0	0
T219	0	132	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	21	0	0
T37	0	1	0	0
T41	795	1	0	0
T63	1086	0	0	0
T67	491	0	0	0
T68	1810	0	0	0
T69	499	0	0	0
T73	5216	0	0	0
T76	0	2	0	0
T82	0	1	0	0
T87	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	1	0	0
T165	683	0	0	0
T214	0	1	0	0
T218	0	1	0	0
T221	422	0	0	0
T222	427	0	0	0
T223	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T5,T1,T13
1	1	Covered	T2,T3,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T38
0	1	Covered	T167
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T38
0	1	Covered	T3,T38,T37
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T38
1	-	Covered	T3,T38,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T38
DetectSt	168	Covered	T2,T3,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T3,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T38
DebounceSt->IdleSt	163	Covered	T173,T164
DetectSt->IdleSt	186	Covered	T167
DetectSt->StableSt	191	Covered	T2,T3,T38
IdleSt->DebounceSt	148	Covered	T2,T3,T38
StableSt->IdleSt	206	Covered	T3,T38,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T38
0	1	Covered	T2,T3,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T173,T164
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T38
DetectSt	-	-	-	-	1	-	-	Covered	T167
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T38,T37
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	78	0	0
CntIncr_A	6869939	1970	0	0
CntNoWrap_A	6869939	6223362	0	0
DetectStDropOut_A	6869939	1	0	0
DetectedOut_A	6869939	2454	0	0
DetectedPulseOut_A	6869939	37	0	0
DisabledIdleSt_A	6869939	6205324	0	0
DisabledNoDetection_A	6869939	6207535	0	0
EnterDebounceSt_A	6869939	40	0	0
EnterDetectSt_A	6869939	38	0	0
EnterStableSt_A	6869939	37	0	0
PulseIsPulse_A	6869939	37	0	0
StayInStableSt	6869939	2401	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	6298	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	78	0	0
T2	694	2	0	0
T3	746	2	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T53	402	0	0	0
T76	0	6	0	0
T87	0	4	0	0
T166	0	4	0	0
T173	0	3	0	0
T174	0	4	0	0
T214	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1970	0	0
T2	694	91	0	0
T3	746	59	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	30	0	0
T38	0	13	0	0
T53	402	0	0	0
T76	0	149	0	0
T87	0	170	0	0
T166	0	90	0	0
T173	0	32	0	0
T174	0	66	0	0
T214	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223362	0	0
T1	19091	18665	0	0
T2	694	291	0	0
T3	746	343	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1	0	0
T104	36105	0	0	0
T105	21678	0	0	0
T167	697	1	0	0
T224	35795	0	0	0
T225	685	0	0	0
T226	16790	0	0	0
T227	405	0	0	0
T228	436	0	0	0
T229	878	0	0	0
T230	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2454	0	0
T2	694	48	0	0
T3	746	31	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	102	0	0
T38	0	65	0	0
T53	402	0	0	0
T76	0	198	0	0
T87	0	78	0	0
T166	0	84	0	0
T173	0	62	0	0
T174	0	81	0	0
T214	0	56	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T53	402	0	0	0
T76	0	3	0	0
T87	0	2	0	0
T166	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0
T214	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6205324	0	0
T1	19091	18665	0	0
T2	694	4	0	0
T3	746	4	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6207535	0	0
T1	19091	18670	0	0
T2	694	4	0	0
T3	746	4	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	40	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T53	402	0	0	0
T76	0	3	0	0
T87	0	2	0	0
T166	0	2	0	0
T173	0	2	0	0
T174	0	2	0	0
T214	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	38	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T53	402	0	0	0
T76	0	3	0	0
T87	0	2	0	0
T166	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0
T214	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T53	402	0	0	0
T76	0	3	0	0
T87	0	2	0	0
T166	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0
T214	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T2	694	1	0	0
T3	746	1	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T53	402	0	0	0
T76	0	3	0	0
T87	0	2	0	0
T166	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0
T214	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2401	0	0
T2	694	46	0	0
T3	746	30	0	0
T6	10166	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T37	0	101	0	0
T38	0	64	0	0
T53	402	0	0	0
T76	0	194	0	0
T87	0	75	0	0
T166	0	81	0	0
T173	0	61	0	0
T174	0	78	0	0
T214	0	54	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6298	0	0
T1	19091	11	0	0
T2	694	1	0	0
T3	746	1	0	0
T5	445	4	0	0
T6	0	13	0	0
T13	50321	6	0	0
T14	422	4	0	0
T15	5016	30	0	0
T16	620	0	0	0
T17	505	4	0	0
T18	736	0	0	0
T26	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	19	0	0
T3	746	1	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T23	499	0	0	0
T26	502	0	0	0
T27	4968	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T53	402	0	0	0
T54	411	0	0	0
T76	0	2	0	0
T87	0	1	0	0
T164	0	1	0	0
T166	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T216	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T10,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T38
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T10,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T38
0	1	Covered	T173,T206,T150
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T38
0	1	Covered	T10,T38,T151
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T38
1	-	Covered	T10,T38,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T38
DetectSt	168	Covered	T2,T10,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T38
DebounceSt->IdleSt	163	Covered	T10,T38
DetectSt->IdleSt	186	Covered	T173,T206,T150
DetectSt->StableSt	191	Covered	T2,T10,T38
IdleSt->DebounceSt	148	Covered	T2,T10,T38
StableSt->IdleSt	206	Covered	T10,T38,T85

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T38
0	1	Covered	T2,T10,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T38
DetectSt	-	-	-	-	1	-	-	Covered	T173,T206,T150
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T38,T151
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	106	0	0
CntIncr_A	6869939	47678	0	0
CntNoWrap_A	6869939	6223334	0	0
DetectStDropOut_A	6869939	3	0	0
DetectedOut_A	6869939	3600	0	0
DetectedPulseOut_A	6869939	49	0	0
DisabledIdleSt_A	6869939	6119663	0	0
DisabledNoDetection_A	6869939	6121885	0	0
EnterDebounceSt_A	6869939	54	0	0
EnterDetectSt_A	6869939	52	0	0
EnterStableSt_A	6869939	49	0	0
PulseIsPulse_A	6869939	49	0	0
StayInStableSt	6869939	3530	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	106	0	0
T2	694	2	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	5	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	3	0	0
T40	0	2	0	0
T53	402	0	0	0
T85	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T174	0	4	0	0
T175	0	4	0	0
T192	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47678	0	0
T2	694	91	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	258	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	26	0	0
T40	0	93	0	0
T53	402	0	0	0
T85	0	77	0	0
T151	0	82	0	0
T152	0	26	0	0
T174	0	44	0	0
T175	0	30	0	0
T192	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223334	0	0
T1	19091	18665	0	0
T2	694	291	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3	0	0
T88	1474	0	0	0
T138	3264	0	0	0
T147	795	0	0	0
T150	0	1	0	0
T173	633	1	0	0
T206	0	1	0	0
T231	493	0	0	0
T232	16062	0	0	0
T233	439	0	0	0
T234	18552	0	0	0
T235	13596	0	0	0
T236	12416	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3600	0	0
T2	694	48	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	84	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	3	0	0
T40	0	41	0	0
T53	402	0	0	0
T85	0	40	0	0
T151	0	57	0	0
T152	0	4	0	0
T174	0	88	0	0
T175	0	132	0	0
T192	0	138	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	49	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T85	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T175	0	2	0	0
T192	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6119663	0	0
T1	19091	18665	0	0
T2	694	4	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6121885	0	0
T1	19091	18670	0	0
T2	694	4	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	3	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T53	402	0	0	0
T85	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T175	0	2	0	0
T192	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	52	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T85	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T175	0	2	0	0
T192	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	49	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T85	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T175	0	2	0	0
T192	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	49	0	0
T2	694	1	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	2	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T53	402	0	0	0
T85	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T175	0	2	0	0
T192	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3530	0	0
T2	694	46	0	0
T3	746	0	0	0
T6	10166	0	0	0
T10	0	82	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T38	0	2	0	0
T40	0	39	0	0
T53	402	0	0	0
T85	0	38	0	0
T151	0	56	0	0
T152	0	3	0	0
T174	0	85	0	0
T175	0	129	0	0
T192	0	136	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	26	0	0
T10	1083	2	0	0
T11	801	0	0	0
T12	507	0	0	0
T28	7476	0	0	0
T38	620	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T126	450	0	0	0
T127	425	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T160	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T10,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T10,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T10,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T9,T10,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T37
0	1	Covered	T39,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T37
0	1	Covered	T9,T10,T76
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T37
1	-	Covered	T9,T10,T76

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T10,T39
DetectSt	168	Covered	T9,T10,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T10,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T39
DebounceSt->IdleSt	163	Covered	T185,T168
DetectSt->IdleSt	186	Covered	T39,T81
DetectSt->StableSt	191	Covered	T9,T10,T37
IdleSt->DebounceSt	148	Covered	T9,T10,T39
StableSt->IdleSt	206	Covered	T9,T10,T76

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T10,T39
0	1	Covered	T9,T10,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T10,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T185,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T10,T39
DetectSt	-	-	-	-	1	-	-	Covered	T39,T81
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T76
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	72	0	0
CntIncr_A	6869939	47189	0	0
CntNoWrap_A	6869939	6223368	0	0
DetectStDropOut_A	6869939	2	0	0
DetectedOut_A	6869939	2363	0	0
DetectedPulseOut_A	6869939	33	0	0
DisabledIdleSt_A	6869939	5914223	0	0
DisabledNoDetection_A	6869939	5916443	0	0
EnterDebounceSt_A	6869939	37	0	0
EnterDetectSt_A	6869939	35	0	0
EnterStableSt_A	6869939	33	0	0
PulseIsPulse_A	6869939	33	0	0
StayInStableSt	6869939	2313	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6869939	6962	0	0
gen_low_level_sva.LowLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	72	0	0
T9	506794	2	0	0
T10	1083	6	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	2	0	0
T38	620	0	0	0
T39	0	2	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	4	0	0
T137	0	2	0	0
T173	0	4	0	0
T214	0	2	0	0
T219	0	2	0	0
T237	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	47189	0	0
T9	506794	36	0	0
T10	1083	258	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	30	0	0
T38	620	0	0	0
T39	0	45101	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	80	0	0
T137	0	50	0	0
T173	0	32	0	0
T214	0	13	0	0
T219	0	96	0	0
T237	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6223368	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2	0	0
T39	287320	1	0	0
T41	795	0	0	0
T45	27882	0	0	0
T62	519	0	0	0
T71	626	0	0	0
T72	7434	0	0	0
T81	0	1	0	0
T169	403	0	0	0
T170	405	0	0	0
T171	422	0	0	0
T172	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2363	0	0
T9	506794	102	0	0
T10	1083	125	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	39	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	81	0	0
T137	0	128	0	0
T173	0	112	0	0
T176	0	171	0	0
T214	0	53	0	0
T219	0	37	0	0
T237	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	33	0	0
T9	506794	1	0	0
T10	1083	3	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	1	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T137	0	1	0	0
T173	0	2	0	0
T176	0	1	0	0
T214	0	1	0	0
T219	0	1	0	0
T237	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5914223	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5916443	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	37	0	0
T9	506794	1	0	0
T10	1083	3	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	1	0	0
T38	620	0	0	0
T39	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T137	0	1	0	0
T173	0	2	0	0
T214	0	1	0	0
T219	0	1	0	0
T237	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	35	0	0
T9	506794	1	0	0
T10	1083	3	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	1	0	0
T38	620	0	0	0
T39	0	1	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T137	0	1	0	0
T173	0	2	0	0
T214	0	1	0	0
T219	0	1	0	0
T237	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	33	0	0
T9	506794	1	0	0
T10	1083	3	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	1	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T137	0	1	0	0
T173	0	2	0	0
T176	0	1	0	0
T214	0	1	0	0
T219	0	1	0	0
T237	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	33	0	0
T9	506794	1	0	0
T10	1083	3	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	1	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	2	0	0
T137	0	1	0	0
T173	0	2	0	0
T176	0	1	0	0
T214	0	1	0	0
T219	0	1	0	0
T237	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2313	0	0
T9	506794	101	0	0
T10	1083	121	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T37	0	37	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	78	0	0
T137	0	126	0	0
T173	0	109	0	0
T176	0	170	0	0
T214	0	52	0	0
T219	0	35	0	0
T237	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6962	0	0
T1	19091	7	0	0
T2	694	0	0	0
T3	746	1	0	0
T4	713	3	0	0
T5	445	8	0	0
T6	0	9	0	0
T13	50321	14	0	0
T14	422	2	0	0
T15	5016	20	0	0
T16	620	0	0	0
T17	505	5	0	0
T26	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	14	0	0
T9	506794	1	0	0
T10	1083	2	0	0
T11	801	0	0	0
T12	507	0	0	0
T25	2313	0	0	0
T28	7476	0	0	0
T38	620	0	0	0
T42	10668	0	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T76	0	1	0	0
T82	0	1	0	0
T120	0	1	0	0
T173	0	1	0	0
T176	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0
T237	0	1	0	0