Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T28
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T27,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T27,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T12,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T28
1	0	Covered	T28,T34,T43
1	1	Covered	T15,T27,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T12,T28
0	1	Covered	T15,T47,T73
1	0	Covered	T72,T92,T93

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T28,T34
0	1	Covered	T28,T34,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T28,T34
1	-	Covered	T28,T34,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T27,T12
DetectSt	168	Covered	T15,T12,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T12,T28,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T12,T28
DebounceSt->IdleSt	163	Covered	T27,T91,T238
DetectSt->IdleSt	186	Covered	T15,T47,T72
DetectSt->StableSt	191	Covered	T12,T28,T34
IdleSt->DebounceSt	148	Covered	T15,T27,T12
StableSt->IdleSt	206	Covered	T28,T34,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T27,T12
0	1	Covered	T15,T27,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T12,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T27,T12
IdleSt	0	-	-	-	-	-	-	Covered	T15,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T12,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T91,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T27,T12
DetectSt	-	-	-	-	1	-	-	Covered	T15,T47,T72
DetectSt	-	-	-	-	0	1	-	Covered	T12,T28,T34
DetectSt	-	-	-	-	0	0	-	Covered	T15,T12,T28
StableSt	-	-	-	-	-	-	1	Covered	T28,T34,T43
StableSt	-	-	-	-	-	-	0	Covered	T12,T28,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	2832	0	0
CntIncr_A	6869939	87480	0	0
CntNoWrap_A	6869939	6220608	0	0
DetectStDropOut_A	6869939	392	0	0
DetectedOut_A	6869939	71634	0	0
DetectedPulseOut_A	6869939	843	0	0
DisabledIdleSt_A	6869939	5791637	0	0
DisabledNoDetection_A	6869939	5793700	0	0
EnterDebounceSt_A	6869939	1433	0	0
EnterDetectSt_A	6869939	1400	0	0
EnterStableSt_A	6869939	843	0	0
PulseIsPulse_A	6869939	843	0	0
StayInStableSt	6869939	70684	0	0
gen_high_event_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	736	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2832	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T12	0	2	0	0
T15	5016	18	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	10	0	0
T28	0	24	0	0
T34	0	16	0	0
T43	0	60	0	0
T44	0	54	0	0
T45	0	26	0	0
T47	0	48	0	0
T53	402	0	0	0
T72	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	87480	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T12	0	21	0	0
T15	5016	429	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	490	0	0
T28	0	468	0	0
T34	0	440	0	0
T43	0	1380	0	0
T44	0	1728	0	0
T45	0	988	0	0
T47	0	1274	0	0
T53	402	0	0	0
T72	0	756	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6220608	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4597	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	392	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	9	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T47	0	24	0	0
T53	402	0	0	0
T73	0	10	0	0
T91	0	2	0	0
T92	0	6	0	0
T93	0	19	0	0
T94	0	4	0	0
T95	0	22	0	0
T96	0	3	0	0
T97	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	71634	0	0
T12	507	81	0	0
T28	7476	1636	0	0
T33	24860	0	0	0
T34	13183	646	0	0
T38	620	0	0	0
T43	0	1225	0	0
T44	0	2140	0	0
T45	0	1899	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T59	1723	0	0	0
T90	0	465	0	0
T126	450	0	0	0
T127	425	0	0	0
T128	0	81	0	0
T153	0	1652	0	0
T156	0	1247	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	843	0	0
T12	507	1	0	0
T28	7476	12	0	0
T33	24860	0	0	0
T34	13183	8	0	0
T38	620	0	0	0
T43	0	30	0	0
T44	0	27	0	0
T45	0	13	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T59	1723	0	0	0
T90	0	11	0	0
T126	450	0	0	0
T127	425	0	0	0
T128	0	1	0	0
T153	0	10	0	0
T156	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5791637	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	2015	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5793700	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	2015	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1433	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T12	0	1	0	0
T15	5016	9	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	10	0	0
T28	0	12	0	0
T34	0	8	0	0
T43	0	30	0	0
T44	0	27	0	0
T45	0	13	0	0
T47	0	24	0	0
T53	402	0	0	0
T72	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1400	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T12	0	1	0	0
T15	5016	9	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T28	0	12	0	0
T34	0	8	0	0
T43	0	30	0	0
T44	0	27	0	0
T45	0	13	0	0
T47	0	24	0	0
T53	402	0	0	0
T72	0	11	0	0
T73	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	843	0	0
T12	507	1	0	0
T28	7476	12	0	0
T33	24860	0	0	0
T34	13183	8	0	0
T38	620	0	0	0
T43	0	30	0	0
T44	0	27	0	0
T45	0	13	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T59	1723	0	0	0
T90	0	11	0	0
T126	450	0	0	0
T127	425	0	0	0
T128	0	1	0	0
T153	0	10	0	0
T156	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	843	0	0
T12	507	1	0	0
T28	7476	12	0	0
T33	24860	0	0	0
T34	13183	8	0	0
T38	620	0	0	0
T43	0	30	0	0
T44	0	27	0	0
T45	0	13	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T59	1723	0	0	0
T90	0	11	0	0
T126	450	0	0	0
T127	425	0	0	0
T128	0	1	0	0
T153	0	10	0	0
T156	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	70684	0	0
T12	507	79	0	0
T28	7476	1624	0	0
T33	24860	0	0	0
T34	13183	638	0	0
T38	620	0	0	0
T43	0	1195	0	0
T44	0	2112	0	0
T45	0	1882	0	0
T46	6383	0	0	0
T58	3672	0	0	0
T59	1723	0	0	0
T90	0	452	0	0
T126	450	0	0	0
T127	425	0	0	0
T128	0	79	0	0
T153	0	1640	0	0
T156	0	1231	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	736	0	0
T28	7476	12	0	0
T33	24860	0	0	0
T34	13183	8	0	0
T43	0	30	0	0
T44	0	26	0	0
T45	0	9	0	0
T47	5265	0	0	0
T59	1723	0	0	0
T66	1425	0	0	0
T90	0	9	0	0
T126	450	0	0	0
T127	425	0	0	0
T129	637	0	0	0
T130	785	0	0	0
T153	0	8	0	0
T156	0	10	0	0
T239	0	14	0	0
T240	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T27
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T27
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T12,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T12,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T12,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T42,T12
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T12,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T33
0	1	Covered	T76,T78,T98
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T33
0	1	Covered	T1,T12,T33
1	0	Covered	T56,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T33
1	-	Covered	T1,T12,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T33
DetectSt	168	Covered	T1,T12,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T12,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T33
DebounceSt->IdleSt	163	Covered	T1,T33,T35
DetectSt->IdleSt	186	Covered	T76,T78,T98
DetectSt->StableSt	191	Covered	T1,T12,T33
IdleSt->DebounceSt	148	Covered	T1,T12,T33
StableSt->IdleSt	206	Covered	T1,T12,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T33
0	1	Covered	T1,T12,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T33,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T33
DetectSt	-	-	-	-	1	-	-	Covered	T76,T78,T98
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T33
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	843	0	0
CntIncr_A	6869939	42252	0	0
CntNoWrap_A	6869939	6222597	0	0
DetectStDropOut_A	6869939	43	0	0
DetectedOut_A	6869939	14813	0	0
DetectedPulseOut_A	6869939	337	0	0
DisabledIdleSt_A	6869939	5856177	0	0
DisabledNoDetection_A	6869939	5857828	0	0
EnterDebounceSt_A	6869939	460	0	0
EnterDetectSt_A	6869939	384	0	0
EnterStableSt_A	6869939	337	0	0
PulseIsPulse_A	6869939	337	0	0
StayInStableSt	6869939	14445	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	304	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	843	0	0
T1	19091	7	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	7	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	7	0	0
T44	0	2	0	0
T45	0	2	0	0
T50	0	2	0	0
T90	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	42252	0	0
T1	19091	1223	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	25	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	333	0	0
T34	0	58	0	0
T35	0	20	0	0
T36	0	529	0	0
T44	0	84	0	0
T45	0	70	0	0
T50	0	25	0	0
T90	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6222597	0	0
T1	19091	18658	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	43	0	0
T76	192938	3	0	0
T78	0	1	0	0
T98	0	7	0	0
T99	0	3	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	0	5	0	0
T104	0	7	0	0
T105	0	4	0	0
T106	0	5	0	0
T107	499	0	0	0
T108	407	0	0	0
T109	2870	0	0	0
T110	698	0	0	0
T111	26168	0	0	0
T112	427	0	0	0
T113	403	0	0	0
T114	743	0	0	0
T115	98891	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	14813	0	0
T1	19091	136	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	3	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	43	0	0
T34	0	57	0	0
T36	0	46	0	0
T44	0	71	0	0
T45	0	72	0	0
T50	0	4	0	0
T90	0	68	0	0
T125	0	236	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	337	0	0
T1	19091	3	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	1	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T36	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T90	0	2	0	0
T125	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5856177	0	0
T1	19091	10072	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5857828	0	0
T1	19091	10072	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	460	0	0
T1	19091	4	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	1	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	4	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T90	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	384	0	0
T1	19091	3	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	1	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T36	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T90	0	2	0	0
T125	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	337	0	0
T1	19091	3	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	1	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T36	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T90	0	2	0	0
T125	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	337	0	0
T1	19091	3	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	1	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T36	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T90	0	2	0	0
T125	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	14445	0	0
T1	19091	133	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	40	0	0
T34	0	56	0	0
T36	0	43	0	0
T44	0	70	0	0
T45	0	70	0	0
T50	0	3	0	0
T90	0	66	0	0
T125	0	225	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	304	0	0
T1	19091	3	0	0
T2	694	0	0	0
T3	746	0	0	0
T12	0	1	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T36	0	3	0	0
T44	0	1	0	0
T50	0	1	0	0
T90	0	2	0	0
T125	0	11	0	0
T128	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T28
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T28
1	0	Covered	T28,T34,T43
1	1	Covered	T15,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T28,T34
0	1	Covered	T15,T28,T47
1	0	Covered	T28,T45,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T43,T44
0	1	Covered	T34,T43,T44
1	0	Covered	T83,T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T43,T44
1	-	Covered	T34,T43,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T27,T28
DetectSt	168	Covered	T15,T28,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T34,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T28,T34
DebounceSt->IdleSt	163	Covered	T27,T91,T238
DetectSt->IdleSt	186	Covered	T15,T28,T47
DetectSt->StableSt	191	Covered	T34,T43,T44
IdleSt->DebounceSt	148	Covered	T15,T27,T28
StableSt->IdleSt	206	Covered	T34,T43,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T27,T28
0	1	Covered	T15,T27,T28
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T28,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T15,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T28,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T91,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T15,T28,T47
DetectSt	-	-	-	-	0	1	-	Covered	T34,T43,T44
DetectSt	-	-	-	-	0	0	-	Covered	T15,T28,T34
StableSt	-	-	-	-	-	-	1	Covered	T34,T43,T44
StableSt	-	-	-	-	-	-	0	Covered	T34,T43,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	3029	0	0
CntIncr_A	6869939	100683	0	0
CntNoWrap_A	6869939	6220411	0	0
DetectStDropOut_A	6869939	442	0	0
DetectedOut_A	6869939	68393	0	0
DetectedPulseOut_A	6869939	874	0	0
DisabledIdleSt_A	6869939	5797790	0	0
DisabledNoDetection_A	6869939	5799831	0	0
EnterDebounceSt_A	6869939	1545	0	0
EnterDetectSt_A	6869939	1485	0	0
EnterStableSt_A	6869939	874	0	0
PulseIsPulse_A	6869939	874	0	0
StayInStableSt	6869939	67390	0	0
gen_high_event_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	740	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3029	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	40	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	30	0	0
T28	0	26	0	0
T34	0	52	0	0
T43	0	22	0	0
T44	0	24	0	0
T45	0	32	0	0
T47	0	42	0	0
T53	402	0	0	0
T72	0	48	0	0
T73	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	100683	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	961	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	1470	0	0
T28	0	933	0	0
T34	0	1170	0	0
T43	0	495	0	0
T44	0	792	0	0
T45	0	1341	0	0
T47	0	1111	0	0
T53	402	0	0	0
T72	0	1632	0	0
T73	0	674	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6220411	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4575	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	442	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	20	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T28	0	1	0	0
T45	0	9	0	0
T47	0	21	0	0
T53	402	0	0	0
T73	0	13	0	0
T92	0	3	0	0
T94	0	18	0	0
T95	0	14	0	0
T96	0	11	0	0
T153	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	68393	0	0
T34	13183	1340	0	0
T40	813	0	0	0
T43	0	133	0	0
T44	0	465	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	1397	0	0
T90	0	686	0	0
T93	0	719	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	1530	0	0
T198	421	0	0	0
T239	0	29	0	0
T240	0	1044	0	0
T241	0	735	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	874	0	0
T34	13183	26	0	0
T40	813	0	0	0
T43	0	11	0	0
T44	0	12	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	24	0	0
T90	0	11	0	0
T93	0	7	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	28	0	0
T198	421	0	0	0
T239	0	7	0	0
T240	0	24	0	0
T241	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5797790	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	2015	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5799831	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	2015	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1545	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	20	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	30	0	0
T28	0	13	0	0
T34	0	26	0	0
T43	0	11	0	0
T44	0	12	0	0
T45	0	16	0	0
T47	0	21	0	0
T53	402	0	0	0
T72	0	24	0	0
T73	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1485	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	20	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T28	0	13	0	0
T34	0	26	0	0
T43	0	11	0	0
T44	0	12	0	0
T45	0	16	0	0
T47	0	21	0	0
T53	402	0	0	0
T72	0	24	0	0
T73	0	13	0	0
T90	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	874	0	0
T34	13183	26	0	0
T40	813	0	0	0
T43	0	11	0	0
T44	0	12	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	24	0	0
T90	0	11	0	0
T93	0	7	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	28	0	0
T198	421	0	0	0
T239	0	7	0	0
T240	0	24	0	0
T241	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	874	0	0
T34	13183	26	0	0
T40	813	0	0	0
T43	0	11	0	0
T44	0	12	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	24	0	0
T90	0	11	0	0
T93	0	7	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	28	0	0
T198	421	0	0	0
T239	0	7	0	0
T240	0	24	0	0
T241	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	67390	0	0
T34	13183	1311	0	0
T40	813	0	0	0
T43	0	122	0	0
T44	0	452	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	1373	0	0
T90	0	675	0	0
T93	0	707	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	1498	0	0
T198	421	0	0	0
T239	0	22	0	0
T240	0	1019	0	0
T241	0	720	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	740	0	0
T34	13183	23	0	0
T40	813	0	0	0
T43	0	11	0	0
T44	0	11	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	24	0	0
T90	0	11	0	0
T93	0	2	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	24	0	0
T198	421	0	0	0
T239	0	7	0	0
T240	0	23	0	0
T241	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T42,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T42,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T42,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T42
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T42,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T42,T33
0	1	Covered	T77,T78,T242
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T42,T33
0	1	Covered	T1,T42,T33
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T42,T33
1	-	Covered	T1,T42,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T42,T33
DetectSt	168	Covered	T1,T42,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T42,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T42,T33
DebounceSt->IdleSt	163	Covered	T33,T72,T36
DetectSt->IdleSt	186	Covered	T77,T78,T242
DetectSt->StableSt	191	Covered	T1,T42,T33
IdleSt->DebounceSt	148	Covered	T1,T42,T33
StableSt->IdleSt	206	Covered	T1,T42,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T42,T33
0	1	Covered	T1,T42,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T42,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T42,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T42,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T72,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T42,T33
DetectSt	-	-	-	-	1	-	-	Covered	T77,T78,T242
DetectSt	-	-	-	-	0	1	-	Covered	T1,T42,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T42,T33
StableSt	-	-	-	-	-	-	1	Covered	T1,T42,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T42,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	939	0	0
CntIncr_A	6869939	54352	0	0
CntNoWrap_A	6869939	6222501	0	0
DetectStDropOut_A	6869939	81	0	0
DetectedOut_A	6869939	15250	0	0
DetectedPulseOut_A	6869939	360	0	0
DisabledIdleSt_A	6869939	5859131	0	0
DisabledNoDetection_A	6869939	5860815	0	0
EnterDebounceSt_A	6869939	496	0	0
EnterDetectSt_A	6869939	445	0	0
EnterStableSt_A	6869939	360	0	0
PulseIsPulse_A	6869939	360	0	0
StayInStableSt	6869939	14856	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	323	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	939	0	0
T1	19091	4	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	18	0	0
T34	0	10	0	0
T35	0	2	0	0
T36	0	7	0	0
T42	0	2	0	0
T44	0	2	0	0
T72	0	3	0	0
T90	0	4	0	0
T125	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	54352	0	0
T1	19091	718	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	1228	0	0
T34	0	190	0	0
T35	0	151	0	0
T36	0	322	0	0
T42	0	139	0	0
T44	0	78	0	0
T72	0	107	0	0
T90	0	90	0	0
T125	0	174	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6222501	0	0
T1	19091	18661	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	81	0	0
T77	28225	1	0	0
T78	15753	4	0	0
T98	0	2	0	0
T104	0	11	0	0
T162	0	4	0	0
T240	13510	0	0	0
T242	0	7	0	0
T243	0	8	0	0
T244	0	4	0	0
T245	0	8	0	0
T246	0	7	0	0
T247	13493	0	0	0
T248	32239	0	0	0
T249	502	0	0	0
T250	405	0	0	0
T251	443	0	0	0
T252	107754	0	0	0
T253	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	15250	0	0
T1	19091	18	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	61	0	0
T34	0	385	0	0
T35	0	11	0	0
T36	0	254	0	0
T42	0	16	0	0
T44	0	79	0	0
T72	0	67	0	0
T90	0	76	0	0
T125	0	31	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	360	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	8	0	0
T34	0	5	0	0
T35	0	1	0	0
T36	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T72	0	1	0	0
T90	0	2	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5859131	0	0
T1	19091	10072	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5860815	0	0
T1	19091	10072	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	496	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	10	0	0
T34	0	5	0	0
T35	0	1	0	0
T36	0	4	0	0
T42	0	1	0	0
T44	0	1	0	0
T72	0	2	0	0
T90	0	2	0	0
T125	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	445	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	8	0	0
T34	0	5	0	0
T35	0	1	0	0
T36	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T72	0	1	0	0
T90	0	2	0	0
T125	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	360	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	8	0	0
T34	0	5	0	0
T35	0	1	0	0
T36	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T72	0	1	0	0
T90	0	2	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	360	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	8	0	0
T34	0	5	0	0
T35	0	1	0	0
T36	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T72	0	1	0	0
T90	0	2	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	14856	0	0
T1	19091	16	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	53	0	0
T34	0	380	0	0
T35	0	10	0	0
T36	0	251	0	0
T42	0	15	0	0
T44	0	78	0	0
T72	0	66	0	0
T90	0	74	0	0
T125	0	30	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	323	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	8	0	0
T34	0	5	0	0
T35	0	1	0	0
T36	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T72	0	1	0	0
T90	0	1	0	0
T125	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T28
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T28
1	0	Covered	T28,T34,T43
1	1	Covered	T15,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T28,T34
0	1	Covered	T15,T47,T44
1	0	Covered	T43,T44,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T34,T45
0	1	Covered	T28,T34,T45
1	0	Covered	T56,T84,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T34,T45
1	-	Covered	T28,T34,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T27,T28
DetectSt	168	Covered	T15,T28,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T28,T34,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T28,T34
DebounceSt->IdleSt	163	Covered	T27,T91,T238
DetectSt->IdleSt	186	Covered	T15,T47,T43
DetectSt->StableSt	191	Covered	T28,T34,T45
IdleSt->DebounceSt	148	Covered	T15,T27,T28
StableSt->IdleSt	206	Covered	T28,T34,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T27,T28
0	1	Covered	T15,T27,T28
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T28,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T15,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T28,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T91,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T15,T47,T43
DetectSt	-	-	-	-	0	1	-	Covered	T28,T34,T45
DetectSt	-	-	-	-	0	0	-	Covered	T15,T28,T34
StableSt	-	-	-	-	-	-	1	Covered	T28,T34,T45
StableSt	-	-	-	-	-	-	0	Covered	T28,T34,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	2841	0	0
CntIncr_A	6869939	99662	0	0
CntNoWrap_A	6869939	6220599	0	0
DetectStDropOut_A	6869939	445	0	0
DetectedOut_A	6869939	76330	0	0
DetectedPulseOut_A	6869939	846	0	0
DisabledIdleSt_A	6869939	5786360	0	0
DisabledNoDetection_A	6869939	5788398	0	0
EnterDebounceSt_A	6869939	1451	0	0
EnterDetectSt_A	6869939	1392	0	0
EnterStableSt_A	6869939	846	0	0
PulseIsPulse_A	6869939	846	0	0
StayInStableSt	6869939	75352	0	0
gen_high_event_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	708	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	2841	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	60	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	22	0	0
T28	0	28	0	0
T34	0	42	0	0
T43	0	26	0	0
T44	0	24	0	0
T45	0	28	0	0
T47	0	59	0	0
T53	402	0	0	0
T72	0	20	0	0
T73	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	99662	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	1440	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	1078	0	0
T28	0	518	0	0
T34	0	609	0	0
T43	0	713	0	0
T44	0	904	0	0
T45	0	896	0	0
T47	0	1595	0	0
T53	402	0	0	0
T72	0	676	0	0
T73	0	667	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6220599	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4555	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	445	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	30	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T44	0	4	0	0
T47	0	29	0	0
T53	402	0	0	0
T72	0	8	0	0
T73	0	13	0	0
T91	0	1	0	0
T94	0	27	0	0
T95	0	14	0	0
T96	0	11	0	0
T254	0	27	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	76330	0	0
T28	7476	515	0	0
T33	24860	0	0	0
T34	13183	1596	0	0
T45	0	2510	0	0
T47	5265	0	0	0
T59	1723	0	0	0
T66	1425	0	0	0
T90	0	617	0	0
T92	0	1407	0	0
T93	0	1371	0	0
T126	450	0	0	0
T127	425	0	0	0
T129	637	0	0	0
T130	785	0	0	0
T153	0	441	0	0
T156	0	60	0	0
T240	0	1869	0	0
T241	0	1698	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	846	0	0
T28	7476	14	0	0
T33	24860	0	0	0
T34	13183	21	0	0
T45	0	14	0	0
T47	5265	0	0	0
T59	1723	0	0	0
T66	1425	0	0	0
T90	0	10	0	0
T92	0	13	0	0
T93	0	11	0	0
T126	450	0	0	0
T127	425	0	0	0
T129	637	0	0	0
T130	785	0	0	0
T153	0	13	0	0
T156	0	5	0	0
T240	0	22	0	0
T241	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5786360	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	2015	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5788398	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	2015	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1451	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	30	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	22	0	0
T28	0	14	0	0
T34	0	21	0	0
T43	0	13	0	0
T44	0	12	0	0
T45	0	14	0	0
T47	0	30	0	0
T53	402	0	0	0
T72	0	10	0	0
T73	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1392	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	30	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T28	0	14	0	0
T34	0	21	0	0
T43	0	13	0	0
T44	0	12	0	0
T45	0	14	0	0
T47	0	30	0	0
T53	402	0	0	0
T72	0	10	0	0
T73	0	13	0	0
T91	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	846	0	0
T28	7476	14	0	0
T33	24860	0	0	0
T34	13183	21	0	0
T45	0	14	0	0
T47	5265	0	0	0
T59	1723	0	0	0
T66	1425	0	0	0
T90	0	10	0	0
T92	0	13	0	0
T93	0	11	0	0
T126	450	0	0	0
T127	425	0	0	0
T129	637	0	0	0
T130	785	0	0	0
T153	0	13	0	0
T156	0	5	0	0
T240	0	22	0	0
T241	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	846	0	0
T28	7476	14	0	0
T33	24860	0	0	0
T34	13183	21	0	0
T45	0	14	0	0
T47	5265	0	0	0
T59	1723	0	0	0
T66	1425	0	0	0
T90	0	10	0	0
T92	0	13	0	0
T93	0	11	0	0
T126	450	0	0	0
T127	425	0	0	0
T129	637	0	0	0
T130	785	0	0	0
T153	0	13	0	0
T156	0	5	0	0
T240	0	22	0	0
T241	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	75352	0	0
T28	7476	501	0	0
T33	24860	0	0	0
T34	13183	1575	0	0
T45	0	2489	0	0
T47	5265	0	0	0
T59	1723	0	0	0
T66	1425	0	0	0
T90	0	605	0	0
T92	0	1391	0	0
T93	0	1355	0	0
T126	450	0	0	0
T127	425	0	0	0
T129	637	0	0	0
T130	785	0	0	0
T153	0	426	0	0
T156	0	55	0	0
T240	0	1846	0	0
T241	0	1671	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	708	0	0
T28	7476	14	0	0
T33	24860	0	0	0
T34	13183	21	0	0
T45	0	7	0	0
T47	5265	0	0	0
T59	1723	0	0	0
T66	1425	0	0	0
T90	0	8	0	0
T92	0	10	0	0
T93	0	6	0	0
T126	450	0	0	0
T127	425	0	0	0
T129	637	0	0	0
T130	785	0	0	0
T153	0	11	0	0
T156	0	5	0	0
T240	0	21	0	0
T241	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T6,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T42
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T6,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T33
0	1	Covered	T76,T174,T162
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T33
0	1	Covered	T1,T6,T33
1	0	Covered	T80,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T33
1	-	Covered	T1,T6,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T33
DetectSt	168	Covered	T1,T6,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T6,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T33
DebounceSt->IdleSt	163	Covered	T241,T255,T174
DetectSt->IdleSt	186	Covered	T76,T174,T162
DetectSt->StableSt	191	Covered	T1,T6,T33
IdleSt->DebounceSt	148	Covered	T1,T6,T33
StableSt->IdleSt	206	Covered	T1,T6,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T33
0	1	Covered	T1,T6,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T241,T255,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T33
DetectSt	-	-	-	-	1	-	-	Covered	T76,T174,T162
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T33
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	861	0	0
CntIncr_A	6869939	45467	0	0
CntNoWrap_A	6869939	6222579	0	0
DetectStDropOut_A	6869939	41	0	0
DetectedOut_A	6869939	17626	0	0
DetectedPulseOut_A	6869939	359	0	0
DisabledIdleSt_A	6869939	5868725	0	0
DisabledNoDetection_A	6869939	5870433	0	0
EnterDebounceSt_A	6869939	457	0	0
EnterDetectSt_A	6869939	404	0	0
EnterStableSt_A	6869939	359	0	0
PulseIsPulse_A	6869939	359	0	0
StayInStableSt	6869939	17212	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	300	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	861	0	0
T1	19091	4	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	4	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	4	0	0
T34	0	6	0	0
T35	0	2	0	0
T45	0	10	0	0
T85	0	2	0	0
T90	0	8	0	0
T92	0	6	0	0
T125	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	45467	0	0
T1	19091	600	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	212	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	182	0	0
T34	0	144	0	0
T35	0	145	0	0
T45	0	340	0	0
T85	0	86	0	0
T90	0	220	0	0
T92	0	144	0	0
T125	0	103	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6222579	0	0
T1	19091	18661	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	41	0	0
T76	192938	2	0	0
T107	499	0	0	0
T108	407	0	0	0
T109	2870	0	0	0
T110	698	0	0	0
T111	26168	0	0	0
T112	427	0	0	0
T113	403	0	0	0
T114	743	0	0	0
T115	98891	0	0	0
T162	0	1	0	0
T174	0	1	0	0
T246	0	14	0	0
T256	0	8	0	0
T257	0	2	0	0
T258	0	1	0	0
T259	0	6	0	0
T260	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	17626	0	0
T1	19091	134	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	32	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	111	0	0
T34	0	200	0	0
T35	0	18	0	0
T45	0	372	0	0
T85	0	46	0	0
T90	0	110	0	0
T92	0	160	0	0
T125	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	359	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	1	0	0
T45	0	5	0	0
T85	0	1	0	0
T90	0	4	0	0
T92	0	3	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5868725	0	0
T1	19091	10072	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5870433	0	0
T1	19091	10072	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	457	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	1	0	0
T45	0	5	0	0
T85	0	1	0	0
T90	0	4	0	0
T92	0	3	0	0
T125	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	404	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	1	0	0
T45	0	5	0	0
T85	0	1	0	0
T90	0	4	0	0
T92	0	3	0	0
T125	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	359	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	1	0	0
T45	0	5	0	0
T85	0	1	0	0
T90	0	4	0	0
T92	0	3	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	359	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	1	0	0
T45	0	5	0	0
T85	0	1	0	0
T90	0	4	0	0
T92	0	3	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	17212	0	0
T1	19091	132	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	30	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	109	0	0
T34	0	197	0	0
T35	0	17	0	0
T45	0	362	0	0
T85	0	45	0	0
T90	0	106	0	0
T92	0	157	0	0
T125	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	300	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	1	0	0
T76	0	3	0	0
T85	0	1	0	0
T90	0	4	0	0
T92	0	3	0	0
T125	0	1	0	0