Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T28
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T28
1	0	Covered	T28,T34,T43
1	1	Covered	T15,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T28,T34
0	1	Covered	T15,T47,T73
1	0	Covered	T28,T90,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T43,T44
0	1	Covered	T34,T43,T44
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T43,T44
1	-	Covered	T34,T43,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T27,T28
DetectSt	168	Covered	T15,T28,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T34,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T28,T34
DebounceSt->IdleSt	163	Covered	T27,T91,T238
DetectSt->IdleSt	186	Covered	T15,T28,T47
DetectSt->StableSt	191	Covered	T34,T43,T44
IdleSt->DebounceSt	148	Covered	T15,T27,T28
StableSt->IdleSt	206	Covered	T34,T43,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T27,T28
0	1	Covered	T15,T27,T28
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T28,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T15,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T28,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T91,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T15,T28,T47
DetectSt	-	-	-	-	0	1	-	Covered	T34,T43,T44
DetectSt	-	-	-	-	0	0	-	Covered	T15,T28,T34
StableSt	-	-	-	-	-	-	1	Covered	T34,T43,T44
StableSt	-	-	-	-	-	-	0	Covered	T34,T43,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	3123	0	0
CntIncr_A	6869939	102878	0	0
CntNoWrap_A	6869939	6220317	0	0
DetectStDropOut_A	6869939	514	0	0
DetectedOut_A	6869939	62208	0	0
DetectedPulseOut_A	6869939	820	0	0
DisabledIdleSt_A	6869939	5800923	0	0
DisabledNoDetection_A	6869939	5802985	0	0
EnterDebounceSt_A	6869939	1598	0	0
EnterDetectSt_A	6869939	1526	0	0
EnterStableSt_A	6869939	820	0	0
PulseIsPulse_A	6869939	820	0	0
StayInStableSt	6869939	61280	0	0
gen_high_event_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	711	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	3123	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	46	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	27	0	0
T28	0	6	0	0
T34	0	54	0	0
T43	0	60	0	0
T44	0	16	0	0
T45	0	26	0	0
T47	0	48	0	0
T53	402	0	0	0
T72	0	18	0	0
T73	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	102878	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	1103	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	1323	0	0
T28	0	214	0	0
T34	0	1080	0	0
T43	0	1530	0	0
T44	0	464	0	0
T45	0	780	0	0
T47	0	1274	0	0
T53	402	0	0	0
T72	0	504	0	0
T73	0	1298	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6220317	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4569	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	514	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	23	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T47	0	24	0	0
T53	402	0	0	0
T73	0	25	0	0
T90	0	12	0	0
T91	0	11	0	0
T92	0	19	0	0
T94	0	23	0	0
T95	0	8	0	0
T153	0	13	0	0
T241	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	62208	0	0
T34	13183	1723	0	0
T40	813	0	0	0
T43	0	1075	0	0
T44	0	481	0	0
T45	0	1950	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	130	0	0
T93	0	789	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	175	0	0
T198	421	0	0	0
T239	0	1031	0	0
T240	0	804	0	0
T247	0	802	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	820	0	0
T34	13183	27	0	0
T40	813	0	0	0
T43	0	30	0	0
T44	0	8	0	0
T45	0	13	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	9	0	0
T93	0	7	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	10	0	0
T198	421	0	0	0
T239	0	12	0	0
T240	0	24	0	0
T247	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5800923	0	0
T1	19091	18665	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	2015	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5802985	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	2015	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1598	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	23	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T27	0	27	0	0
T28	0	3	0	0
T34	0	27	0	0
T43	0	30	0	0
T44	0	8	0	0
T45	0	13	0	0
T47	0	24	0	0
T53	402	0	0	0
T72	0	9	0	0
T73	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	1526	0	0
T3	746	0	0	0
T6	10166	0	0	0
T7	1006	0	0	0
T15	5016	23	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T26	502	0	0	0
T28	0	3	0	0
T34	0	27	0	0
T43	0	30	0	0
T44	0	8	0	0
T45	0	13	0	0
T47	0	24	0	0
T53	402	0	0	0
T72	0	9	0	0
T73	0	25	0	0
T91	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	820	0	0
T34	13183	27	0	0
T40	813	0	0	0
T43	0	30	0	0
T44	0	8	0	0
T45	0	13	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	9	0	0
T93	0	7	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	10	0	0
T198	421	0	0	0
T239	0	12	0	0
T240	0	24	0	0
T247	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	820	0	0
T34	13183	27	0	0
T40	813	0	0	0
T43	0	30	0	0
T44	0	8	0	0
T45	0	13	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	9	0	0
T93	0	7	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	10	0	0
T198	421	0	0	0
T239	0	12	0	0
T240	0	24	0	0
T247	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	61280	0	0
T34	13183	1693	0	0
T40	813	0	0	0
T43	0	1045	0	0
T44	0	472	0	0
T45	0	1930	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	121	0	0
T93	0	777	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	165	0	0
T198	421	0	0	0
T239	0	1019	0	0
T240	0	779	0	0
T247	0	785	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	711	0	0
T34	13183	24	0	0
T40	813	0	0	0
T43	0	30	0	0
T44	0	7	0	0
T45	0	6	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T72	0	9	0	0
T93	0	2	0	0
T129	637	0	0	0
T130	785	0	0	0
T156	0	10	0	0
T198	421	0	0	0
T239	0	12	0	0
T240	0	23	0	0
T247	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T6,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T42
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T6,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T33
0	1	Covered	T33,T111,T248
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T34
0	1	Covered	T1,T6,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T34
1	-	Covered	T1,T6,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T33
DetectSt	168	Covered	T1,T6,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T6,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T33
DebounceSt->IdleSt	163	Covered	T33,T125,T111
DetectSt->IdleSt	186	Covered	T33,T111,T248
DetectSt->StableSt	191	Covered	T1,T6,T34
IdleSt->DebounceSt	148	Covered	T1,T6,T33
StableSt->IdleSt	206	Covered	T1,T6,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T33
0	1	Covered	T1,T6,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T125,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T33
DetectSt	-	-	-	-	1	-	-	Covered	T33,T111,T248
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T34
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T33
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T34
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6869939	713	0	0
CntIncr_A	6869939	41374	0	0
CntNoWrap_A	6869939	6222727	0	0
DetectStDropOut_A	6869939	84	0	0
DetectedOut_A	6869939	11396	0	0
DetectedPulseOut_A	6869939	247	0	0
DisabledIdleSt_A	6869939	5869277	0	0
DisabledNoDetection_A	6869939	5870993	0	0
EnterDebounceSt_A	6869939	378	0	0
EnterDetectSt_A	6869939	336	0	0
EnterStableSt_A	6869939	247	0	0
PulseIsPulse_A	6869939	247	0	0
StayInStableSt	6869939	11127	0	0
gen_high_level_sva.HighLevelEvent_A	6869939	6225703	0	0
gen_not_sticky_sva.StableStDropOut_A	6869939	222	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	713	0	0
T1	19091	2	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	4	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	18	0	0
T34	0	6	0	0
T36	0	4	0	0
T45	0	12	0	0
T76	0	2	0	0
T85	0	4	0	0
T93	0	10	0	0
T125	0	23	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	41374	0	0
T1	19091	281	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	232	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	1282	0	0
T34	0	108	0	0
T36	0	250	0	0
T45	0	402	0	0
T76	0	90	0	0
T85	0	226	0	0
T93	0	330	0	0
T125	0	1362	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6222727	0	0
T1	19091	18663	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	84	0	0
T33	24860	8	0	0
T34	13183	0	0	0
T40	813	0	0	0
T47	5265	0	0	0
T48	730	0	0	0
T59	1723	0	0	0
T61	10298	0	0	0
T66	1425	0	0	0
T111	0	2	0	0
T129	637	0	0	0
T130	785	0	0	0
T162	0	6	0	0
T203	0	1	0	0
T232	0	1	0	0
T244	0	5	0	0
T248	0	2	0	0
T261	0	1	0	0
T262	0	6	0	0
T263	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	11396	0	0
T1	19091	87	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	12	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T34	0	239	0	0
T36	0	92	0	0
T45	0	452	0	0
T76	0	69	0	0
T85	0	40	0	0
T93	0	260	0	0
T125	0	253	0	0
T219	0	271	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	247	0	0
T1	19091	1	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T34	0	3	0	0
T36	0	2	0	0
T45	0	6	0	0
T76	0	1	0	0
T85	0	2	0	0
T93	0	5	0	0
T125	0	10	0	0
T219	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5869277	0	0
T1	19091	10072	0	0
T2	694	293	0	0
T3	746	345	0	0
T4	713	312	0	0
T5	445	44	0	0
T13	50321	48317	0	0
T14	422	21	0	0
T15	5016	4615	0	0
T16	620	219	0	0
T17	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	5870993	0	0
T1	19091	10072	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	378	0	0
T1	19091	1	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	10	0	0
T34	0	3	0	0
T36	0	2	0	0
T45	0	6	0	0
T76	0	1	0	0
T85	0	2	0	0
T93	0	5	0	0
T125	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	336	0	0
T1	19091	1	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T33	0	8	0	0
T34	0	3	0	0
T36	0	2	0	0
T45	0	6	0	0
T76	0	1	0	0
T85	0	2	0	0
T93	0	5	0	0
T125	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	247	0	0
T1	19091	1	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T34	0	3	0	0
T36	0	2	0	0
T45	0	6	0	0
T76	0	1	0	0
T85	0	2	0	0
T93	0	5	0	0
T125	0	10	0	0
T219	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	247	0	0
T1	19091	1	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T34	0	3	0	0
T36	0	2	0	0
T45	0	6	0	0
T76	0	1	0	0
T85	0	2	0	0
T93	0	5	0	0
T125	0	10	0	0
T219	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	11127	0	0
T1	19091	86	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	10	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T34	0	236	0	0
T36	0	89	0	0
T45	0	440	0	0
T76	0	68	0	0
T85	0	38	0	0
T93	0	255	0	0
T125	0	243	0	0
T219	0	267	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	6225703	0	0
T1	19091	18670	0	0
T2	694	294	0	0
T3	746	346	0	0
T4	713	313	0	0
T5	445	45	0	0
T13	50321	48321	0	0
T14	422	22	0	0
T15	5016	4616	0	0
T16	620	220	0	0
T17	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6869939	222	0	0
T1	19091	1	0	0
T2	694	0	0	0
T3	746	0	0	0
T6	0	2	0	0
T13	50321	0	0	0
T14	422	0	0	0
T15	5016	0	0	0
T16	620	0	0	0
T17	505	0	0	0
T18	736	0	0	0
T19	514	0	0	0
T34	0	3	0	0
T36	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T85	0	2	0	0
T93	0	5	0	0
T125	0	10	0	0
T219	0	4	0	0