Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1224241141	9485	0	0
auto_block_debounce_ctl_rd_A	1224241141	1887	0	0
auto_block_out_ctl_rd_A	1224241141	2314	0	0
com_det_ctl_0_rd_A	1224241141	3612	0	0
com_det_ctl_1_rd_A	1224241141	3973	0	0
com_det_ctl_2_rd_A	1224241141	4056	0	0
com_det_ctl_3_rd_A	1224241141	4075	0	0
com_out_ctl_0_rd_A	1224241141	4589	0	0
com_out_ctl_1_rd_A	1224241141	4532	0	0
com_out_ctl_2_rd_A	1224241141	4279	0	0
com_out_ctl_3_rd_A	1224241141	4450	0	0
com_pre_det_ctl_0_rd_A	1224241141	1555	0	0
com_pre_det_ctl_1_rd_A	1224241141	1236	0	0
com_pre_det_ctl_2_rd_A	1224241141	1374	0	0
com_pre_det_ctl_3_rd_A	1224241141	1328	0	0
com_pre_sel_ctl_0_rd_A	1224241141	4561	0	0
com_pre_sel_ctl_1_rd_A	1224241141	4820	0	0
com_pre_sel_ctl_2_rd_A	1224241141	4471	0	0
com_pre_sel_ctl_3_rd_A	1224241141	4267	0	0
com_sel_ctl_0_rd_A	1224241141	4503	0	0
com_sel_ctl_1_rd_A	1224241141	4228	0	0
com_sel_ctl_2_rd_A	1224241141	4439	0	0
com_sel_ctl_3_rd_A	1224241141	4549	0	0
ec_rst_ctl_rd_A	1224241141	2404	0	0
intr_enable_rd_A	1224241141	1690	0	0
key_intr_ctl_rd_A	1224241141	3148	0	0
key_intr_debounce_ctl_rd_A	1224241141	1384	0	0
key_invert_ctl_rd_A	1224241141	4992	0	0
pin_allowed_ctl_rd_A	1224241141	5921	0	0
pin_out_ctl_rd_A	1224241141	4060	0	0
pin_out_value_rd_A	1224241141	4256	0	0
regwen_rd_A	1224241141	1413	0	0
ulp_ac_debounce_ctl_rd_A	1224241141	1469	0	0
ulp_ctl_rd_A	1224241141	1564	0	0
ulp_lid_debounce_ctl_rd_A	1224241141	1505	0	0
ulp_pwrb_debounce_ctl_rd_A	1224241141	1422	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	9485	0	0
T9	211026	7	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T35	0	12	0	0
T38	172231	0	0	0
T42	522737	10	0	0
T46	306396	8	0	0
T58	739128	0	0	0
T76	0	6	0	0
T85	0	10	0	0
T111	0	16	0	0
T135	0	4	0	0
T287	0	2	0	0
T288	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1887	0	0
T2	49034	0	0	0
T3	373179	0	0	0
T6	254165	0	0	0
T9	0	26	0	0
T13	213862	58	0	0
T14	211187	0	0	0
T15	240787	0	0	0
T16	46542	0	0	0
T17	63167	0	0	0
T18	349719	0	0	0
T19	56617	0	0	0
T49	0	16	0	0
T52	0	14	0	0
T85	0	37	0	0
T287	0	17	0	0
T289	0	10	0	0
T290	0	17	0	0
T291	0	11	0	0
T292	0	15	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	2314	0	0
T2	49034	0	0	0
T3	373179	0	0	0
T6	254165	0	0	0
T9	0	6	0	0
T13	213862	18	0	0
T14	211187	0	0	0
T15	240787	0	0	0
T16	46542	0	0	0
T17	63167	0	0	0
T18	349719	0	0	0
T19	56617	0	0	0
T49	0	15	0	0
T52	0	8	0	0
T85	0	27	0	0
T287	0	34	0	0
T289	0	4	0	0
T290	0	9	0	0
T291	0	9	0	0
T292	0	3	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	3612	0	0
T9	211026	10	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	40	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	90	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	66	0	0
T85	0	53	0	0
T93	0	63	0	0
T156	0	54	0	0
T219	0	43	0	0
T241	0	58	0	0
T287	0	18	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	3973	0	0
T9	211026	12	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	42	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	100	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	113	0	0
T85	0	31	0	0
T93	0	54	0	0
T156	0	61	0	0
T219	0	61	0	0
T241	0	57	0	0
T287	0	5	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4056	0	0
T9	211026	10	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	35	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	102	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	121	0	0
T85	0	46	0	0
T93	0	67	0	0
T156	0	55	0	0
T219	0	74	0	0
T241	0	36	0	0
T287	0	9	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4075	0	0
T9	211026	13	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	58	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	119	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	82	0	0
T85	0	18	0	0
T93	0	44	0	0
T156	0	68	0	0
T219	0	66	0	0
T241	0	51	0	0
T287	0	9	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4589	0	0
T9	211026	10	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	33	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	87	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	100	0	0
T85	0	44	0	0
T93	0	62	0	0
T156	0	67	0	0
T219	0	78	0	0
T241	0	67	0	0
T287	0	8	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4532	0	0
T9	211026	20	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	59	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	104	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	92	0	0
T85	0	47	0	0
T93	0	51	0	0
T156	0	47	0	0
T219	0	97	0	0
T241	0	35	0	0
T248	0	65	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4279	0	0
T9	211026	13	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	33	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	102	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	88	0	0
T85	0	46	0	0
T93	0	62	0	0
T156	0	50	0	0
T219	0	89	0	0
T241	0	58	0	0
T287	0	9	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4450	0	0
T9	211026	9	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	35	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	97	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	107	0	0
T85	0	34	0	0
T93	0	66	0	0
T156	0	51	0	0
T219	0	66	0	0
T241	0	36	0	0
T287	0	1	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1555	0	0
T9	211026	16	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	23	0	0
T85	0	44	0	0
T145	0	4	0	0
T168	0	46	0	0
T218	0	27	0	0
T266	0	91	0	0
T281	0	13	0	0
T293	0	5	0	0
T294	0	34	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1236	0	0
T9	211026	7	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	12	0	0
T85	0	16	0	0
T145	0	26	0	0
T168	0	32	0	0
T218	0	12	0	0
T266	0	63	0	0
T293	0	5	0	0
T294	0	23	0	0
T295	0	9	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1374	0	0
T9	211026	4	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	32	0	0
T85	0	15	0	0
T145	0	25	0	0
T168	0	49	0	0
T218	0	52	0	0
T266	0	80	0	0
T287	0	10	0	0
T293	0	4	0	0
T294	0	3	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1328	0	0
T9	211026	13	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	10	0	0
T85	0	27	0	0
T145	0	29	0	0
T168	0	36	0	0
T218	0	48	0	0
T266	0	67	0	0
T281	0	8	0	0
T293	0	12	0	0
T294	0	15	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4561	0	0
T9	211026	15	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	31	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	79	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	96	0	0
T85	0	35	0	0
T93	0	62	0	0
T156	0	47	0	0
T219	0	69	0	0
T241	0	48	0	0
T248	0	22	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4820	0	0
T9	211026	15	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	39	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	94	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	87	0	0
T85	0	54	0	0
T93	0	52	0	0
T156	0	45	0	0
T219	0	52	0	0
T241	0	41	0	0
T287	0	16	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4471	0	0
T9	211026	2	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	57	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	108	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	90	0	0
T85	0	45	0	0
T93	0	59	0	0
T156	0	40	0	0
T219	0	74	0	0
T241	0	37	0	0
T287	0	10	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4267	0	0
T9	211026	8	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	49	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	80	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	59	0	0
T85	0	27	0	0
T93	0	53	0	0
T156	0	47	0	0
T219	0	60	0	0
T241	0	42	0	0
T287	0	8	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4503	0	0
T9	211026	14	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	25	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	83	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	94	0	0
T85	0	30	0	0
T93	0	62	0	0
T156	0	39	0	0
T219	0	67	0	0
T241	0	49	0	0
T287	0	9	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4228	0	0
T9	211026	15	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	40	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	83	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	81	0	0
T85	0	39	0	0
T93	0	64	0	0
T156	0	50	0	0
T219	0	69	0	0
T241	0	60	0	0
T287	0	10	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4439	0	0
T9	211026	12	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	32	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	121	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	98	0	0
T85	0	32	0	0
T93	0	55	0	0
T156	0	75	0	0
T219	0	62	0	0
T241	0	48	0	0
T287	0	13	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4549	0	0
T9	211026	24	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	62	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	113	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	96	0	0
T85	0	49	0	0
T93	0	43	0	0
T156	0	57	0	0
T219	0	62	0	0
T241	0	54	0	0
T287	0	8	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	2404	0	0
T9	211026	9	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T36	0	11	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T45	0	39	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	36	0	0
T85	0	59	0	0
T93	0	42	0	0
T156	0	13	0	0
T287	0	1	0	0
T296	0	1	0	0
T297	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1690	0	0
T9	211026	14	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	39	0	0
T85	0	36	0	0
T163	0	19	0	0
T168	0	32	0	0
T218	0	40	0	0
T219	0	16	0	0
T287	0	40	0	0
T293	0	5	0	0
T298	0	11	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	3148	0	0
T9	211026	14	0	0
T10	209240	0	0	0
T11	100245	1	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T37	0	3	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T71	0	4	0	0
T76	0	37	0	0
T85	0	26	0	0
T86	0	6	0	0
T175	0	6	0	0
T219	0	6	0	0
T287	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1384	0	0
T9	211026	26	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	30	0	0
T85	0	18	0	0
T145	0	28	0	0
T168	0	17	0	0
T218	0	15	0	0
T287	0	13	0	0
T293	0	9	0	0
T294	0	18	0	0
T295	0	1	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4992	0	0
T8	223422	0	0	0
T9	211026	12	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T24	59240	63	0	0
T25	111076	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T65	260881	0	0	0
T68	0	58	0	0
T69	0	59	0	0
T76	0	190	0	0
T85	0	92	0	0
T107	0	86	0	0
T287	0	42	0	0
T299	0	65	0	0
T300	0	40	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	5921	0	0
T9	211026	8	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T68	0	47	0	0
T76	0	79	0	0
T85	0	184	0	0
T159	0	75	0	0
T200	0	76	0	0
T249	0	36	0	0
T287	0	4	0	0
T301	0	78	0	0
T302	0	67	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4060	0	0
T9	211026	19	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T68	0	38	0	0
T76	0	94	0	0
T85	0	154	0	0
T159	0	51	0	0
T200	0	75	0	0
T249	0	44	0	0
T287	0	18	0	0
T301	0	45	0	0
T302	0	54	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	4256	0	0
T9	211026	5	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T68	0	58	0	0
T76	0	86	0	0
T85	0	173	0	0
T159	0	71	0	0
T200	0	53	0	0
T249	0	77	0	0
T301	0	66	0	0
T302	0	80	0	0
T303	0	56	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1413	0	0
T9	211026	23	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T76	0	30	0	0
T85	0	16	0	0
T145	0	22	0	0
T168	0	29	0	0
T218	0	45	0	0
T287	0	5	0	0
T293	0	7	0	0
T294	0	30	0	0
T295	0	1	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1469	0	0
T9	211026	6	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T60	0	1	0	0
T62	0	3	0	0
T63	0	1	0	0
T76	0	33	0	0
T85	0	31	0	0
T134	0	7	0	0
T147	0	4	0	0
T287	0	13	0	0
T304	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1564	0	0
T9	211026	14	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T60	0	3	0	0
T62	0	5	0	0
T63	0	9	0	0
T76	0	31	0	0
T85	0	36	0	0
T134	0	16	0	0
T287	0	16	0	0
T304	0	6	0	0
T305	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1505	0	0
T9	211026	14	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T60	0	1	0	0
T62	0	9	0	0
T63	0	2	0	0
T76	0	30	0	0
T85	0	23	0	0
T134	0	4	0	0
T147	0	4	0	0
T287	0	1	0	0
T304	0	3	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224241141	1422	0	0
T9	211026	18	0	0
T10	209240	0	0	0
T11	100245	0	0	0
T12	126953	0	0	0
T25	111076	0	0	0
T28	362621	0	0	0
T38	172231	0	0	0
T42	522737	0	0	0
T46	306396	0	0	0
T58	739128	0	0	0
T60	0	5	0	0
T63	0	1	0	0
T76	0	30	0	0
T85	0	36	0	0
T134	0	8	0	0
T147	0	4	0	0
T287	0	4	0	0
T304	0	5	0	0
T305	0	4	0	0