Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2038

1

T1

10

T2

25

T7

18

auto[1]

738

1

T1

2

T16

3

T11

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2192

1

T1

7

T2

21

T7

8

auto[1]

584

1

T1

5

T2

4

T7

10

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2139

1

T1

7

T2

25

T7

7

auto[1]

637

1

T1

5

T7

11

T16

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2178

1

T1

12

T2

15

T7

15

auto[1]

598

1

T2

10

T7

3

T16

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2516

1

T1

10

T2

25

T7

18

auto[1]

260

1

T1

2

T49

3

T54

6

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2475

1

T1

10

T2

25

T7

18

auto[1]

301

1

T1

2

T12

4

T49

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2495

1

T1

8

T2

25

T7

18

auto[1]

281

1

T1

4

T12

1

T37

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2508

1

T1

5

T2

25

T7

18

auto[1]

268

1

T1

7

T54

6

T37

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2512

1

T1

12

T2

25

T7

18

auto[1]

264

1

T12

3

T37

5

T82

16

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2119

1

T1

8

T2

10

T7

10

auto[1]

657

1

T1

4

T2

15

T7

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

880

1

T2

25

T7

18

T16

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

53

1

T49

3

T54

2

T82

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T12

2

T37

5

T82

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T88

1

T350

9

T351

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

65

1

T1

3

T54

4

T37

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T1

2

T54

2

T230

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T247

7

T352

3

T232

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T98

1

T230

4

T89

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

71

1

T1

2

T81

3

T307

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T37

3

T351

3

T353

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T12

1

T82

2

T39

20

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T354

4

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T355

4

T330

9

T344

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T230

3

T356

2

T183

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T98

3

T357

2

T358

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

74

1

T12

4

T49

3

T39

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

45

1

T357

5

T355

4

T359

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29

1

T98

4

T101

2

T346

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T82

1

T101

2

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T81

3

T40

1

T247

28

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T360

1

T338

2

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T361

4

T254

4

T362

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

33

1

T81

2

T230

8

T363

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T364

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T357

1

T365

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

11

1

T1

2

T89

1

T183

6

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

168

1

T197

9

T82

2

T98

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

126

1

T1

2

T2

11

T37

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

84

1

T81

3

T39

11

T238

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

134

1

T2

10

T82

5

T304

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

73

1

T12

4

T38

7

T71

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T38

6

T122

2

T242

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T246

2

T307

5

T112

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

138

1

T241

14

T230

4

T357

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

107

1

T11

8

T81

5

T39

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

59

1

T1

2

T7

8

T16

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T304

2

T255

2

T366

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T12

2

T49

3

T71

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T97

1

T304

2

T340

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

25

1

T189

2

T122

1

T337

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T189

2

T367

4

T250

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

72

1

T7

7

T11

9

T12

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

79

1

T1

2

T37

5

T367

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

93

1

T2

4

T54

4

T199

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T241

1

T235

3

T163

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T197

5

T235

5

T110

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T16

3

T81

3

T46

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T306

3

T367

2

T242

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T250

1

T244

1

T259

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T1

3

T98

1

T141

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

41

1

T54

2

T46

1

T368

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T135

3

T337

3

T356

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T128

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T7

3

T37

5

T103

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T38

1

T331

1

T332

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T235

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T189

1

T163

1

T369

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded