Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T30

7

T31

12

T78

9

auto[1]

961

1

T30

13

T31

8

T78

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

467

1

T30

5

T31

4

T78

5

from_0to1

455

1

T30

6

T31

4

T78

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T30

10

T31

10

T78

9

auto[1]

957

1

T30

10

T31

10

T78

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T30

11

T31

12

T78

8

auto[1]

982

1

T30

9

T31

8

T78

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T30

1

T379

1

T41

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T30

1

T31

2

T78

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T41

2

T281

1

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T30

1

T379

1

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T31

1

T68

2

T117

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T379

2

T281

1

T117

2

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T31

2

T41

1

T282

2

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T30

1

T78

1

T379

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T31

1

T41

2

T282

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T379

2

T41

1

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T30

2

T31

1

T78

3

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T78

1

T41

1

T282

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T30

2

T78

2

T379

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T30

1

T31

1

T78

2

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T30

1

T41

2

T48

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T30

1

T41

2

T281

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T30

12

T31

8

T78

14

auto[1]

910

1

T30

8

T31

12

T78

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

461

1

T30

4

T31

5

T78

6

from_0to1

451

1

T30

5

T31

4

T78

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T30

10

T31

12

T78

8

auto[1]

932

1

T30

10

T31

8

T78

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T30

14

T31

14

T78

11

auto[1]

945

1

T30

6

T31

6

T78

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T30

1

T31

1

T78

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T30

1

T78

2

T379

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T78

1

T41

1

T282

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T379

1

T48

2

T117

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T30

1

T78

1

T41

2

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T30

1

T78

1

T41

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T30

2

T78

1

T379

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T30

1

T31

1

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T30

1

T31

2

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T31

1

T41

2

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T31

1

T41

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T30

1

T78

1

T379

4

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T31

1

T78

1

T379

3

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T31

1

T41

3

T48

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T31

1

T78

1

T41

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T379

1

T48

1

T68

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

980

1

T30

7

T31

11

T78

14

auto[1]

960

1

T30

13

T31

9

T78

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

459

1

T30

8

T31

6

T78

6

from_0to1

454

1

T30

7

T31

6

T78

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

938

1

T30

5

T31

9

T78

8

auto[1]

1002

1

T30

15

T31

11

T78

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

959

1

T30

9

T31

12

T78

12

auto[1]

981

1

T30

11

T31

8

T78

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T78

2

T41

4

T281

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T78

2

T41

1

T117

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T30

2

T31

2

T78

2

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T31

2

T379

1

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T30

1

T31

1

T41

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T30

1

T41

1

T281

2

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T31

1

T281

1

T282

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T30

1

T31

1

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T379

1

T41

1

T281

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T31

1

T379

1

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T30

2

T379

1

T41

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T30

4

T31

1

T281

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T31

2

T78

1

T41

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T30

2

T31

1

T379

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T30

1

T78

3

T41

4

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T30

1

T379

2

T41

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

975

1

T30

13

T31

11

T78

10

auto[1]

965

1

T30

7

T31

9

T78

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T30

6

T31

5

T78

4

from_0to1

476

1

T30

7

T31

5

T78

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

977

1

T30

12

T31

6

T78

11

auto[1]

963

1

T30

8

T31

14

T78

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

971

1

T30

11

T31

10

T78

9

auto[1]

969

1

T30

9

T31

10

T78

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T30

2

T78

1

T41

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T30

1

T31

1

T379

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T30

2

T31

2

T78

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T31

1

T379

1

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T379

1

T41

1

T68

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T30

1

T31

2

T78

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T31

1

T78

1

T379

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T30

2

T41

1

T281

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T30

1

T78

2

T41

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T379

1

T68

1

T215

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T31

1

T41

3

T48

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T281

1

T48

1

T117

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T379

1

T41

4

T281

2

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T30

1

T78

1

T41

2

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T30

2

T31

1

T41

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T30

1

T31

1

T78

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931

1

T30

10

T31

9

T78

13

auto[1]

1009

1

T30

10

T31

11

T78

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

468

1

T30

4

T31

6

T78

4

from_0to1

463

1

T30

5

T31

7

T78

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

952

1

T30

11

T31

7

T78

12

auto[1]

988

1

T30

9

T31

13

T78

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984

1

T30

9

T31

9

T78

14

auto[1]

956

1

T30

11

T31

11

T78

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T78

1

T379

1

T281

1

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T30

1

T31

1

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T78

1

T379

2

T41

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T31

1

T78

1

T282

2

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T30

2

T78

4

T41

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T31

1

T379

2

T41

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T31

1

T41

1

T281

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T30

1

T31

2

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T30

1

T31

2

T379

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T41

2

T281

1

T68

2

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T31

1

T41

3

T117

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T30

2

T31

1

T78

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T48

1

T68

1

T117

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T41

3

T48

2

T68

3

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T30

1

T31

2

T379

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T30

1

T31

1

T41

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T30

8

T31

11

T78

9

auto[1]

962

1

T30

12

T31

9

T78

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

449

1

T30

5

T31

5

T78

3

from_0to1

461

1

T30

4

T31

4

T78

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

993

1

T30

9

T31

13

T78

12

auto[1]

947

1

T30

11

T31

7

T78

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T30

13

T31

7

T78

11

auto[1]

979

1

T30

7

T31

13

T78

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T30

1

T31

1

T78

2

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T31

1

T379

2

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T41

1

T282

2

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T30

1

T41

1

T281

1

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T30

1

T31

1

T379

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T30

1

T31

1

T78

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T41

2

T281

1

T282

2

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T379

1

T68

1

T117

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T30

1

T78

1

T379

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T41

3

T281

1

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T30

1

T31

1

T379

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T30

1

T31

2

T379

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T30

1

T31

1

T78

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T31

1

T41

2

T281

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T379

1

T41

1

T282

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T30

1

T78

1

T379

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

974

1

T30

11

T31

15

T78

9

auto[1]

966

1

T30

9

T31

5

T78

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

454

1

T30

5

T31

4

T78

3

from_0to1

451

1

T30

5

T31

4

T78

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

926

1

T30

11

T31

6

T78

5

auto[1]

1014

1

T30

9

T31

14

T78

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

968

1

T30

10

T31

11

T78

12

auto[1]

972

1

T30

10

T31

9

T78

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T31

1

T379

2

T41

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T30

2

T379

1

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T30

1

T41

1

T282

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T31

1

T78

1

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T30

1

T379

2

T41

1

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T31

1

T41

1

T68

2

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T30

1

T31

1

T78

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T30

1

T31

1

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T78

1

T41

2

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T30

1

T78

1

T379

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T30

1

T31

2

T41

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T41

2

T68

1

T117

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T30

1

T41

1

T281

2

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T31

1

T41

1

T281

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T30

1

T78

1

T41

2

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T78

1

T379

1

T41

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

974

1

T30

10

T31

14

T78

10

auto[1]

966

1

T30

10

T31

6

T78

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

443

1

T30

4

T31

4

T78

5

from_0to1

447

1

T30

3

T31

5

T78

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

975

1

T30

13

T31

11

T78

8

auto[1]

965

1

T30

7

T31

9

T78

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981

1

T30

11

T31

11

T78

11

auto[1]

959

1

T30

9

T31

9

T78

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T379

1

T41

1

T282

1

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T31

1

T78

1

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T30

1

T78

2

T41

2

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T379

1

T41

1

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T30

1

T31

3

T78

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T379

1

T281

1

T282

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T30

1

T78

1

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T41

1

T281

1

T68

2

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T30

1

T379

1

T281

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T31

2

T78

1

T41

3

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T30

1

T31

1

T379

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T30

1

T78

1

T282

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T78

1

T41

2

T281

1

auto[1]

from_0to1

auto[0]

auto[1]

49

1

T30

1

T31

1

T78

1

auto[1]

from_0to1

auto[1]

auto[0]

48

1

T31

1

T78

1

T117

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T41

1

T281

1

T282

1