Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154327	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115973

1

T4

7

T5

3

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142295	1			T4	9		T5	3		T6	8
values[0x0]	63173	1			T4	1		T5	2		T6	2
values[0x1]	64832	1			T4	2		T6	5		T1	302

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145512

1

T4

8

T5

4

T6

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	911	1			T2	8		T15	1		T12	5
valid_sources[0x01]	1364	1			T1	5		T15	1		T12	9
valid_sources[0x02]	940	1			T2	6		T15	8		T80	1
valid_sources[0x03]	1035	1			T1	2		T2	4		T15	3
valid_sources[0x04]	1005	1			T4	5		T15	7		T78	1
valid_sources[0x05]	1068	1			T1	1		T2	9		T12	5
valid_sources[0x06]	1060	1			T1	5		T2	1		T380	1
valid_sources[0x07]	949	1			T2	1		T15	7		T12	8
valid_sources[0x08]	757	1			T15	8		T17	2		T57	3
valid_sources[0x09]	1958	1			T1	1		T2	5		T56	1
valid_sources[0x0a]	1080	1			T1	5		T12	1		T214	2
valid_sources[0x0b]	1399	1			T2	1		T12	7		T38	1
valid_sources[0x0c]	1001	1			T15	1		T17	1		T56	1
valid_sources[0x0d]	782	1			T2	4		T15	7		T12	3
valid_sources[0x0e]	1053	1			T1	14		T15	3		T80	1
valid_sources[0x0f]	836	1			T33	2		T56	1		T12	3
valid_sources[0x10]	836	1			T1	8		T15	23		T63	1
valid_sources[0x11]	1672	1			T2	1		T12	5		T381	2
valid_sources[0x12]	957	1			T2	2		T15	9		T59	23
valid_sources[0x13]	1007	1			T6	1		T2	3		T15	3
valid_sources[0x14]	870	1			T1	8		T2	3		T15	5
valid_sources[0x15]	1566	1			T1	9		T2	6		T9	4
valid_sources[0x16]	1016	1			T15	2		T26	4		T12	5
valid_sources[0x17]	934	1			T1	2		T2	1		T15	2
valid_sources[0x18]	2845	1			T2	1		T15	1		T56	2
valid_sources[0x19]	1528	1			T2	1		T80	1		T12	3
valid_sources[0x1a]	812	1			T65	1		T41	3		T37	8
valid_sources[0x1b]	845	1			T2	4		T80	1		T12	7
valid_sources[0x1c]	903	1			T2	7		T15	3		T12	6
valid_sources[0x1d]	945	1			T1	3		T2	1		T15	2
valid_sources[0x1e]	1048	1			T1	10		T15	19		T9	3
valid_sources[0x1f]	2029	1			T12	3		T29	1		T77	1
valid_sources[0x20]	1432	1			T2	2		T15	2		T10	1
valid_sources[0x21]	1583	1			T1	4		T2	26		T15	3
valid_sources[0x22]	829	1			T15	1		T63	1		T12	4
valid_sources[0x23]	952	1			T1	14		T15	2		T9	1
valid_sources[0x24]	925	1			T6	1		T1	6		T12	2
valid_sources[0x25]	852	1			T2	4		T15	1		T12	9
valid_sources[0x26]	806	1			T1	2		T2	11		T15	10
valid_sources[0x27]	990	1			T4	1		T1	4		T12	14
valid_sources[0x28]	894	1			T1	4		T2	2		T10	8
valid_sources[0x29]	805	1			T1	7		T2	2		T15	2
valid_sources[0x2a]	1045	1			T1	7		T2	1		T15	1
valid_sources[0x2b]	963	1			T1	1		T2	3		T15	4
valid_sources[0x2c]	1949	1			T2	5		T15	1		T57	3
valid_sources[0x2d]	945	1			T1	5		T62	1		T12	3
valid_sources[0x2e]	945	1			T1	1		T2	4		T9	1
valid_sources[0x2f]	803	1			T2	2		T80	1		T12	6
valid_sources[0x30]	854	1			T2	5		T15	9		T12	2
valid_sources[0x31]	867	1			T15	1		T9	2		T12	6
valid_sources[0x32]	940	1			T2	3		T17	1		T12	1
valid_sources[0x33]	1010	1			T1	13		T15	18		T26	1
valid_sources[0x34]	1664	1			T17	1		T57	1		T26	3
valid_sources[0x35]	1113	1			T1	4		T15	4		T17	1
valid_sources[0x36]	1203	1			T1	2		T2	1		T9	3
valid_sources[0x37]	794	1			T15	5		T379	9		T41	1
valid_sources[0x38]	963	1			T2	2		T80	1		T12	5
valid_sources[0x39]	1022	1			T1	3		T2	5		T62	1
valid_sources[0x3a]	823	1			T4	1		T1	5		T2	2
valid_sources[0x3b]	845	1			T1	19		T2	6		T56	6
valid_sources[0x3c]	923	1			T1	2		T15	10		T57	4
valid_sources[0x3d]	826	1			T1	6		T15	1		T12	1
valid_sources[0x3e]	1579	1			T1	3		T2	3		T15	3
valid_sources[0x3f]	908	1			T1	13		T15	6		T57	1
valid_sources[0x40]	855	1			T6	1		T2	5		T15	1
valid_sources[0x41]	877	1			T1	6		T15	2		T12	2
valid_sources[0x42]	784	1			T1	1		T2	4		T15	1
valid_sources[0x43]	965	1			T2	1		T15	4		T17	1
valid_sources[0x44]	1068	1			T12	5		T37	3		T68	5
valid_sources[0x45]	795	1			T1	6		T78	2		T379	2
valid_sources[0x46]	814	1			T2	1		T15	1		T18	2
valid_sources[0x47]	941	1			T2	1		T12	4		T38	4
valid_sources[0x48]	1352	1			T2	2		T15	3		T12	3
valid_sources[0x49]	1093	1			T2	17		T15	2		T78	1
valid_sources[0x4a]	986	1			T33	2		T9	1		T12	3
valid_sources[0x4b]	867	1			T6	1		T2	4		T15	13
valid_sources[0x4c]	1045	1			T1	9		T2	3		T15	5
valid_sources[0x4d]	1408	1			T1	1		T12	5		T38	4
valid_sources[0x4e]	879	1			T2	2		T15	3		T80	1
valid_sources[0x4f]	1407	1			T17	1		T12	5		T77	3
valid_sources[0x50]	791	1			T2	1		T15	7		T12	4
valid_sources[0x51]	1423	1			T2	6		T14	33		T9	3
valid_sources[0x52]	847	1			T2	3		T15	6		T17	1
valid_sources[0x53]	860	1			T1	1		T18	1		T12	6
valid_sources[0x54]	849	1			T2	5		T12	5		T65	1
valid_sources[0x55]	1147	1			T4	1		T1	7		T2	9
valid_sources[0x56]	1086	1			T1	37		T2	3		T15	1
valid_sources[0x57]	911	1			T6	1		T1	17		T15	4
valid_sources[0x58]	954	1			T1	19		T56	2		T80	1
valid_sources[0x59]	973	1			T2	1		T80	1		T12	2
valid_sources[0x5a]	977	1			T4	3		T15	1		T12	4
valid_sources[0x5b]	913	1			T1	8		T15	1		T379	1
valid_sources[0x5c]	912	1			T2	4		T15	8		T12	4
valid_sources[0x5d]	952	1			T12	8		T78	2		T38	5
valid_sources[0x5e]	994	1			T15	5		T17	1		T12	7
valid_sources[0x5f]	888	1			T1	4		T15	2		T12	3
valid_sources[0x60]	963	1			T1	1		T2	5		T12	5
valid_sources[0x61]	1028	1			T2	2		T15	1		T12	6
valid_sources[0x62]	1418	1			T1	5		T2	19		T57	2
valid_sources[0x63]	850	1			T15	13		T56	3		T12	4
valid_sources[0x64]	896	1			T2	6		T15	1		T12	6
valid_sources[0x65]	1129	1			T1	2		T2	1		T12	4
valid_sources[0x66]	1368	1			T1	1		T15	9		T12	4
valid_sources[0x67]	880	1			T15	5		T12	8		T78	1
valid_sources[0x68]	2415	1			T2	18		T15	5		T17	2
valid_sources[0x69]	1036	1			T1	7		T15	8		T12	6
valid_sources[0x6a]	813	1			T2	3		T15	5		T12	4
valid_sources[0x6b]	1177	1			T15	8		T17	1		T9	5
valid_sources[0x6c]	842	1			T2	2		T15	5		T12	5
valid_sources[0x6d]	927	1			T1	12		T56	2		T12	5
valid_sources[0x6e]	1012	1			T1	16		T2	4		T57	5
valid_sources[0x6f]	991	1			T2	2		T3	19		T15	7
valid_sources[0x70]	1073	1			T2	12		T15	4		T56	1
valid_sources[0x71]	1003	1			T1	4		T2	1		T15	4
valid_sources[0x72]	1114	1			T15	1		T17	2		T80	1
valid_sources[0x73]	932	1			T1	11		T2	2		T12	4
valid_sources[0x74]	964	1			T15	2		T17	1		T12	3
valid_sources[0x75]	1159	1			T1	2		T15	1		T18	1
valid_sources[0x76]	1044	1			T2	3		T15	10		T17	1
valid_sources[0x77]	915	1			T1	6		T2	1		T80	1
valid_sources[0x78]	1024	1			T1	13		T2	9		T15	3
valid_sources[0x79]	1207	1			T1	18		T2	4		T56	2
valid_sources[0x7a]	1173	1			T2	4		T12	4		T38	6
valid_sources[0x7b]	951	1			T2	2		T15	6		T12	6
valid_sources[0x7c]	884	1			T6	1		T15	1		T80	2
valid_sources[0x7d]	957	1			T15	2		T8	15		T12	5
valid_sources[0x7e]	837	1			T1	3		T12	10		T77	1
valid_sources[0x7f]	898	1			T1	3		T15	3		T12	4
valid_sources[0x80]	1010	1			T6	2		T1	5		T2	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63784

1

T4

6

T5

2

T6

3

values[0x0]

all_enables

biggest_size

30478

1

T4

1

T5

1

T6

2

values[0x1]

all_enables

biggest_size

21711

1

T6

2

T1

65

T2

51