Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T43,T44
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T43,T44
0	1	Covered	T9,T118,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T43,T44
0	1	Covered	T43,T44,T100
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T43,T44
1	-	Covered	T43,T44,T100

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T43,T44
DetectSt	168	Covered	T9,T43,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T43,T44
DebounceSt->IdleSt	163	Covered	T71,T155
DetectSt->IdleSt	186	Covered	T9,T118,T96
DetectSt->StableSt	191	Covered	T9,T43,T44
IdleSt->DebounceSt	148	Covered	T9,T43,T44
StableSt->IdleSt	206	Covered	T9,T43,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T43,T44
0	1	Covered	T9,T43,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T43,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T155
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T43,T44
DetectSt	-	-	-	-	1	-	-	Covered	T9,T118,T96
DetectSt	-	-	-	-	0	1	-	Covered	T9,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T44,T100
StableSt	-	-	-	-	-	-	0	Covered	T9,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	109	0	0
CntIncr_A	6669080	32603	0	0
CntNoWrap_A	6669080	6021229	0	0
DetectStDropOut_A	6669080	4	0	0
DetectedOut_A	6669080	23993	0	0
DetectedPulseOut_A	6669080	50	0	0
DisabledIdleSt_A	6669080	5861670	0	0
DisabledNoDetection_A	6669080	5863998	0	0
EnterDebounceSt_A	6669080	56	0	0
EnterDetectSt_A	6669080	54	0	0
EnterStableSt_A	6669080	50	0	0
PulseIsPulse_A	6669080	50	0	0
StayInStableSt	6669080	23920	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	109	0	0
T9	2326	4	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	4	0	0
T43	0	4	0	0
T44	0	2	0	0
T46	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T118	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	32603	0	0
T9	2326	54	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	131	0	0
T43	0	102	0	0
T44	0	61	0	0
T46	0	14	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	17	0	0
T80	443	0	0	0
T85	0	33	0	0
T100	0	82	0	0
T118	0	40	0	0
T149	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021229	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	4	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T96	0	1	0	0
T118	0	1	0	0
T171	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	23993	0	0
T9	2326	43	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	78	0	0
T43	0	43	0	0
T44	0	238	0	0
T46	0	117	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	43	0	0
T100	0	73	0	0
T123	0	63	0	0
T149	0	113	0	0
T150	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	50	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T123	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5861670	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5863998	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	56	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T118	0	1	0	0
T149	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	54	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T118	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	50	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T123	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	50	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T123	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	23920	0	0
T9	2326	41	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	74	0	0
T43	0	40	0	0
T44	0	237	0	0
T46	0	115	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	42	0	0
T100	0	72	0	0
T123	0	61	0	0
T149	0	111	0	0
T150	0	89	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	25	0	0
T37	19642	0	0	0
T41	8850	0	0	0
T43	897	1	0	0
T44	1037	1	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	421	0	0	0
T154	978	0	0	0
T169	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	409	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T13,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T43
1	0	Covered	T5,T1,T2
1	1	Covered	T9,T13,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T43
0	1	Covered	T13,T41
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T43
0	1	Covered	T9,T13,T43
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T43
1	-	Covered	T9,T13,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T13,T43
DetectSt	168	Covered	T9,T13,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T13,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T13,T43
DebounceSt->IdleSt	163	Covered	T100,T47,T175
DetectSt->IdleSt	186	Covered	T13,T41
DetectSt->StableSt	191	Covered	T9,T13,T43
IdleSt->DebounceSt	148	Covered	T9,T13,T43
StableSt->IdleSt	206	Covered	T9,T13,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T13,T43
0	1	Covered	T9,T13,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T13,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T13,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T13,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T175,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T13,T43
DetectSt	-	-	-	-	1	-	-	Covered	T13,T41
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T13,T43
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	156	0	0
CntIncr_A	6669080	58413	0	0
CntNoWrap_A	6669080	6021182	0	0
DetectStDropOut_A	6669080	2	0	0
DetectedOut_A	6669080	5656	0	0
DetectedPulseOut_A	6669080	73	0	0
DisabledIdleSt_A	6669080	5947190	0	0
DisabledNoDetection_A	6669080	5949515	0	0
EnterDebounceSt_A	6669080	83	0	0
EnterDetectSt_A	6669080	75	0	0
EnterStableSt_A	6669080	73	0	0
PulseIsPulse_A	6669080	73	0	0
StayInStableSt	6669080	5557	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	2897	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	156	0	0
T9	2326	4	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	4	0	0
T26	123078	0	0	0
T41	0	4	0	0
T43	0	4	0	0
T46	0	6	0	0
T47	0	3	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	2	0	0
T80	443	0	0	0
T85	0	4	0	0
T100	0	6	0	0
T176	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	58413	0	0
T9	2326	54	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	70	0	0
T26	123078	0	0	0
T41	0	131	0	0
T43	0	102	0	0
T46	0	133	0	0
T47	0	114	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	29	0	0
T80	443	0	0	0
T85	0	66	0	0
T100	0	37351	0	0
T176	0	162	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021182	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	1	0	0
T45	503	0	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5656	0	0
T9	2326	110	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	142	0	0
T26	123078	0	0	0
T41	0	56	0	0
T43	0	153	0	0
T46	0	234	0	0
T47	0	40	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T80	443	0	0	0
T85	0	99	0	0
T100	0	272	0	0
T176	0	171	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	73	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	1	0	0
T26	123078	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	3	0	0
T176	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5947190	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5949515	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	83	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T46	0	3	0	0
T47	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	4	0	0
T176	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	75	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	3	0	0
T176	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	73	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	1	0	0
T26	123078	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	3	0	0
T176	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	73	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	1	0	0
T26	123078	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	3	0	0
T176	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5557	0	0
T9	2326	108	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	141	0	0
T26	123078	0	0	0
T41	0	55	0	0
T43	0	151	0	0
T46	0	230	0	0
T47	0	39	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	96	0	0
T100	0	268	0	0
T123	0	132	0	0
T176	0	169	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2897	0	0
T1	11087	0	0	0
T2	29615	0	0	0
T3	687	0	0	0
T5	856	4	0	0
T6	606	0	0	0
T7	21017	0	0	0
T8	0	1	0	0
T14	433	4	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	6	0	0
T18	0	3	0	0
T30	0	4	0	0
T31	0	5	0	0
T32	0	4	0	0
T62	0	5	0	0
T63	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	45	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	1	0	0
T26	123078	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	2	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T13,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T45
1	0	Covered	T4,T1,T2
1	1	Covered	T8,T13,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T45
0	1	Covered	T177,T178,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T45
0	1	Covered	T8,T13,T43
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T45
1	-	Covered	T8,T13,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T13,T45
DetectSt	168	Covered	T8,T13,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T13,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T45
DebounceSt->IdleSt	163	Covered	T85,T93,T161
DetectSt->IdleSt	186	Covered	T177,T178,T179
DetectSt->StableSt	191	Covered	T8,T13,T45
IdleSt->DebounceSt	148	Covered	T8,T13,T45
StableSt->IdleSt	206	Covered	T8,T13,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T13,T45
0	1	Covered	T8,T13,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T13,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T161,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T13,T45
DetectSt	-	-	-	-	1	-	-	Covered	T177,T178,T179
DetectSt	-	-	-	-	0	1	-	Covered	T8,T13,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T13,T43
StableSt	-	-	-	-	-	-	0	Covered	T8,T13,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	168	0	0
CntIncr_A	6669080	113783	0	0
CntNoWrap_A	6669080	6021170	0	0
DetectStDropOut_A	6669080	3	0	0
DetectedOut_A	6669080	29043	0	0
DetectedPulseOut_A	6669080	78	0	0
DisabledIdleSt_A	6669080	5808716	0	0
DisabledNoDetection_A	6669080	5811041	0	0
EnterDebounceSt_A	6669080	88	0	0
EnterDetectSt_A	6669080	81	0	0
EnterStableSt_A	6669080	78	0	0
PulseIsPulse_A	6669080	78	0	0
StayInStableSt	6669080	28936	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	47	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	168	0	0
T8	558	4	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	4	0	0
T26	123078	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	0	10	0	0
T48	0	4	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	4	0	0
T118	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	113783	0	0
T8	558	28	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	70	0	0
T26	123078	0	0	0
T41	0	73	0	0
T42	0	74	0	0
T43	0	51	0	0
T45	0	23	0	0
T46	0	144	0	0
T48	0	96	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	164	0	0
T118	0	120	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021170	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	3	0	0
T60	7988	0	0	0
T177	857	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T181	403	0	0	0
T182	502	0	0	0
T183	18821	0	0	0
T184	449	0	0	0
T185	638	0	0	0
T186	521	0	0	0
T187	668	0	0	0
T188	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	29043	0	0
T8	558	80	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	162	0	0
T26	123078	0	0	0
T41	0	593	0	0
T42	0	2	0	0
T43	0	270	0	0
T45	0	70	0	0
T46	0	350	0	0
T48	0	114	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	87	0	0
T118	0	126	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	78	0	0
T8	558	2	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	5	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	2	0	0
T118	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5808716	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5811041	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	88	0	0
T8	558	2	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	5	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	2	0	0
T118	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	81	0	0
T8	558	2	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	5	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	2	0	0
T118	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	78	0	0
T8	558	2	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	5	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	2	0	0
T118	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	78	0	0
T8	558	2	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	5	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	2	0	0
T118	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	28936	0	0
T8	558	77	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	160	0	0
T26	123078	0	0	0
T41	0	591	0	0
T43	0	269	0	0
T45	0	68	0	0
T46	0	343	0	0
T47	0	40	0	0
T48	0	111	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T100	0	84	0	0
T118	0	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T8	558	1	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	1	0	0
T118	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T43,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T43,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T43,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T45,T43
1	0	Covered	T4,T1,T2
1	1	Covered	T9,T43,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T43,T48
0	1	Covered	T118
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T43,T48
0	1	Covered	T9,T48,T118
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T43,T48
1	-	Covered	T9,T48,T118

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T43,T48
DetectSt	168	Covered	T9,T43,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T43,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T43,T48
DebounceSt->IdleSt	163	Covered	T100
DetectSt->IdleSt	186	Covered	T118
DetectSt->StableSt	191	Covered	T9,T43,T48
IdleSt->DebounceSt	148	Covered	T9,T43,T48
StableSt->IdleSt	206	Covered	T9,T48,T118

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T43,T48
0	1	Covered	T9,T43,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T43,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T43,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T43,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T100
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T43,T48
DetectSt	-	-	-	-	1	-	-	Covered	T118
DetectSt	-	-	-	-	0	1	-	Covered	T9,T43,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T48,T118
StableSt	-	-	-	-	-	-	0	Covered	T9,T43,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	101	0	0
CntIncr_A	6669080	87167	0	0
CntNoWrap_A	6669080	6021237	0	0
DetectStDropOut_A	6669080	1	0	0
DetectedOut_A	6669080	2762	0	0
DetectedPulseOut_A	6669080	49	0	0
DisabledIdleSt_A	6669080	5792098	0	0
DisabledNoDetection_A	6669080	5794429	0	0
EnterDebounceSt_A	6669080	51	0	0
EnterDetectSt_A	6669080	50	0	0
EnterStableSt_A	6669080	49	0	0
PulseIsPulse_A	6669080	49	0	0
StayInStableSt	6669080	2689	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	6388	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	101	0	0
T9	2326	4	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	2	0	0
T46	0	6	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T93	0	2	0	0
T100	0	3	0	0
T118	0	4	0	0
T135	0	2	0	0
T176	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	87167	0	0
T9	2326	54	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	51	0	0
T46	0	79	0	0
T48	0	48	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	33	0	0
T93	0	82	0	0
T100	0	169	0	0
T118	0	80	0	0
T135	0	52	0	0
T176	0	162	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021237	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1	0	0
T71	29489	0	0	0
T72	495	0	0	0
T83	1374	0	0	0
T99	729	0	0	0
T118	818	1	0	0
T119	422	0	0	0
T120	906	0	0	0
T121	530	0	0	0
T189	10831	0	0	0
T190	515	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2762	0	0
T9	2326	85	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	114	0	0
T46	0	50	0	0
T48	0	40	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	23	0	0
T93	0	42	0	0
T100	0	73	0	0
T118	0	25	0	0
T135	0	41	0	0
T176	0	223	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	49	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	1	0	0
T46	0	3	0	0
T48	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	1	0	0
T118	0	1	0	0
T135	0	1	0	0
T176	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5792098	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5794429	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	51	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	1	0	0
T46	0	3	0	0
T48	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	2	0	0
T118	0	2	0	0
T135	0	1	0	0
T176	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	50	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	1	0	0
T46	0	3	0	0
T48	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	1	0	0
T118	0	2	0	0
T135	0	1	0	0
T176	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	49	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	1	0	0
T46	0	3	0	0
T48	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	1	0	0
T118	0	1	0	0
T135	0	1	0	0
T176	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	49	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	1	0	0
T46	0	3	0	0
T48	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	1	0	0
T118	0	1	0	0
T135	0	1	0	0
T176	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2689	0	0
T9	2326	82	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T43	0	112	0	0
T46	0	47	0	0
T48	0	39	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	22	0	0
T93	0	40	0	0
T100	0	72	0	0
T118	0	24	0	0
T135	0	39	0	0
T176	0	221	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6388	0	0
T1	11087	24	0	0
T2	29615	10	0	0
T3	687	2	0	0
T4	520	1	0	0
T5	856	0	0	0
T6	606	0	0	0
T7	21017	12	0	0
T14	433	3	0	0
T15	8200	25	0	0
T16	12100	11	0	0
T17	0	5	0	0
T30	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	23	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T46	0	3	0	0
T48	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T118	0	1	0	0
T176	0	2	0	0
T177	0	2	0	0
T191	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T45,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T45,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T45,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T45,T44
1	0	Covered	T1,T2,T14
1	1	Covered	T9,T45,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T45,T44
0	1	Covered	T100,T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T45,T44
0	1	Covered	T9,T44,T41
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T45,T44
1	-	Covered	T9,T44,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T45,T44
DetectSt	168	Covered	T9,T45,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T45,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T45,T44
DebounceSt->IdleSt	163	Covered	T100,T93,T96
DetectSt->IdleSt	186	Covered	T100,T193
DetectSt->StableSt	191	Covered	T9,T45,T44
IdleSt->DebounceSt	148	Covered	T9,T45,T44
StableSt->IdleSt	206	Covered	T9,T44,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T45,T44
0	1	Covered	T9,T45,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T45,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T45,T44
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T45,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T96,T177,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T45,T44
DetectSt	-	-	-	-	1	-	-	Covered	T100,T193
DetectSt	-	-	-	-	0	1	-	Covered	T9,T45,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T44,T41
StableSt	-	-	-	-	-	-	0	Covered	T9,T45,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	152	0	0
CntIncr_A	6669080	110207	0	0
CntNoWrap_A	6669080	6021186	0	0
DetectStDropOut_A	6669080	2	0	0
DetectedOut_A	6669080	85625	0	0
DetectedPulseOut_A	6669080	71	0	0
DisabledIdleSt_A	6669080	5743987	0	0
DisabledNoDetection_A	6669080	5746312	0	0
EnterDebounceSt_A	6669080	82	0	0
EnterDetectSt_A	6669080	73	0	0
EnterStableSt_A	6669080	71	0	0
PulseIsPulse_A	6669080	71	0	0
StayInStableSt	6669080	85525	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	152	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	8	0	0
T42	0	2	0	0
T44	0	6	0	0
T45	0	2	0	0
T48	0	4	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	4	0	0
T100	0	6	0	0
T158	0	4	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	110207	0	0
T9	2326	27	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	277	0	0
T42	0	37	0	0
T44	0	183	0	0
T45	0	23	0	0
T48	0	96	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	30	0	0
T100	0	37350	0	0
T158	0	42	0	0
T194	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021186	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2	0	0
T46	17300	0	0	0
T47	749	0	0	0
T81	23609	0	0	0
T100	44878	1	0	0
T193	0	1	0	0
T195	654	0	0	0
T196	423	0	0	0
T197	31794	0	0	0
T198	746	0	0	0
T199	19819	0	0	0
T200	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	85625	0	0
T9	2326	67	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	472	0	0
T42	0	202	0	0
T44	0	122	0	0
T45	0	70	0	0
T48	0	29	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	108	0	0
T100	0	222	0	0
T158	0	80	0	0
T194	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	71	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	4	0	0
T42	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T158	0	2	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5743987	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5746312	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	82	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	4	0	0
T42	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	4	0	0
T158	0	2	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	73	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	4	0	0
T42	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	3	0	0
T158	0	2	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	71	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	4	0	0
T42	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T158	0	2	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	71	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	4	0	0
T42	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T158	0	2	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	85525	0	0
T9	2326	66	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	465	0	0
T42	0	201	0	0
T44	0	119	0	0
T45	0	68	0	0
T48	0	27	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	105	0	0
T100	0	219	0	0
T158	0	77	0	0
T194	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	40	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	3	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	1	0	0
T123	0	1	0	0
T158	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T44,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T44,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T44,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T44
1	0	Covered	T1,T2,T14
1	1	Covered	T9,T44,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T44,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T44,T41
0	1	Covered	T44,T41,T48
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T44,T41
1	-	Covered	T44,T41,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T44,T41
DetectSt	168	Covered	T9,T44,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T44,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T44,T41
DebounceSt->IdleSt	163	Covered	T96
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T44,T41
IdleSt->DebounceSt	148	Covered	T9,T44,T41
StableSt->IdleSt	206	Covered	T9,T44,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T44,T41
0	1	Covered	T9,T44,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T44,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T44,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T44,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T96
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T44,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T44,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T41,T48
StableSt	-	-	-	-	-	-	0	Covered	T9,T44,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	95	0	0
CntIncr_A	6669080	2475	0	0
CntNoWrap_A	6669080	6021243	0	0
DetectStDropOut_A	6669080	0	0	0
DetectedOut_A	6669080	3546	0	0
DetectedPulseOut_A	6669080	47	0	0
DisabledIdleSt_A	6669080	5811457	0	0
DisabledNoDetection_A	6669080	5813785	0	0
EnterDebounceSt_A	6669080	48	0	0
EnterDetectSt_A	6669080	47	0	0
EnterStableSt_A	6669080	47	0	0
PulseIsPulse_A	6669080	47	0	0
StayInStableSt	6669080	3474	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	6167	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	95	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	2	0	0
T44	0	6	0	0
T46	0	2	0	0
T48	0	4	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2475	0	0
T9	2326	27	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	73	0	0
T44	0	183	0	0
T46	0	51	0	0
T48	0	96	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	15	0	0
T100	0	58	0	0
T149	0	39	0	0
T150	0	41	0	0
T176	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021243	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	3546	0	0
T9	2326	142	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	125	0	0
T44	0	134	0	0
T46	0	36	0	0
T48	0	223	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	64	0	0
T100	0	45	0	0
T149	0	112	0	0
T150	0	87	0	0
T176	0	500	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5811457	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5813785	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	48	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	3474	0	0
T9	2326	140	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T26	123078	0	0	0
T41	0	124	0	0
T44	0	130	0	0
T46	0	35	0	0
T48	0	220	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T85	0	63	0	0
T100	0	43	0	0
T149	0	110	0	0
T150	0	85	0	0
T176	0	498	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6167	0	0
T1	11087	31	0	0
T2	29615	11	0	0
T3	687	0	0	0
T7	21017	14	0	0
T14	433	3	0	0
T15	8200	25	0	0
T16	12100	11	0	0
T17	496	7	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	0	6	0	0
T31	0	4	0	0
T32	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	20	0	0
T37	19642	0	0	0
T41	8850	1	0	0
T44	1037	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T54	8521	0	0	0
T55	2417	0	0	0
T66	610	0	0	0
T67	1707	0	0	0
T69	495	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T96	0	2	0	0
T152	0	1	0	0
T153	421	0	0	0
T154	978	0	0	0
T173	0	1	0	0
T201	0	1	0	0