Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T43,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T43,T41,T42
1	0	Covered	T1,T2,T14
1	1	Covered	T43,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T41,T42
0	1	Covered	T202,T203,T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T41,T42
0	1	Covered	T43,T41,T48
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T41,T42
1	-	Covered	T43,T41,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T43,T41,T42
DetectSt	168	Covered	T43,T41,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T43,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T41,T42
DebounceSt->IdleSt	163	Covered	T100,T204,T130
DetectSt->IdleSt	186	Covered	T202,T203,T193
DetectSt->StableSt	191	Covered	T43,T41,T42
IdleSt->DebounceSt	148	Covered	T43,T41,T42
StableSt->IdleSt	206	Covered	T43,T41,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T43,T41,T42
0	1	Covered	T43,T41,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T41,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T43,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T100,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T43,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T202,T203,T193
DetectSt	-	-	-	-	0	1	-	Covered	T43,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T41,T48
StableSt	-	-	-	-	-	-	0	Covered	T43,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	158	0	0
CntIncr_A	6669080	38828	0	0
CntNoWrap_A	6669080	6021180	0	0
DetectStDropOut_A	6669080	3	0	0
DetectedOut_A	6669080	5595	0	0
DetectedPulseOut_A	6669080	75	0	0
DisabledIdleSt_A	6669080	5938758	0	0
DisabledNoDetection_A	6669080	5941090	0	0
EnterDebounceSt_A	6669080	81	0	0
EnterDetectSt_A	6669080	78	0	0
EnterStableSt_A	6669080	75	0	0
PulseIsPulse_A	6669080	75	0	0
StayInStableSt	6669080	5488	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	158	0	0
T37	19642	0	0	0
T41	8850	6	0	0
T42	0	2	0	0
T43	897	4	0	0
T44	1037	0	0	0
T48	0	6	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	4	0	0
T100	0	5	0	0
T118	0	6	0	0
T149	0	4	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	4	0	0
T174	409	0	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	38828	0	0
T37	19642	0	0	0
T41	8850	219	0	0
T42	0	37	0	0
T43	897	102	0	0
T44	1037	0	0	0
T48	0	144	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	164	0	0
T100	0	222	0	0
T118	0	120	0	0
T149	0	78	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	42	0	0
T174	409	0	0	0
T194	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021180	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	3	0	0
T115	7809	0	0	0
T193	0	1	0	0
T202	14661	1	0	0
T203	0	1	0	0
T205	422	0	0	0
T206	441	0	0	0
T207	1492	0	0	0
T208	1153	0	0	0
T209	9947	0	0	0
T210	5366	0	0	0
T211	502	0	0	0
T212	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5595	0	0
T37	19642	0	0	0
T41	8850	98	0	0
T42	0	162	0	0
T43	897	22	0	0
T44	1037	0	0	0
T48	0	154	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	178	0	0
T100	0	117	0	0
T118	0	182	0	0
T149	0	116	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	39	0	0
T174	409	0	0	0
T194	0	168	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	75	0	0
T37	19642	0	0	0
T41	8850	3	0	0
T42	0	1	0	0
T43	897	2	0	0
T44	1037	0	0	0
T48	0	3	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	2	0	0
T100	0	2	0	0
T118	0	3	0	0
T149	0	2	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	2	0	0
T174	409	0	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5938758	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5941090	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	81	0	0
T37	19642	0	0	0
T41	8850	3	0	0
T42	0	1	0	0
T43	897	2	0	0
T44	1037	0	0	0
T48	0	3	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	2	0	0
T100	0	3	0	0
T118	0	3	0	0
T149	0	2	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	2	0	0
T174	409	0	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	78	0	0
T37	19642	0	0	0
T41	8850	3	0	0
T42	0	1	0	0
T43	897	2	0	0
T44	1037	0	0	0
T48	0	3	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	2	0	0
T100	0	2	0	0
T118	0	3	0	0
T149	0	2	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	2	0	0
T174	409	0	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	75	0	0
T37	19642	0	0	0
T41	8850	3	0	0
T42	0	1	0	0
T43	897	2	0	0
T44	1037	0	0	0
T48	0	3	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	2	0	0
T100	0	2	0	0
T118	0	3	0	0
T149	0	2	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	2	0	0
T174	409	0	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	75	0	0
T37	19642	0	0	0
T41	8850	3	0	0
T42	0	1	0	0
T43	897	2	0	0
T44	1037	0	0	0
T48	0	3	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	2	0	0
T100	0	2	0	0
T118	0	3	0	0
T149	0	2	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	2	0	0
T174	409	0	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5488	0	0
T37	19642	0	0	0
T41	8850	95	0	0
T42	0	160	0	0
T43	897	20	0	0
T44	1037	0	0	0
T48	0	150	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	175	0	0
T100	0	114	0	0
T118	0	178	0	0
T149	0	113	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	36	0	0
T174	409	0	0	0
T194	0	166	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	41	0	0
T37	19642	0	0	0
T41	8850	3	0	0
T43	897	2	0	0
T44	1037	0	0	0
T48	0	2	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T93	0	1	0	0
T100	0	1	0	0
T118	0	2	0	0
T149	0	1	0	0
T152	0	2	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	1	0	0
T173	0	1	0	0
T174	409	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T46,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T45,T46,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T45,T41
1	0	Covered	T1,T2,T14
1	1	Covered	T45,T46,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Covered	T46,T47,T149
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T47
1	-	Covered	T46,T47,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T45,T46,T47
DetectSt	168	Covered	T45,T46,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T45,T46,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T46,T47
DebounceSt->IdleSt	163	Covered	T96,T147,T130
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T45,T46,T47
IdleSt->DebounceSt	148	Covered	T45,T46,T47
StableSt->IdleSt	206	Covered	T46,T47,T149

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T46,T47
0	1	Covered	T45,T46,T47
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T46,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T96,T147,T130
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T46,T47
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T47,T149
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	105	0	0
CntIncr_A	6669080	32651	0	0
CntNoWrap_A	6669080	6021233	0	0
DetectStDropOut_A	6669080	0	0	0
DetectedOut_A	6669080	3345	0	0
DetectedPulseOut_A	6669080	51	0	0
DisabledIdleSt_A	6669080	5827778	0	0
DisabledNoDetection_A	6669080	5830107	0	0
EnterDebounceSt_A	6669080	54	0	0
EnterDetectSt_A	6669080	51	0	0
EnterStableSt_A	6669080	51	0	0
PulseIsPulse_A	6669080	51	0	0
StayInStableSt	6669080	3271	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	6143	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	105	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	2	0	0
T46	0	6	0	0
T47	0	4	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	4	0	0
T123	0	2	0	0
T149	0	2	0	0
T151	0	4	0	0
T158	0	2	0	0
T159	0	2	0	0
T213	0	2	0	0
T214	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	32651	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	23	0	0
T46	0	170	0	0
T47	0	114	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	66	0	0
T123	0	19	0	0
T149	0	39	0	0
T151	0	182	0	0
T158	0	21	0	0
T159	0	33	0	0
T213	0	63	0	0
T214	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021233	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	3345	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	41	0	0
T46	0	101	0	0
T47	0	80	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	84	0	0
T123	0	60	0	0
T149	0	41	0	0
T151	0	259	0	0
T158	0	60	0	0
T159	0	77	0	0
T213	0	110	0	0
T214	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	51	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T213	0	1	0	0
T214	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5827778	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5830107	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	54	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T213	0	1	0	0
T214	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	51	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T213	0	1	0	0
T214	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	51	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T213	0	1	0	0
T214	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	51	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T213	0	1	0	0
T214	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	3271	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	39	0	0
T46	0	97	0	0
T47	0	77	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T85	0	81	0	0
T123	0	59	0	0
T149	0	40	0	0
T151	0	256	0	0
T158	0	59	0	0
T159	0	75	0	0
T213	0	109	0	0
T214	406	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6143	0	0
T1	11087	21	0	0
T2	29615	15	0	0
T3	687	0	0	0
T7	21017	13	0	0
T14	433	3	0	0
T15	8200	30	0	0
T16	12100	6	0	0
T17	496	9	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	0	5	0	0
T31	0	4	0	0
T32	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	26	0	0
T46	17300	2	0	0
T47	749	1	0	0
T73	495	0	0	0
T85	0	1	0	0
T96	0	1	0	0
T123	0	1	0	0
T149	685	1	0	0
T151	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0
T200	425	0	0	0
T213	0	1	0	0
T215	501	0	0	0
T216	426	0	0	0
T217	425	0	0	0
T218	402	0	0	0
T219	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T13
1	0	Covered	T1,T2,T14
1	1	Covered	T8,T9,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T43
0	1	Covered	T8,T42,T177
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T43
0	1	Covered	T9,T13,T43
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T43
1	-	Covered	T9,T13,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T13
DetectSt	168	Covered	T8,T9,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T13,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T13
DebounceSt->IdleSt	163	Covered	T176,T161,T179
DetectSt->IdleSt	186	Covered	T8,T42,T177
DetectSt->StableSt	191	Covered	T9,T13,T43
IdleSt->DebounceSt	148	Covered	T8,T9,T13
StableSt->IdleSt	206	Covered	T9,T13,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T13
0	1	Covered	T8,T9,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T13
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T176,T161,T179
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T13
DetectSt	-	-	-	-	1	-	-	Covered	T8,T42,T177
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T13,T43
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	160	0	0
CntIncr_A	6669080	63725	0	0
CntNoWrap_A	6669080	6021178	0	0
DetectStDropOut_A	6669080	5	0	0
DetectedOut_A	6669080	6152	0	0
DetectedPulseOut_A	6669080	73	0	0
DisabledIdleSt_A	6669080	5816320	0	0
DisabledNoDetection_A	6669080	5818641	0	0
EnterDebounceSt_A	6669080	82	0	0
EnterDetectSt_A	6669080	78	0	0
EnterStableSt_A	6669080	73	0	0
PulseIsPulse_A	6669080	73	0	0
StayInStableSt	6669080	6042	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	160	0	0
T8	558	2	0	0
T9	2326	4	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	4	0	0
T26	123078	0	0	0
T41	0	4	0	0
T42	0	4	0	0
T43	0	2	0	0
T48	0	4	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	2	0	0
T79	0	2	0	0
T80	443	0	0	0
T118	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	63725	0	0
T8	558	14	0	0
T9	2326	54	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	70	0	0
T26	123078	0	0	0
T41	0	131	0	0
T42	0	74	0	0
T43	0	51	0	0
T48	0	96	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	29	0	0
T79	0	97	0	0
T80	443	0	0	0
T118	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021178	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5	0	0
T8	558	1	0	0
T9	2326	0	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T26	123078	0	0	0
T42	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T145	0	1	0	0
T177	0	1	0	0
T220	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6152	0	0
T9	2326	210	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	100	0	0
T26	123078	0	0	0
T41	0	96	0	0
T42	0	81	0	0
T43	0	114	0	0
T46	0	67	0	0
T48	0	260	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	19	0	0
T79	0	43	0	0
T80	443	0	0	0
T118	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	73	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T79	0	1	0	0
T80	443	0	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5816320	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5818641	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	82	0	0
T8	558	1	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T79	0	1	0	0
T80	443	0	0	0
T118	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	78	0	0
T8	558	1	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T79	0	1	0	0
T80	443	0	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	73	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T79	0	1	0	0
T80	443	0	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	73	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	2	0	0
T26	123078	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	1	0	0
T79	0	1	0	0
T80	443	0	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6042	0	0
T9	2326	207	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	97	0	0
T26	123078	0	0	0
T41	0	93	0	0
T42	0	79	0	0
T43	0	113	0	0
T46	0	64	0	0
T48	0	257	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T71	0	17	0	0
T79	0	41	0	0
T80	443	0	0	0
T118	0	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	34	0	0
T9	2326	1	0	0
T10	1473	0	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	0	1	0	0
T26	123078	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T118	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T43,T44
1	0	Covered	T1,T2,T14
1	1	Covered	T13,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T43,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T43,T44
0	1	Covered	T13,T44,T48
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T43,T44
1	-	Covered	T13,T44,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T43,T44
DetectSt	168	Covered	T13,T43,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T43,T44
DebounceSt->IdleSt	163	Covered	T147
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T13,T43,T44
IdleSt->DebounceSt	148	Covered	T13,T43,T44
StableSt->IdleSt	206	Covered	T13,T44,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T43,T44
0	1	Covered	T13,T43,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T43,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T147
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T43,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T44,T48
StableSt	-	-	-	-	-	-	0	Covered	T13,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	83	0	0
CntIncr_A	6669080	32018	0	0
CntNoWrap_A	6669080	6021255	0	0
DetectStDropOut_A	6669080	0	0	0
DetectedOut_A	6669080	51823	0	0
DetectedPulseOut_A	6669080	41	0	0
DisabledIdleSt_A	6669080	5801336	0	0
DisabledNoDetection_A	6669080	5803666	0	0
EnterDebounceSt_A	6669080	42	0	0
EnterDetectSt_A	6669080	41	0	0
EnterStableSt_A	6669080	41	0	0
PulseIsPulse_A	6669080	41	0	0
StayInStableSt	6669080	51763	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	6066	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	83	0	0
T13	777	2	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	2	0	0
T44	0	4	0	0
T45	503	0	0	0
T48	0	2	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T100	0	4	0	0
T118	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T176	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	32018	0	0
T13	777	35	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	51	0	0
T44	0	122	0	0
T45	503	0	0	0
T48	0	48	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	33	0	0
T100	0	174	0	0
T118	0	40	0	0
T149	0	39	0	0
T150	0	41	0	0
T176	0	162	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021255	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	51823	0	0
T13	777	39	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	41	0	0
T44	0	72	0	0
T45	503	0	0	0
T48	0	41	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	99	0	0
T100	0	163	0	0
T118	0	167	0	0
T149	0	113	0	0
T150	0	41	0	0
T176	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	41	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	503	0	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T100	0	2	0	0
T118	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5801336	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5803666	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	42	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	503	0	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T100	0	2	0	0
T118	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	41	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	503	0	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T100	0	2	0	0
T118	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	41	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	503	0	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T100	0	2	0	0
T118	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	41	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	503	0	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T100	0	2	0	0
T118	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T176	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	51763	0	0
T13	777	38	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T43	0	39	0	0
T44	0	70	0	0
T45	503	0	0	0
T48	0	40	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	97	0	0
T100	0	160	0	0
T118	0	165	0	0
T149	0	111	0	0
T150	0	39	0	0
T176	0	79	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6066	0	0
T1	11087	38	0	0
T2	29615	10	0	0
T3	687	0	0	0
T7	21017	7	0	0
T14	433	4	0	0
T15	8200	28	0	0
T16	12100	11	0	0
T17	496	9	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	0	6	0	0
T31	0	3	0	0
T32	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	20	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T44	0	2	0	0
T45	503	0	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T96	0	1	0	0
T100	0	1	0	0
T147	0	1	0	0
T172	0	1	0	0
T176	0	2	0	0
T221	0	1	0	0
T222	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T43,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T45,T43,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T43,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T45,T43,T41
1	0	Covered	T4,T6,T1
1	1	Covered	T45,T43,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T43,T41
0	1	Covered	T46,T202,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T43,T41
0	1	Covered	T43,T41,T42
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T43,T41
1	-	Covered	T43,T41,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T45,T43,T41
DetectSt	168	Covered	T45,T43,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T45,T43,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T43,T41
DebounceSt->IdleSt	163	Covered	T71,T223,T222
DetectSt->IdleSt	186	Covered	T46,T202,T171
DetectSt->StableSt	191	Covered	T45,T43,T41
IdleSt->DebounceSt	148	Covered	T45,T43,T41
StableSt->IdleSt	206	Covered	T43,T41,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T43,T41
0	1	Covered	T45,T43,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T43,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T43,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T43,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T223,T222,T224
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T43,T41
DetectSt	-	-	-	-	1	-	-	Covered	T46,T202,T171
DetectSt	-	-	-	-	0	1	-	Covered	T45,T43,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T45,T43,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	147	0	0
CntIncr_A	6669080	66992	0	0
CntNoWrap_A	6669080	6021191	0	0
DetectStDropOut_A	6669080	3	0	0
DetectedOut_A	6669080	26018	0	0
DetectedPulseOut_A	6669080	68	0	0
DisabledIdleSt_A	6669080	5824896	0	0
DisabledNoDetection_A	6669080	5827224	0	0
EnterDebounceSt_A	6669080	77	0	0
EnterDetectSt_A	6669080	71	0	0
EnterStableSt_A	6669080	68	0	0
PulseIsPulse_A	6669080	68	0	0
StayInStableSt	6669080	25923	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	147	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	4	0	0
T42	0	4	0	0
T43	0	6	0	0
T45	503	2	0	0
T46	0	2	0	0
T48	0	4	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T79	0	2	0	0
T85	0	4	0	0
T100	0	4	0	0
T149	0	2	0	0
T214	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	66992	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	146	0	0
T42	0	74	0	0
T43	0	153	0	0
T45	503	23	0	0
T46	0	51	0	0
T48	0	96	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T71	0	18	0	0
T76	522	0	0	0
T79	0	97	0	0
T100	0	116	0	0
T149	0	39	0	0
T214	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021191	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	3	0	0
T46	17300	1	0	0
T47	749	0	0	0
T73	495	0	0	0
T149	685	0	0	0
T171	0	1	0	0
T200	425	0	0	0
T202	0	1	0	0
T215	501	0	0	0
T216	426	0	0	0
T217	425	0	0	0
T218	402	0	0	0
T219	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	26018	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	398	0	0
T42	0	80	0	0
T43	0	78	0	0
T45	503	70	0	0
T48	0	293	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T79	0	43	0	0
T85	0	255	0	0
T100	0	128	0	0
T149	0	41	0	0
T194	0	40	0	0
T214	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	68	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	3	0	0
T45	503	1	0	0
T48	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T79	0	1	0	0
T85	0	2	0	0
T100	0	2	0	0
T149	0	1	0	0
T194	0	1	0	0
T214	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5824896	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5827224	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	77	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	3	0	0
T45	503	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T71	0	1	0	0
T76	522	0	0	0
T79	0	1	0	0
T100	0	2	0	0
T149	0	1	0	0
T214	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	71	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	3	0	0
T45	503	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T79	0	1	0	0
T85	0	2	0	0
T100	0	2	0	0
T149	0	1	0	0
T214	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	68	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	3	0	0
T45	503	1	0	0
T48	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T79	0	1	0	0
T85	0	2	0	0
T100	0	2	0	0
T149	0	1	0	0
T194	0	1	0	0
T214	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	68	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	3	0	0
T45	503	1	0	0
T48	0	2	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T79	0	1	0	0
T85	0	2	0	0
T100	0	2	0	0
T149	0	1	0	0
T194	0	1	0	0
T214	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	25923	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	395	0	0
T42	0	77	0	0
T43	0	74	0	0
T45	503	68	0	0
T48	0	290	0	0
T49	10387	0	0	0
T51	669	0	0	0
T52	606	0	0	0
T64	1350	0	0	0
T76	522	0	0	0
T79	0	41	0	0
T85	0	253	0	0
T100	0	125	0	0
T149	0	40	0	0
T194	0	38	0	0
T214	406	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	39	0	0
T37	19642	0	0	0
T41	8850	1	0	0
T42	0	1	0	0
T43	897	2	0	0
T44	1037	0	0	0
T48	0	1	0	0
T54	8521	0	0	0
T65	1614	0	0	0
T69	495	0	0	0
T85	0	2	0	0
T100	0	1	0	0
T123	0	1	0	0
T149	0	1	0	0
T153	421	0	0	0
T154	978	0	0	0
T158	0	1	0	0
T159	0	1	0	0
T174	409	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T45
1	0	Covered	T6,T1,T2
1	1	Covered	T13,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T41,T42
0	1	Covered	T13,T41,T42
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T41,T42
1	-	Covered	T13,T41,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T41,T42
DetectSt	168	Covered	T13,T41,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T41,T42
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T13,T41,T42
IdleSt->DebounceSt	148	Covered	T13,T41,T42
StableSt->IdleSt	206	Covered	T13,T41,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T41,T42
0	1	Covered	T13,T41,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T41,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T41,T42
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T41,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T13,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	94	0	0
CntIncr_A	6669080	35255	0	0
CntNoWrap_A	6669080	6021244	0	0
DetectStDropOut_A	6669080	0	0	0
DetectedOut_A	6669080	2824	0	0
DetectedPulseOut_A	6669080	47	0	0
DisabledIdleSt_A	6669080	5958649	0	0
DisabledNoDetection_A	6669080	5960978	0	0
EnterDebounceSt_A	6669080	47	0	0
EnterDetectSt_A	6669080	47	0	0
EnterStableSt_A	6669080	47	0	0
PulseIsPulse_A	6669080	47	0	0
StayInStableSt	6669080	2753	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	6746	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	94	0	0
T13	777	2	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	503	0	0	0
T46	0	8	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	4	0	0
T100	0	4	0	0
T118	0	4	0	0
T123	0	2	0	0
T150	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	35255	0	0
T13	777	35	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	73	0	0
T42	0	37	0	0
T45	503	0	0	0
T46	0	164	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	48	0	0
T100	0	145	0	0
T118	0	80	0	0
T123	0	19	0	0
T150	0	41	0	0
T175	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021244	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2824	0	0
T13	777	133	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	46	0	0
T42	0	6	0	0
T45	503	0	0	0
T46	0	116	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	103	0	0
T100	0	185	0	0
T118	0	66	0	0
T123	0	63	0	0
T150	0	86	0	0
T175	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	503	0	0	0
T46	0	4	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T118	0	2	0	0
T123	0	1	0	0
T150	0	1	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5958649	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5960978	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	503	0	0	0
T46	0	4	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T118	0	2	0	0
T123	0	1	0	0
T150	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	503	0	0	0
T46	0	4	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T118	0	2	0	0
T123	0	1	0	0
T150	0	1	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	503	0	0	0
T46	0	4	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T118	0	2	0	0
T123	0	1	0	0
T150	0	1	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	503	0	0	0
T46	0	4	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T100	0	2	0	0
T118	0	2	0	0
T123	0	1	0	0
T150	0	1	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2753	0	0
T13	777	132	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	45	0	0
T42	0	5	0	0
T45	503	0	0	0
T46	0	110	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	99	0	0
T100	0	183	0	0
T118	0	63	0	0
T123	0	61	0	0
T150	0	84	0	0
T175	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6746	0	0
T1	11087	31	0	0
T2	29615	11	0	0
T3	687	2	0	0
T6	606	3	0	0
T7	21017	10	0	0
T14	433	4	0	0
T15	8200	29	0	0
T16	12100	15	0	0
T17	496	11	0	0
T18	540	0	0	0
T30	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	21	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	503	0	0	0
T46	0	2	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T91	0	1	0	0
T100	0	2	0	0
T118	0	1	0	0
T155	0	1	0	0
T175	0	1	0	0
T225	0	1	0	0