Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T12
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T12
1	0	Covered	T1,T15,T12
1	1	Covered	T1,T15,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T12
0	1	Covered	T98,T101,T104
1	0	Covered	T98,T226,T101

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T12
0	1	Covered	T1,T15,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T12
1	-	Covered	T1,T15,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T12
DetectSt	168	Covered	T1,T15,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T15,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T12
DebounceSt->IdleSt	163	Covered	T111,T60,T227
DetectSt->IdleSt	186	Covered	T98,T226,T101
DetectSt->StableSt	191	Covered	T1,T15,T12
IdleSt->DebounceSt	148	Covered	T1,T15,T12
StableSt->IdleSt	206	Covered	T1,T15,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T12
0	1	Covered	T1,T15,T12
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T15,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T111,T60,T227
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T12
DetectSt	-	-	-	-	1	-	-	Covered	T98,T226,T101
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T15,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	3065	0	0
CntIncr_A	6669080	102349	0	0
CntNoWrap_A	6669080	6018273	0	0
DetectStDropOut_A	6669080	419	0	0
DetectedOut_A	6669080	80979	0	0
DetectedPulseOut_A	6669080	925	0	0
DisabledIdleSt_A	6669080	5572970	0	0
DisabledNoDetection_A	6669080	5575119	0	0
EnterDebounceSt_A	6669080	1546	0	0
EnterDetectSt_A	6669080	1521	0	0
EnterStableSt_A	6669080	925	0	0
PulseIsPulse_A	6669080	925	0	0
StayInStableSt	6669080	79904	0	0
gen_high_event_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	775	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	3065	0	0
T1	11087	62	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	46	0	0
T14	433	0	0	0
T15	8200	42	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	30	0	0
T39	0	30	0	0
T40	0	12	0	0
T49	0	52	0	0
T54	0	60	0	0
T81	0	42	0	0
T82	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	102349	0	0
T1	11087	2325	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	1058	0	0
T14	433	0	0	0
T15	8200	1197	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1170	0	0
T39	0	1350	0	0
T40	0	348	0	0
T49	0	1612	0	0
T54	0	1260	0	0
T81	0	1869	0	0
T82	0	680	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6018273	0	0
T1	11087	10617	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7757	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	419	0	0
T97	285314	0	0	0
T98	20794	5	0	0
T101	0	18	0	0
T104	0	5	0	0
T105	0	12	0	0
T106	0	28	0	0
T107	0	12	0	0
T108	0	22	0	0
T109	0	14	0	0
T111	0	18	0	0
T123	696295	0	0	0
T158	2297	0	0	0
T159	654	0	0	0
T176	1089	0	0	0
T226	30685	0	0	0
T228	0	26	0	0
T229	445	0	0	0
T230	41055	0	0	0
T231	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	80979	0	0
T1	11087	2269	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	1754	0	0
T14	433	0	0	0
T15	8200	638	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1247	0	0
T39	0	1116	0	0
T40	0	146	0	0
T49	0	3141	0	0
T54	0	663	0	0
T81	0	1752	0	0
T82	0	760	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	925	0	0
T1	11087	31	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	23	0	0
T14	433	0	0	0
T15	8200	21	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	15	0	0
T39	0	15	0	0
T40	0	6	0	0
T49	0	26	0	0
T54	0	30	0	0
T81	0	21	0	0
T82	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5572970	0	0
T1	11087	4056	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	3273	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5575119	0	0
T1	11087	4056	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	3273	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1546	0	0
T1	11087	31	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	23	0	0
T14	433	0	0	0
T15	8200	21	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	15	0	0
T39	0	15	0	0
T40	0	6	0	0
T49	0	26	0	0
T54	0	30	0	0
T81	0	21	0	0
T82	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1521	0	0
T1	11087	31	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	23	0	0
T14	433	0	0	0
T15	8200	21	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	15	0	0
T39	0	15	0	0
T40	0	6	0	0
T49	0	26	0	0
T54	0	30	0	0
T81	0	21	0	0
T82	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	925	0	0
T1	11087	31	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	23	0	0
T14	433	0	0	0
T15	8200	21	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	15	0	0
T39	0	15	0	0
T40	0	6	0	0
T49	0	26	0	0
T54	0	30	0	0
T81	0	21	0	0
T82	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	925	0	0
T1	11087	31	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	23	0	0
T14	433	0	0	0
T15	8200	21	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	15	0	0
T39	0	15	0	0
T40	0	6	0	0
T49	0	26	0	0
T54	0	30	0	0
T81	0	21	0	0
T82	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	79904	0	0
T1	11087	2237	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	1727	0	0
T14	433	0	0	0
T15	8200	617	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1230	0	0
T39	0	1095	0	0
T40	0	140	0	0
T49	0	3115	0	0
T54	0	632	0	0
T81	0	1728	0	0
T82	0	750	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	775	0	0
T1	11087	30	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	19	0	0
T14	433	0	0	0
T15	8200	21	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	13	0	0
T39	0	9	0	0
T40	0	6	0	0
T49	0	26	0	0
T54	0	29	0	0
T81	0	18	0	0
T82	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T15
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T15
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T15
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T7,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T16
0	1	Covered	T16,T71,T97
1	0	Covered	T60,T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T11
1	-	Covered	T1,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T16
DetectSt	168	Covered	T1,T7,T16
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T16
DebounceSt->IdleSt	163	Covered	T1,T11,T38
DetectSt->IdleSt	186	Covered	T16,T71,T46
DetectSt->StableSt	191	Covered	T1,T7,T11
IdleSt->DebounceSt	148	Covered	T1,T7,T16
StableSt->IdleSt	206	Covered	T1,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T16
0	1	Covered	T1,T7,T16
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T16
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T16
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T11,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T71,T97
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T16
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	1069	0	0
CntIncr_A	6669080	54701	0	0
CntNoWrap_A	6669080	6020269	0	0
DetectStDropOut_A	6669080	77	0	0
DetectedOut_A	6669080	15328	0	0
DetectedPulseOut_A	6669080	410	0	0
DisabledIdleSt_A	6669080	5613187	0	0
DisabledNoDetection_A	6669080	5614790	0	0
EnterDebounceSt_A	6669080	579	0	0
EnterDetectSt_A	6669080	492	0	0
EnterStableSt_A	6669080	410	0	0
PulseIsPulse_A	6669080	410	0	0
StayInStableSt	6669080	14890	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	379	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1069	0	0
T1	11087	4	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	14	0	0
T11	0	9	0	0
T12	0	6	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	22	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	2	0	0
T38	0	12	0	0
T41	0	3	0	0
T49	0	6	0	0
T54	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	54701	0	0
T1	11087	159	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	980	0	0
T11	0	685	0	0
T12	0	207	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	1506	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	87	0	0
T38	0	540	0	0
T41	0	45	0	0
T49	0	192	0	0
T54	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6020269	0	0
T1	11087	10675	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20545	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11656	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	77	0	0
T16	12100	11	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T32	522	0	0	0
T33	757	0	0	0
T62	870	0	0	0
T63	822	0	0	0
T71	0	3	0	0
T97	0	1	0	0
T102	0	2	0	0
T103	0	9	0	0
T110	0	2	0	0
T112	0	5	0	0
T113	0	1	0	0
T114	0	5	0	0
T115	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	15328	0	0
T1	11087	55	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	161	0	0
T11	0	22	0	0
T12	0	110	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	53	0	0
T38	0	112	0	0
T41	0	3	0	0
T42	0	3	0	0
T49	0	236	0	0
T54	0	77	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	410	0	0
T1	11087	1	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	7	0	0
T11	0	4	0	0
T12	0	3	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1	0	0
T38	0	5	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	0	3	0	0
T54	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5613187	0	0
T1	11087	8411	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	16118	0	0
T14	433	32	0	0
T15	8200	7161	0	0
T16	12100	8058	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5614790	0	0
T1	11087	8412	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	16118	0	0
T14	433	33	0	0
T15	8200	7162	0	0
T16	12100	8058	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	579	0	0
T1	11087	3	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	7	0	0
T11	0	5	0	0
T12	0	3	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	11	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1	0	0
T38	0	7	0	0
T41	0	2	0	0
T49	0	3	0	0
T54	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	492	0	0
T1	11087	1	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	7	0	0
T11	0	4	0	0
T12	0	3	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	11	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1	0	0
T38	0	5	0	0
T41	0	1	0	0
T49	0	3	0	0
T54	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	410	0	0
T1	11087	1	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	7	0	0
T11	0	4	0	0
T12	0	3	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1	0	0
T38	0	5	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	0	3	0	0
T54	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	410	0	0
T1	11087	1	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	7	0	0
T11	0	4	0	0
T12	0	3	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1	0	0
T38	0	5	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	0	3	0	0
T54	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	14890	0	0
T1	11087	54	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	154	0	0
T11	0	18	0	0
T12	0	107	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	51	0	0
T38	0	107	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	0	233	0	0
T54	0	76	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	379	0	0
T1	11087	1	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	7	0	0
T11	0	4	0	0
T12	0	3	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	5	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T54	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T12
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T12
1	0	Covered	T1,T15,T12
1	1	Covered	T1,T15,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T12
0	1	Covered	T40,T104,T105
1	0	Covered	T49,T40,T232

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T12
0	1	Covered	T1,T15,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T12
1	-	Covered	T1,T15,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T12
DetectSt	168	Covered	T1,T15,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T15,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T12
DebounceSt->IdleSt	163	Covered	T111,T60,T227
DetectSt->IdleSt	186	Covered	T49,T40,T104
DetectSt->StableSt	191	Covered	T1,T15,T12
IdleSt->DebounceSt	148	Covered	T1,T15,T12
StableSt->IdleSt	206	Covered	T1,T15,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T12
0	1	Covered	T1,T15,T12
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T15,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T111,T60,T227
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T12
DetectSt	-	-	-	-	1	-	-	Covered	T49,T40,T104
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T15,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	2594	0	0
CntIncr_A	6669080	83046	0	0
CntNoWrap_A	6669080	6018744	0	0
DetectStDropOut_A	6669080	325	0	0
DetectedOut_A	6669080	67425	0	0
DetectedPulseOut_A	6669080	749	0	0
DisabledIdleSt_A	6669080	5580802	0	0
DisabledNoDetection_A	6669080	5582984	0	0
EnterDebounceSt_A	6669080	1302	0	0
EnterDetectSt_A	6669080	1292	0	0
EnterStableSt_A	6669080	749	0	0
PulseIsPulse_A	6669080	749	0	0
StayInStableSt	6669080	66560	0	0
gen_high_event_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	633	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2594	0	0
T1	11087	32	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	26	0	0
T14	433	0	0	0
T15	8200	52	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	60	0	0
T39	0	30	0	0
T40	0	8	0	0
T49	0	22	0	0
T54	0	46	0	0
T81	0	18	0	0
T82	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	83046	0	0
T1	11087	1040	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	741	0	0
T14	433	0	0	0
T15	8200	1664	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	2160	0	0
T39	0	1305	0	0
T40	0	320	0	0
T49	0	1359	0	0
T54	0	874	0	0
T81	0	765	0	0
T82	0	1403	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6018744	0	0
T1	11087	10647	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7747	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	325	0	0
T40	10325	1	0	0
T85	11672	0	0	0
T104	0	14	0	0
T105	0	12	0	0
T106	0	5	0	0
T107	0	11	0	0
T108	0	11	0	0
T109	0	23	0	0
T111	0	5	0	0
T150	3277	0	0	0
T228	0	23	0	0
T233	0	4	0	0
T234	402	0	0	0
T235	15924	0	0	0
T236	438	0	0	0
T237	444	0	0	0
T238	16649	0	0	0
T239	434	0	0	0
T240	474	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	67425	0	0
T1	11087	819	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	309	0	0
T14	433	0	0	0
T15	8200	608	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	2700	0	0
T39	0	1161	0	0
T54	0	1618	0	0
T81	0	1290	0	0
T82	0	2795	0	0
T88	0	4414	0	0
T98	0	1297	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	749	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	13	0	0
T14	433	0	0	0
T15	8200	26	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	30	0	0
T39	0	15	0	0
T54	0	23	0	0
T81	0	9	0	0
T82	0	23	0	0
T88	0	5	0	0
T98	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5580802	0	0
T1	11087	5384	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	3255	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5582984	0	0
T1	11087	5384	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	3255	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1302	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	13	0	0
T14	433	0	0	0
T15	8200	26	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	30	0	0
T39	0	15	0	0
T40	0	4	0	0
T49	0	11	0	0
T54	0	23	0	0
T81	0	9	0	0
T82	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1292	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	13	0	0
T14	433	0	0	0
T15	8200	26	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	30	0	0
T39	0	15	0	0
T40	0	4	0	0
T49	0	11	0	0
T54	0	23	0	0
T81	0	9	0	0
T82	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	749	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	13	0	0
T14	433	0	0	0
T15	8200	26	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	30	0	0
T39	0	15	0	0
T54	0	23	0	0
T81	0	9	0	0
T82	0	23	0	0
T88	0	5	0	0
T98	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	749	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	13	0	0
T14	433	0	0	0
T15	8200	26	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	30	0	0
T39	0	15	0	0
T54	0	23	0	0
T81	0	9	0	0
T82	0	23	0	0
T88	0	5	0	0
T98	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	66560	0	0
T1	11087	802	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	295	0	0
T14	433	0	0	0
T15	8200	582	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	2666	0	0
T39	0	1140	0	0
T54	0	1594	0	0
T81	0	1279	0	0
T82	0	2767	0	0
T88	0	4409	0	0
T98	0	1280	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	633	0	0
T1	11087	15	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	12	0	0
T14	433	0	0	0
T15	8200	26	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	26	0	0
T39	0	9	0	0
T54	0	22	0	0
T81	0	7	0	0
T82	0	18	0	0
T88	0	5	0	0
T98	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T7,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T2,T7,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T16
0	1	Covered	T189,T241,T238
1	0	Covered	T60,T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T16
0	1	Covered	T2,T7,T16
1	0	Covered	T60,T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T16
1	-	Covered	T2,T7,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T16
DetectSt	168	Covered	T2,T7,T16
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T7,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T16
DebounceSt->IdleSt	163	Covered	T2,T11,T38
DetectSt->IdleSt	186	Covered	T189,T46,T241
DetectSt->StableSt	191	Covered	T2,T7,T16
IdleSt->DebounceSt	148	Covered	T2,T7,T16
StableSt->IdleSt	206	Covered	T2,T7,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T16
0	1	Covered	T2,T7,T16
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T16
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T16
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T11,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T16
DetectSt	-	-	-	-	1	-	-	Covered	T189,T241,T238
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T16
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T16
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T16
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	939	0	0
CntIncr_A	6669080	50250	0	0
CntNoWrap_A	6669080	6020399	0	0
DetectStDropOut_A	6669080	72	0	0
DetectedOut_A	6669080	15737	0	0
DetectedPulseOut_A	6669080	369	0	0
DisabledIdleSt_A	6669080	5625509	0	0
DisabledNoDetection_A	6669080	5627199	0	0
EnterDebounceSt_A	6669080	495	0	0
EnterDetectSt_A	6669080	446	0	0
EnterStableSt_A	6669080	369	0	0
PulseIsPulse_A	6669080	369	0	0
StayInStableSt	6669080	15339	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	334	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	939	0	0
T2	29615	21	0	0
T3	687	0	0	0
T7	21017	6	0	0
T11	0	19	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	6	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	6	0	0
T38	0	13	0	0
T54	0	4	0	0
T62	870	0	0	0
T71	0	6	0	0
T189	0	4	0	0
T197	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	50250	0	0
T2	29615	1096	0	0
T3	687	0	0	0
T7	21017	435	0	0
T11	0	996	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	369	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	225	0	0
T38	0	528	0	0
T54	0	112	0	0
T62	870	0	0	0
T71	0	159	0	0
T189	0	302	0	0
T197	0	1218	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6020399	0	0
T1	11087	10679	0	0
T2	29615	29124	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20553	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11672	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	72	0	0
T46	17300	0	0	0
T81	23609	0	0	0
T100	44878	0	0	0
T102	0	1	0	0
T110	0	10	0	0
T112	0	13	0	0
T189	10831	2	0	0
T190	515	0	0	0
T195	654	0	0	0
T196	423	0	0	0
T197	31794	0	0	0
T198	746	0	0	0
T199	19819	0	0	0
T238	0	2	0	0
T241	0	2	0	0
T242	0	5	0	0
T243	0	4	0	0
T244	0	1	0	0
T245	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	15737	0	0
T2	29615	955	0	0
T3	687	0	0	0
T7	21017	53	0	0
T11	0	512	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	39	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	200	0	0
T38	0	172	0	0
T54	0	117	0	0
T62	870	0	0	0
T71	0	29	0	0
T81	0	175	0	0
T197	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	369	0	0
T2	29615	10	0	0
T3	687	0	0	0
T7	21017	3	0	0
T11	0	9	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	6	0	0
T54	0	2	0	0
T62	870	0	0	0
T71	0	3	0	0
T81	0	2	0	0
T197	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5625509	0	0
T1	11087	9861	0	0
T2	29615	24174	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	16118	0	0
T14	433	32	0	0
T15	8200	7190	0	0
T16	12100	8058	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5627199	0	0
T1	11087	9862	0	0
T2	29615	24174	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	16118	0	0
T14	433	33	0	0
T15	8200	7191	0	0
T16	12100	8058	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	495	0	0
T2	29615	11	0	0
T3	687	0	0	0
T7	21017	3	0	0
T11	0	10	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	7	0	0
T54	0	2	0	0
T62	870	0	0	0
T71	0	3	0	0
T189	0	2	0	0
T197	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	446	0	0
T2	29615	10	0	0
T3	687	0	0	0
T7	21017	3	0	0
T11	0	9	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	6	0	0
T54	0	2	0	0
T62	870	0	0	0
T71	0	3	0	0
T189	0	2	0	0
T197	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	369	0	0
T2	29615	10	0	0
T3	687	0	0	0
T7	21017	3	0	0
T11	0	9	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	6	0	0
T54	0	2	0	0
T62	870	0	0	0
T71	0	3	0	0
T81	0	2	0	0
T197	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	369	0	0
T2	29615	10	0	0
T3	687	0	0	0
T7	21017	3	0	0
T11	0	9	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	6	0	0
T54	0	2	0	0
T62	870	0	0	0
T71	0	3	0	0
T81	0	2	0	0
T197	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	15339	0	0
T2	29615	945	0	0
T3	687	0	0	0
T7	21017	50	0	0
T11	0	503	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	36	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	197	0	0
T38	0	166	0	0
T54	0	115	0	0
T62	870	0	0	0
T71	0	26	0	0
T81	0	171	0	0
T197	0	30	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	334	0	0
T2	29615	10	0	0
T3	687	0	0	0
T7	21017	3	0	0
T11	0	9	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	5	0	0
T54	0	2	0	0
T62	870	0	0	0
T71	0	3	0	0
T197	0	7	0	0
T246	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T12
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T12
1	0	Covered	T1,T15,T12
1	1	Covered	T1,T15,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T12
0	1	Covered	T12,T88,T104
1	0	Covered	T12,T88,T247

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T49
0	1	Covered	T1,T15,T49
1	0	Covered	T88,T248

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T49
1	-	Covered	T1,T15,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T12
DetectSt	168	Covered	T1,T15,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T15,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T12
DebounceSt->IdleSt	163	Covered	T111,T60,T227
DetectSt->IdleSt	186	Covered	T12,T88,T104
DetectSt->StableSt	191	Covered	T1,T15,T49
IdleSt->DebounceSt	148	Covered	T1,T15,T12
StableSt->IdleSt	206	Covered	T1,T15,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T12
0	1	Covered	T1,T15,T12
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T15,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T111,T60,T227
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T12
DetectSt	-	-	-	-	1	-	-	Covered	T12,T88,T104
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T49
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T15,T49
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	2809	0	0
CntIncr_A	6669080	86607	0	0
CntNoWrap_A	6669080	6018529	0	0
DetectStDropOut_A	6669080	369	0	0
DetectedOut_A	6669080	82971	0	0
DetectedPulseOut_A	6669080	901	0	0
DisabledIdleSt_A	6669080	5569828	0	0
DisabledNoDetection_A	6669080	5571997	0	0
EnterDebounceSt_A	6669080	1414	0	0
EnterDetectSt_A	6669080	1396	0	0
EnterStableSt_A	6669080	901	0	0
PulseIsPulse_A	6669080	901	0	0
StayInStableSt	6669080	81941	0	0
gen_high_event_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	764	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2809	0	0
T1	11087	10	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	50	0	0
T14	433	0	0	0
T15	8200	50	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	52	0	0
T39	0	40	0	0
T40	0	30	0	0
T49	0	20	0	0
T54	0	26	0	0
T81	0	18	0	0
T82	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	86607	0	0
T1	11087	305	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	1544	0	0
T14	433	0	0	0
T15	8200	1525	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	2028	0	0
T39	0	1420	0	0
T40	0	1035	0	0
T49	0	880	0	0
T54	0	507	0	0
T81	0	720	0	0
T82	0	1550	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6018529	0	0
T1	11087	10669	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7749	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	369	0	0
T12	17611	3	0	0
T13	777	0	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T45	503	0	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T88	0	8	0	0
T104	0	33	0	0
T105	0	10	0	0
T106	0	17	0	0
T107	0	6	0	0
T108	0	20	0	0
T109	0	15	0	0
T111	0	6	0	0
T247	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	82971	0	0
T1	11087	469	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	1828	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	999	0	0
T39	0	2131	0	0
T40	0	1832	0	0
T49	0	376	0	0
T54	0	525	0	0
T81	0	1043	0	0
T82	0	3027	0	0
T88	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	901	0	0
T1	11087	5	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	25	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	26	0	0
T39	0	20	0	0
T40	0	15	0	0
T49	0	10	0	0
T54	0	13	0	0
T81	0	9	0	0
T82	0	25	0	0
T88	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5569828	0	0
T1	11087	5430	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	2086	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5571997	0	0
T1	11087	5430	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	2086	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1414	0	0
T1	11087	5	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	25	0	0
T14	433	0	0	0
T15	8200	25	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	26	0	0
T39	0	20	0	0
T40	0	15	0	0
T49	0	10	0	0
T54	0	13	0	0
T81	0	9	0	0
T82	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1396	0	0
T1	11087	5	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	25	0	0
T14	433	0	0	0
T15	8200	25	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	26	0	0
T39	0	20	0	0
T40	0	15	0	0
T49	0	10	0	0
T54	0	13	0	0
T81	0	9	0	0
T82	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	901	0	0
T1	11087	5	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	25	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	26	0	0
T39	0	20	0	0
T40	0	15	0	0
T49	0	10	0	0
T54	0	13	0	0
T81	0	9	0	0
T82	0	25	0	0
T88	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	901	0	0
T1	11087	5	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	25	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	26	0	0
T39	0	20	0	0
T40	0	15	0	0
T49	0	10	0	0
T54	0	13	0	0
T81	0	9	0	0
T82	0	25	0	0
T88	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	81941	0	0
T1	11087	463	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	1803	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	970	0	0
T39	0	2104	0	0
T40	0	1816	0	0
T49	0	366	0	0
T54	0	511	0	0
T81	0	1032	0	0
T82	0	2999	0	0
T98	0	114	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	764	0	0
T1	11087	4	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	25	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	23	0	0
T39	0	13	0	0
T40	0	14	0	0
T49	0	10	0	0
T54	0	12	0	0
T81	0	7	0	0
T82	0	22	0	0
T98	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T7,T197,T235
1	0	Covered	T60,T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T16
1	-	Covered	T1,T2,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T7,T38,T199
DetectSt->IdleSt	186	Covered	T7,T197,T46
DetectSt->StableSt	191	Covered	T1,T2,T16
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T38,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T197,T235
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T16
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T16
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	964	0	0
CntIncr_A	6669080	52048	0	0
CntNoWrap_A	6669080	6020374	0	0
DetectStDropOut_A	6669080	72	0	0
DetectedOut_A	6669080	17561	0	0
DetectedPulseOut_A	6669080	374	0	0
DisabledIdleSt_A	6669080	5613257	0	0
DisabledNoDetection_A	6669080	5614939	0	0
EnterDebounceSt_A	6669080	515	0	0
EnterDetectSt_A	6669080	452	0	0
EnterStableSt_A	6669080	374	0	0
PulseIsPulse_A	6669080	374	0	0
StayInStableSt	6669080	17146	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	330	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	964	0	0
T1	11087	2	0	0
T2	29615	8	0	0
T3	687	0	0	0
T7	21017	25	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	6	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	6	0	0
T38	0	15	0	0
T71	0	6	0	0
T189	0	2	0	0
T197	0	2	0	0
T199	0	15	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	52048	0	0
T1	11087	56	0	0
T2	29615	612	0	0
T3	687	0	0	0
T7	21017	2032	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	351	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	282	0	0
T38	0	676	0	0
T71	0	168	0	0
T189	0	80	0	0
T197	0	179	0	0
T199	0	1389	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6020374	0	0
T1	11087	10677	0	0
T2	29615	29137	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20534	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11672	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	72	0	0
T7	21017	12	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T33	757	0	0	0
T61	0	1	0	0
T62	870	0	0	0
T113	0	3	0	0
T197	0	1	0	0
T235	0	5	0	0
T244	0	6	0	0
T249	0	4	0	0
T250	0	3	0	0
T251	0	1	0	0
T252	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	17561	0	0
T1	11087	82	0	0
T2	29615	171	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	60	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	140	0	0
T38	0	128	0	0
T71	0	18	0	0
T81	0	156	0	0
T122	0	62	0	0
T189	0	71	0	0
T199	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	374	0	0
T1	11087	1	0	0
T2	29615	4	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	7	0	0
T71	0	3	0	0
T81	0	2	0	0
T122	0	1	0	0
T189	0	1	0	0
T199	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5613257	0	0
T1	11087	10211	0	0
T2	29615	24174	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	16118	0	0
T14	433	32	0	0
T15	8200	5968	0	0
T16	12100	8058	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5614939	0	0
T1	11087	10212	0	0
T2	29615	24174	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	16118	0	0
T14	433	33	0	0
T15	8200	5969	0	0
T16	12100	8058	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	515	0	0
T1	11087	1	0	0
T2	29615	4	0	0
T3	687	0	0	0
T7	21017	13	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	8	0	0
T71	0	3	0	0
T189	0	1	0	0
T197	0	1	0	0
T199	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	452	0	0
T1	11087	1	0	0
T2	29615	4	0	0
T3	687	0	0	0
T7	21017	12	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	7	0	0
T71	0	3	0	0
T189	0	1	0	0
T197	0	1	0	0
T199	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	374	0	0
T1	11087	1	0	0
T2	29615	4	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	7	0	0
T71	0	3	0	0
T81	0	2	0	0
T122	0	1	0	0
T189	0	1	0	0
T199	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	374	0	0
T1	11087	1	0	0
T2	29615	4	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	3	0	0
T38	0	7	0	0
T71	0	3	0	0
T81	0	2	0	0
T122	0	1	0	0
T189	0	1	0	0
T199	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	17146	0	0
T1	11087	81	0	0
T2	29615	167	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	57	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	135	0	0
T38	0	121	0	0
T71	0	15	0	0
T81	0	152	0	0
T122	0	61	0	0
T189	0	70	0	0
T199	0	29	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	330	0	0
T1	11087	1	0	0
T2	29615	4	0	0
T3	687	0	0	0
T7	21017	0	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	3	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	1	0	0
T38	0	7	0	0
T71	0	3	0	0
T82	0	5	0	0
T122	0	1	0	0
T189	0	1	0	0
T199	0	6	0	0