Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T12
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T12
1	0	Covered	T1,T15,T12
1	1	Covered	T1,T15,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T12
0	1	Covered	T40,T88,T104
1	0	Covered	T40,T88,T253

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T12
0	1	Covered	T1,T15,T12
1	0	Covered	T89,T90,T254

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T12
1	-	Covered	T1,T15,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T12
DetectSt	168	Covered	T1,T15,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T15,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T12
DebounceSt->IdleSt	163	Covered	T111,T60,T227
DetectSt->IdleSt	186	Covered	T40,T88,T104
DetectSt->StableSt	191	Covered	T1,T15,T12
IdleSt->DebounceSt	148	Covered	T1,T15,T12
StableSt->IdleSt	206	Covered	T1,T15,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T12
0	1	Covered	T1,T15,T12
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T15,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T111,T60,T227
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T12
DetectSt	-	-	-	-	1	-	-	Covered	T40,T88,T104
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T15,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	2750	0	0
CntIncr_A	6669080	88698	0	0
CntNoWrap_A	6669080	6018588	0	0
DetectStDropOut_A	6669080	369	0	0
DetectedOut_A	6669080	66536	0	0
DetectedPulseOut_A	6669080	861	0	0
DisabledIdleSt_A	6669080	5586640	0	0
DisabledNoDetection_A	6669080	5588825	0	0
EnterDebounceSt_A	6669080	1384	0	0
EnterDetectSt_A	6669080	1367	0	0
EnterStableSt_A	6669080	861	0	0
PulseIsPulse_A	6669080	861	0	0
StayInStableSt	6669080	65562	0	0
gen_high_event_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	738	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2750	0	0
T1	11087	32	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	54	0	0
T14	433	0	0	0
T15	8200	24	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	12	0	0
T39	0	48	0	0
T40	0	48	0	0
T49	0	54	0	0
T54	0	60	0	0
T81	0	54	0	0
T82	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	88698	0	0
T1	11087	1136	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	1647	0	0
T14	433	0	0	0
T15	8200	624	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	516	0	0
T39	0	2016	0	0
T40	0	1925	0	0
T49	0	2214	0	0
T54	0	1290	0	0
T81	0	2592	0	0
T82	0	528	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6018588	0	0
T1	11087	10647	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7775	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	369	0	0
T40	10325	17	0	0
T85	11672	0	0	0
T88	0	8	0	0
T104	0	8	0	0
T105	0	24	0	0
T106	0	27	0	0
T107	0	11	0	0
T108	0	17	0	0
T109	0	17	0	0
T111	0	5	0	0
T150	3277	0	0	0
T228	0	23	0	0
T234	402	0	0	0
T235	15924	0	0	0
T236	438	0	0	0
T237	444	0	0	0
T238	16649	0	0	0
T239	434	0	0	0
T240	474	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	66536	0	0
T1	11087	997	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	531	0	0
T14	433	0	0	0
T15	8200	411	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	43	0	0
T39	0	2600	0	0
T49	0	2669	0	0
T54	0	633	0	0
T81	0	2704	0	0
T82	0	603	0	0
T98	0	446	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	861	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	27	0	0
T14	433	0	0	0
T15	8200	12	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	6	0	0
T39	0	24	0	0
T49	0	27	0	0
T54	0	30	0	0
T81	0	27	0	0
T82	0	8	0	0
T98	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5586640	0	0
T1	11087	5102	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	3325	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5588825	0	0
T1	11087	5102	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	3325	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1384	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	27	0	0
T14	433	0	0	0
T15	8200	12	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	6	0	0
T39	0	24	0	0
T40	0	24	0	0
T49	0	27	0	0
T54	0	30	0	0
T81	0	27	0	0
T82	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	1367	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	27	0	0
T14	433	0	0	0
T15	8200	12	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	6	0	0
T39	0	24	0	0
T40	0	24	0	0
T49	0	27	0	0
T54	0	30	0	0
T81	0	27	0	0
T82	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	861	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	27	0	0
T14	433	0	0	0
T15	8200	12	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	6	0	0
T39	0	24	0	0
T49	0	27	0	0
T54	0	30	0	0
T81	0	27	0	0
T82	0	8	0	0
T98	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	861	0	0
T1	11087	16	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	27	0	0
T14	433	0	0	0
T15	8200	12	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	6	0	0
T39	0	24	0	0
T49	0	27	0	0
T54	0	30	0	0
T81	0	27	0	0
T82	0	8	0	0
T98	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	65562	0	0
T1	11087	980	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	502	0	0
T14	433	0	0	0
T15	8200	399	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	37	0	0
T39	0	2567	0	0
T49	0	2642	0	0
T54	0	602	0	0
T81	0	2673	0	0
T82	0	594	0	0
T98	0	431	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	738	0	0
T1	11087	15	0	0
T2	29615	0	0	0
T3	687	0	0	0
T7	21017	0	0	0
T12	0	25	0	0
T14	433	0	0	0
T15	8200	12	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T37	0	6	0	0
T39	0	15	0	0
T49	0	27	0	0
T54	0	29	0	0
T81	0	23	0	0
T82	0	7	0	0
T98	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T16,T141,T255
1	0	Covered	T60,T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T11,T12,T38
DetectSt->IdleSt	186	Covered	T16,T46,T141
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T12,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T16,T141,T255
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	756	0	0
CntIncr_A	6669080	41970	0	0
CntNoWrap_A	6669080	6020582	0	0
DetectStDropOut_A	6669080	48	0	0
DetectedOut_A	6669080	13997	0	0
DetectedPulseOut_A	6669080	303	0	0
DisabledIdleSt_A	6669080	5639170	0	0
DisabledNoDetection_A	6669080	5640896	0	0
EnterDebounceSt_A	6669080	401	0	0
EnterDetectSt_A	6669080	356	0	0
EnterStableSt_A	6669080	303	0	0
PulseIsPulse_A	6669080	303	0	0
StayInStableSt	6669080	13668	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	274	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	756	0	0
T1	11087	2	0	0
T2	29615	22	0	0
T3	687	0	0	0
T7	21017	16	0	0
T11	0	9	0	0
T12	0	5	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	4	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	3	0	0
T54	0	2	0	0
T189	0	4	0	0
T197	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	41970	0	0
T1	11087	77	0	0
T2	29615	1342	0	0
T3	687	0	0	0
T7	21017	912	0	0
T11	0	541	0	0
T12	0	161	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	272	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	156	0	0
T54	0	67	0	0
T189	0	200	0	0
T197	0	821	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6020582	0	0
T1	11087	10677	0	0
T2	29615	29123	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20543	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11674	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	48	0	0
T16	12100	2	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T32	522	0	0	0
T33	757	0	0	0
T62	870	0	0	0
T63	822	0	0	0
T110	0	6	0	0
T128	0	1	0	0
T141	0	1	0	0
T251	0	4	0	0
T255	0	4	0	0
T256	0	10	0	0
T257	0	1	0	0
T258	0	2	0	0
T259	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	13997	0	0
T1	11087	61	0	0
T2	29615	814	0	0
T3	687	0	0	0
T7	21017	387	0	0
T11	0	166	0	0
T12	0	77	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	11	0	0
T54	0	47	0	0
T189	0	102	0	0
T197	0	170	0	0
T199	0	66	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	303	0	0
T1	11087	1	0	0
T2	29615	11	0	0
T3	687	0	0	0
T7	21017	8	0	0
T11	0	4	0	0
T12	0	2	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	1	0	0
T54	0	1	0	0
T189	0	2	0	0
T197	0	5	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5639170	0	0
T1	11087	9683	0	0
T2	29615	24174	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	16118	0	0
T14	433	32	0	0
T15	8200	7383	0	0
T16	12100	8058	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5640896	0	0
T1	11087	9684	0	0
T2	29615	24174	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	16118	0	0
T14	433	33	0	0
T15	8200	7384	0	0
T16	12100	8058	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	401	0	0
T1	11087	1	0	0
T2	29615	11	0	0
T3	687	0	0	0
T7	21017	8	0	0
T11	0	5	0	0
T12	0	3	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	2	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	2	0	0
T54	0	1	0	0
T189	0	2	0	0
T197	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	356	0	0
T1	11087	1	0	0
T2	29615	11	0	0
T3	687	0	0	0
T7	21017	8	0	0
T11	0	4	0	0
T12	0	2	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	2	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	1	0	0
T54	0	1	0	0
T189	0	2	0	0
T197	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	303	0	0
T1	11087	1	0	0
T2	29615	11	0	0
T3	687	0	0	0
T7	21017	8	0	0
T11	0	4	0	0
T12	0	2	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	1	0	0
T54	0	1	0	0
T189	0	2	0	0
T197	0	5	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	303	0	0
T1	11087	1	0	0
T2	29615	11	0	0
T3	687	0	0	0
T7	21017	8	0	0
T11	0	4	0	0
T12	0	2	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	1	0	0
T54	0	1	0	0
T189	0	2	0	0
T197	0	5	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	13668	0	0
T1	11087	60	0	0
T2	29615	803	0	0
T3	687	0	0	0
T7	21017	379	0	0
T11	0	162	0	0
T12	0	75	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	10	0	0
T54	0	46	0	0
T189	0	100	0	0
T197	0	165	0	0
T199	0	65	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	274	0	0
T1	11087	1	0	0
T2	29615	11	0	0
T3	687	0	0	0
T7	21017	8	0	0
T11	0	4	0	0
T12	0	2	0	0
T14	433	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T38	0	1	0	0
T54	0	1	0	0
T189	0	2	0	0
T197	0	5	0	0
T199	0	1	0	0