Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1248619610	11081	0	0
auto_block_debounce_ctl_rd_A	1248619610	2065	0	0
auto_block_out_ctl_rd_A	1248619610	2991	0	0
com_det_ctl_0_rd_A	1248619610	3507	0	0
com_det_ctl_1_rd_A	1248619610	3658	0	0
com_det_ctl_2_rd_A	1248619610	3369	0	0
com_det_ctl_3_rd_A	1248619610	3538	0	0
com_out_ctl_0_rd_A	1248619610	4449	0	0
com_out_ctl_1_rd_A	1248619610	4264	0	0
com_out_ctl_2_rd_A	1248619610	4400	0	0
com_out_ctl_3_rd_A	1248619610	4454	0	0
com_pre_det_ctl_0_rd_A	1248619610	1553	0	0
com_pre_det_ctl_1_rd_A	1248619610	1465	0	0
com_pre_det_ctl_2_rd_A	1248619610	1393	0	0
com_pre_det_ctl_3_rd_A	1248619610	1585	0	0
com_pre_sel_ctl_0_rd_A	1248619610	4662	0	0
com_pre_sel_ctl_1_rd_A	1248619610	4675	0	0
com_pre_sel_ctl_2_rd_A	1248619610	4839	0	0
com_pre_sel_ctl_3_rd_A	1248619610	4754	0	0
com_sel_ctl_0_rd_A	1248619610	4937	0	0
com_sel_ctl_1_rd_A	1248619610	4857	0	0
com_sel_ctl_2_rd_A	1248619610	4568	0	0
com_sel_ctl_3_rd_A	1248619610	4516	0	0
ec_rst_ctl_rd_A	1248619610	2391	0	0
intr_enable_rd_A	1248619610	1916	0	0
key_intr_ctl_rd_A	1248619610	4910	0	0
key_intr_debounce_ctl_rd_A	1248619610	1405	0	0
key_invert_ctl_rd_A	1248619610	6188	0	0
pin_allowed_ctl_rd_A	1248619610	7930	0	0
pin_out_ctl_rd_A	1248619610	5528	0	0
pin_out_value_rd_A	1248619610	5529	0	0
regwen_rd_A	1248619610	1661	0	0
ulp_ac_debounce_ctl_rd_A	1248619610	1598	0	0
ulp_ctl_rd_A	1248619610	1724	0	0
ulp_lid_debounce_ctl_rd_A	1248619610	1658	0	0
ulp_pwrb_debounce_ctl_rd_A	1248619610	1602	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	11081	0	0
T37	982097	0	0	0
T41	194304	10	0	0
T42	815452	10	0	0
T46	0	20	0	0
T48	0	5	0	0
T55	967095	0	0	0
T66	55328	0	0	0
T67	126612	0	0	0
T68	0	12	0	0
T71	0	2	0	0
T85	0	10	0	0
T97	0	18	0	0
T100	0	13	0	0
T123	0	19	0	0
T281	240989	0	0	0
T282	60859	0	0	0
T283	163155	0	0	0
T284	60445	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	2065	0	0
T41	194304	0	0	0
T43	346667	0	0	0
T44	43701	0	0	0
T48	0	1	0	0
T53	343359	8	0	0
T54	408991	0	0	0
T55	0	12	0	0
T65	21335	0	0	0
T68	0	8	0	0
T69	59561	0	0	0
T150	0	16	0	0
T153	204633	0	0	0
T154	83156	0	0	0
T163	0	23	0	0
T174	36845	0	0	0
T285	0	9	0	0
T286	0	15	0	0
T287	0	9	0	0
T288	0	8	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	2991	0	0
T41	194304	0	0	0
T43	346667	0	0	0
T44	43701	0	0	0
T53	343359	8	0	0
T54	408991	0	0	0
T55	0	18	0	0
T65	21335	0	0	0
T68	0	17	0	0
T69	59561	0	0	0
T150	0	12	0	0
T153	204633	0	0	0
T154	83156	0	0	0
T157	0	12	0	0
T163	0	34	0	0
T174	36845	0	0	0
T285	0	13	0	0
T286	0	15	0	0
T287	0	8	0	0
T288	0	5	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	3507	0	0
T11	0	27	0	0
T12	0	47	0	0
T15	451015	33	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	56	0	0
T48	0	8	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	3	0	0
T189	0	47	0	0
T197	0	81	0	0
T235	0	59	0	0
T246	0	39	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	3658	0	0
T11	0	40	0	0
T12	0	46	0	0
T15	451015	8	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	50	0	0
T48	0	2	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	12	0	0
T189	0	40	0	0
T197	0	84	0	0
T235	0	85	0	0
T246	0	33	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	3369	0	0
T11	0	54	0	0
T12	0	41	0	0
T15	451015	28	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	47	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	5	0	0
T98	0	29	0	0
T189	0	37	0	0
T197	0	60	0	0
T235	0	63	0	0
T246	0	32	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	3538	0	0
T11	0	39	0	0
T12	0	75	0	0
T15	451015	18	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	37	0	0
T48	0	10	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	3	0	0
T189	0	17	0	0
T197	0	53	0	0
T235	0	64	0	0
T246	0	39	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4449	0	0
T11	0	60	0	0
T12	0	55	0	0
T15	451015	20	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	59	0	0
T48	0	10	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	5	0	0
T189	0	40	0	0
T197	0	75	0	0
T235	0	71	0	0
T246	0	39	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4264	0	0
T11	0	44	0	0
T12	0	61	0	0
T15	451015	20	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	47	0	0
T48	0	13	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	9	0	0
T189	0	41	0	0
T197	0	69	0	0
T235	0	64	0	0
T246	0	41	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4400	0	0
T11	0	22	0	0
T12	0	56	0	0
T15	451015	28	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	52	0	0
T48	0	13	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	8	0	0
T189	0	37	0	0
T197	0	81	0	0
T235	0	45	0	0
T246	0	39	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4454	0	0
T11	0	25	0	0
T12	0	65	0	0
T15	451015	17	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	37	0	0
T48	0	1	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	3	0	0
T189	0	49	0	0
T197	0	82	0	0
T235	0	96	0	0
T246	0	56	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1553	0	0
T48	287302	23	0	0
T68	489061	6	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	22	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T145	0	20	0	0
T157	0	13	0	0
T163	0	16	0	0
T209	0	20	0	0
T289	0	28	0	0
T290	0	2	0	0
T291	0	17	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1465	0	0
T48	287302	7	0	0
T68	489061	0	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	23	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T145	0	18	0	0
T157	0	23	0	0
T163	0	9	0	0
T180	0	12	0	0
T209	0	9	0	0
T289	0	23	0	0
T291	0	6	0	0
T292	0	16	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1393	0	0
T48	287302	5	0	0
T68	489061	0	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	29	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T145	0	15	0	0
T157	0	13	0	0
T163	0	20	0	0
T180	0	9	0	0
T209	0	17	0	0
T289	0	20	0	0
T290	0	9	0	0
T291	0	5	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1585	0	0
T48	287302	7	0	0
T68	489061	5	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	14	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T145	0	19	0	0
T157	0	2	0	0
T163	0	9	0	0
T209	0	8	0	0
T289	0	33	0	0
T290	0	17	0	0
T291	0	15	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4662	0	0
T11	0	32	0	0
T12	0	72	0	0
T15	451015	30	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	58	0	0
T48	0	18	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T98	0	44	0	0
T189	0	56	0	0
T197	0	49	0	0
T235	0	81	0	0
T246	0	30	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4675	0	0
T11	0	66	0	0
T12	0	59	0	0
T15	451015	16	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	63	0	0
T48	0	5	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	3	0	0
T189	0	70	0	0
T197	0	76	0	0
T235	0	75	0	0
T246	0	58	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4839	0	0
T11	0	42	0	0
T12	0	51	0	0
T15	451015	17	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	58	0	0
T48	0	15	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	5	0	0
T189	0	65	0	0
T197	0	67	0	0
T235	0	74	0	0
T246	0	47	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4754	0	0
T11	0	43	0	0
T12	0	41	0	0
T15	451015	24	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	66	0	0
T48	0	10	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	2	0	0
T189	0	52	0	0
T197	0	88	0	0
T235	0	85	0	0
T246	0	40	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4937	0	0
T11	0	62	0	0
T12	0	43	0	0
T15	451015	29	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	62	0	0
T48	0	17	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	3	0	0
T189	0	60	0	0
T197	0	75	0	0
T235	0	73	0	0
T246	0	45	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4857	0	0
T11	0	41	0	0
T12	0	63	0	0
T15	451015	24	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	63	0	0
T48	0	21	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T98	0	44	0	0
T189	0	28	0	0
T197	0	78	0	0
T235	0	58	0	0
T246	0	40	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4568	0	0
T11	0	25	0	0
T12	0	73	0	0
T15	451015	22	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	47	0	0
T48	0	6	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T98	0	47	0	0
T189	0	33	0	0
T197	0	63	0	0
T235	0	57	0	0
T246	0	60	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4516	0	0
T11	0	42	0	0
T12	0	49	0	0
T15	451015	15	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T33	355857	0	0	0
T37	0	44	0	0
T48	0	2	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	2	0	0
T189	0	39	0	0
T197	0	54	0	0
T235	0	49	0	0
T246	0	48	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	2391	0	0
T8	243116	0	0	0
T9	259944	0	0	0
T11	0	23	0	0
T12	0	24	0	0
T18	216382	2	0	0
T19	65032	0	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T32	250605	0	0	0
T33	355857	0	0	0
T37	0	13	0	0
T48	0	8	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	9	0	0
T189	0	4	0	0
T197	0	51	0	0
T198	0	1	0	0
T246	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1916	0	0
T48	287302	21	0	0
T68	489061	0	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	63	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T145	0	4	0	0
T157	0	13	0	0
T163	0	17	0	0
T209	0	11	0	0
T245	0	6	0	0
T289	0	31	0	0
T290	0	32	0	0
T291	0	30	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	4910	0	0
T37	982097	0	0	0
T41	194304	0	0	0
T44	43701	4	0	0
T48	0	12	0	0
T54	408991	0	0	0
T55	967095	0	0	0
T66	55328	0	0	0
T67	126612	0	0	0
T68	0	4	0	0
T69	59561	0	0	0
T96	0	37	0	0
T150	0	5	0	0
T153	204633	0	0	0
T154	83156	0	0	0
T157	0	16	0	0
T163	0	21	0	0
T191	0	4	0	0
T225	0	4	0	0
T289	0	24	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1405	0	0
T68	489061	3	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T83	35049	0	0	0
T96	0	21	0	0
T99	134836	0	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T120	102788	0	0	0
T121	42398	0	0	0
T145	0	16	0	0
T157	0	28	0	0
T163	0	11	0	0
T180	0	17	0	0
T209	0	13	0	0
T289	0	24	0	0
T290	0	5	0	0
T291	0	7	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	6188	0	0
T8	243116	0	0	0
T17	54574	74	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T27	0	91	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T32	250605	0	0	0
T33	355857	0	0	0
T48	0	5	0	0
T62	213254	0	0	0
T63	102881	0	0	0
T68	0	166	0	0
T70	0	60	0	0
T74	0	40	0	0
T124	0	74	0	0
T163	0	17	0	0
T293	0	97	0	0
T294	0	49	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	7930	0	0
T48	287302	60	0	0
T68	489061	113	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	146	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T150	0	80	0	0
T157	0	156	0	0
T163	0	152	0	0
T215	0	47	0	0
T295	0	76	0	0
T296	0	70	0	0
T297	0	36	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	5528	0	0
T48	287302	54	0	0
T68	489061	106	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	146	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T150	0	93	0	0
T157	0	138	0	0
T163	0	105	0	0
T215	0	33	0	0
T295	0	77	0	0
T296	0	60	0	0
T297	0	41	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	5529	0	0
T48	287302	40	0	0
T68	489061	62	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	140	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T150	0	73	0	0
T157	0	147	0	0
T163	0	164	0	0
T215	0	47	0	0
T295	0	70	0	0
T296	0	67	0	0
T297	0	54	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1661	0	0
T48	287302	4	0	0
T68	489061	3	0	0
T70	121094	0	0	0
T71	914158	0	0	0
T72	59472	0	0	0
T79	78027	0	0	0
T83	35049	0	0	0
T96	0	26	0	0
T117	63278	0	0	0
T118	240440	0	0	0
T119	204463	0	0	0
T145	0	36	0	0
T157	0	32	0	0
T163	0	22	0	0
T209	0	9	0	0
T289	0	25	0	0
T290	0	2	0	0
T291	0	5	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1598	0	0
T10	251302	11	0	0
T11	143960	0	0	0
T12	220146	0	0	0
T13	65521	0	0	0
T26	202564	0	0	0
T36	0	3	0	0
T48	0	6	0	0
T50	338990	0	0	0
T57	261406	0	0	0
T58	51051	0	0	0
T59	833330	0	0	0
T67	0	10	0	0
T68	0	3	0	0
T80	110961	0	0	0
T95	0	13	0	0
T96	0	37	0	0
T157	0	12	0	0
T163	0	23	0	0
T298	0	13	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1724	0	0
T3	114183	10	0	0
T7	262710	0	0	0
T15	451015	0	0	0
T16	284345	0	0	0
T17	54574	0	0	0
T18	216382	0	0	0
T19	65032	0	0	0
T26	0	10	0	0
T30	123265	0	0	0
T31	238550	0	0	0
T48	0	5	0	0
T62	213254	0	0	0
T67	0	11	0	0
T68	0	2	0	0
T96	0	30	0	0
T124	0	1	0	0
T157	0	11	0	0
T163	0	7	0	0
T298	0	11	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1658	0	0
T1	188480	0	0	0
T2	148077	0	0	0
T3	114183	1	0	0
T4	200805	3	0	0
T5	209848	0	0	0
T6	294178	0	0	0
T7	262710	0	0	0
T10	0	2	0	0
T14	212393	0	0	0
T15	451015	0	0	0
T16	284345	0	0	0
T26	0	9	0	0
T36	0	5	0	0
T48	0	4	0	0
T67	0	9	0	0
T68	0	2	0	0
T124	0	4	0	0
T163	0	12	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248619610	1602	0	0
T10	251302	13	0	0
T11	143960	0	0	0
T12	220146	0	0	0
T13	65521	0	0	0
T26	202564	4	0	0
T50	338990	0	0	0
T57	261406	0	0	0
T58	51051	0	0	0
T59	833330	0	0	0
T67	0	5	0	0
T80	110961	0	0	0
T95	0	10	0	0
T96	0	16	0	0
T157	0	9	0	0
T163	0	23	0	0
T289	0	31	0	0
T298	0	7	0	0
T299	0	1	0	0