Unified Coverage Report :: Module :: sysrst_ctrl

Module : sysrst_ctrl_autoblock

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_autoblock	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_sysrst_ctrl_autoblock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.43	96.00	100.00		100.00	96.15	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sysrst_ctrl_detect	98.13	95.65	100.00		100.00	95.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_autoblock

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
50	1	1
51	1	1
53	1	1
55	1	1

Cond Coverage for Module : sysrst_ctrl_autoblock

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q) ? aon_auto_block_out_ctl_i.key0_out_value.q : key0_int_i)
             -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T50,T51

 LINE       51
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q)
                 -------1-------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T33,T9
1	0	Covered	T9,T51,T52
1	1	Covered	T33,T50,T51

 LINE       53
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q) ? aon_auto_block_out_ctl_i.key1_out_value.q : key1_int_i)
             -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T51,T55,T42

 LINE       53
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q)
                 -------1-------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T33,T50
1	0	Covered	T33,T9,T50
1	1	Covered	T51,T55,T42

 LINE       55
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q) ? aon_auto_block_out_ctl_i.key2_out_value.q : key2_int_i)
             -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T51,T52,T55

 LINE       55
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q)
                 -------1-------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T33,T9
1	0	Covered	T33,T9,T50
1	1	Covered	T51,T52,T55

Branch Coverage for Module : sysrst_ctrl_autoblock

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	51	2	2	100.00
TERNARY	53	2	2	100.00
TERNARY	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	51	((aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q)) ?

Branches:

-1-	Status	Tests
1	Covered	T33,T50,T51
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	53	((aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q)) ?

Branches:

-1-	Status	Tests
1	Covered	T51,T55,T42
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	55	((aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q)) ?

Branches:

-1-	Status	Tests
1	Covered	T51,T52,T55
0	Covered	T4,T5,T6