SYSRST_CTRL Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.460s	2.110ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.240s	2.462ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	7.010s	2.414ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	3.660s	2.357ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.690s	6.035ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.140s	2.035ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.731m	29.627ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	13.640s	3.329ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	7.350s	2.109ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.140s	2.035ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.640s	3.329ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.333m	190.533ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	9.286m	205.277ms	91	100	91.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	7.596m	336.872ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	3.554m	695.168ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.720s	2.512ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.840s	2.207ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	37.042m	826.722ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	8.110s	2.610ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	51.870s	1.249s	45	50	90.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	23.830s	39.267ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	15.099m	756.465ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	6.200s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.260s	2.012ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.970s	2.097ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.970s	2.097ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.690s	6.035ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.140s	2.035ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.640s	3.329ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	23.830s	8.421ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.690s	6.035ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.140s	2.035ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.640s	3.329ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	23.830s	8.421ms	20	20	100.00
V2		TOTAL			677	692	97.83
V2S	tl_intg_err	sysrst_ctrl_sec_cm	58.210s	22.014ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.961m	42.449ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.961m	42.449ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	5.913m	1.427s	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			912	932	97.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.64	98.79	96.78	100.00	96.15	98.26	99.52	94.00

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 6 failures:

Test sysrst_ctrl_ultra_low_pwr has 5 failures.

12.sysrst_ctrl_ultra_low_pwr.12918472592424388417560483666696661753381587920393829577237176569109260971020
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3112562081 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 3225062081 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 6015062081 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 6029798092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.sysrst_ctrl_ultra_low_pwr.40423633354842385334989967364626235376534353302254793287898874902586392382331
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3196534877 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 3799034877 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3799034877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test sysrst_ctrl_stress_all has 1 failures.

17.sysrst_ctrl_stress_all.45293419611917089742020026352220955404544553922752870055702175901600672619377
Line 567, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 755375444069 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 755507944069 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 756432944069 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 756464546667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 5 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 5 failures.

21.sysrst_ctrl_combo_detect_with_pre_cond.113846121571138714407698977701170842339235204255266326222896295994391264777722
Line 571, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 16084696620 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 16084696620 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16084696620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.sysrst_ctrl_combo_detect_with_pre_cond.82535142956313564572143025709998588075857864385351248162904877500692729247340
Line 597, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 48530195827 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 48530195827 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 48530195827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 3 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 3 failures.

15.sysrst_ctrl_combo_detect_with_pre_cond.37843915920184647833170137666044927335922981957673540107609390362134509492301
Line 625, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 60006231344 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 60046231344 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 60066231344 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 70228487404 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x19
  UVM_INFO @ 70228592668 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xf

65.sysrst_ctrl_combo_detect_with_pre_cond.92639872036534036101646021087858250250158257119519991254197272632323942582800
Line 595, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 64518199903 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 64518199903 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 64518199903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:121) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

1.sysrst_ctrl_stress_all_with_rand_reset.100374252534164073230189285656730154051778706300736595523180564812316403394903
Line 666, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 60592956525 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:121) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 60615113241 ps: (cip_base_vseq.sv:763) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 6/10
  UVM_INFO @ 60615958262 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 60617458262 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 7/10

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

6.sysrst_ctrl_stress_all_with_rand_reset.11829386897701194311247434679630643725439759697041114001789330763802624297233
Line 629, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 37468060012 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 37492686655 ps: (cip_base_vseq.sv:763) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 5/5
  UVM_INFO @ 37493556110 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 37504147902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

26.sysrst_ctrl_stress_all_with_rand_reset.52521494011534859182330115082869452691926485530857663269222128312192107026267
Line 562, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4178377240 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 4431626227 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_edge_detect_vseq
  UVM_INFO @ 6428284907 ps: (sysrst_ctrl_edge_detect_vseq.sv:141) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Starting the body from edge_detect_vseq
  UVM_INFO @ 6468195725 ps: (sysrst_ctrl_edge_detect_vseq.sv:56) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] L2H detected for AcPresentIdx
  UVM_INFO @ 6468195725 ps: (sysrst_ctrl_edge_detect_vseq.sv:56) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] L2H detected for Key0Idx

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.sysrst_ctrl_stress_all_with_rand_reset.54209964261395570405186151689480631174853746911249936365047955146086870820047
    Line 652, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 40144360240 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 40144360240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

47.sysrst_ctrl_stress_all_with_rand_reset.16890398710723430806113908674245102595475308570736305964352710460910009387947
Line 617, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22176130391 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 22207018238 ps: (cip_base_vseq.sv:763) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 6/10
  UVM_INFO @ 22208169843 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 22210190043 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 7/10

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == *) Unexpected H2L transition of ec_rst_l_o has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

99.sysrst_ctrl_combo_detect_with_pre_cond.27639297949835826167609891117786732681870538716073360530690198236511931843308
Line 682, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 125684853656 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
  UVM_INFO @ 125704853656 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :2
  UVM_INFO @ 125704853656 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :3
  UVM_INFO @ 125829853656 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 125849853656 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0