Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2018

1

T1

7

T5

1

T2

4

auto[1]

634

1

T1

6

T5

14

T2

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1946

1

T2

11

T27

10

T48

16

auto[1]

706

1

T1

13

T5

15

T27

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1943

1

T1

13

T5

14

T2

4

auto[1]

709

1

T5

1

T2

7

T27

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2022

1

T1

6

T5

14

T2

4

auto[1]

630

1

T1

7

T5

1

T2

7

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2409

1

T1

13

T5

15

T2

11

auto[1]

243

1

T27

3

T12

5

T271

22

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2473

1

T1

13

T5

15

T2

11

auto[1]

179

1

T12

6

T31

3

T131

10

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2434

1

T1

13

T5

15

T2

11

auto[1]

218

1

T27

2

T47

1

T131

10

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2431

1

T1

13

T5

15

T2

11

auto[1]

221

1

T48

4

T12

8

T31

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2447

1

T1

13

T5

15

T2

11

auto[1]

205

1

T27

1

T48

4

T12

6

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1930

1

T1

13

T5

14

T2

3

auto[1]

722

1

T5

1

T2

8

T27

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1057

1

T1

13

T5

14

T2

11

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

114

1

T12

5

T271

6

T216

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T31

1

T131

4

T33

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T27

1

T352

3

T353

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T12

8

T31

2

T103

20

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T216

1

T288

1

T354

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

32

1

T48

4

T104

6

T351

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T216

1

T355

7

T356

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T131

6

T33

12

T288

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T27

2

T349

1

T352

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

21

1

T355

6

T349

3

T357

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T355

5

T95

6

T177

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

7

1

T282

1

T358

2

T359

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T355

6

T360

1

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T356

3

T361

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

29

1

T31

3

T131

4

T288

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T151

5

T362

10

T351

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

10

1

T12

6

T363

1

T364

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

31

1

T33

1

T104

7

T365

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T282

1

T263

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T151

9

T358

2

T362

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T349

2

T366

6

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T367

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

84

1

T33

6

T151

9

T276

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

133

1

T130

9

T135

11

T131

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

59

1

T35

7

T129

5

T33

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T105

1

T355

5

T362

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

66

1

T130

5

T153

7

T251

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

87

1

T12

5

T135

2

T33

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T2

4

T131

7

T189

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

146

1

T12

6

T35

9

T103

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43

1

T48

4

T31

5

T35

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

88

1

T2

4

T7

6

T52

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T7

4

T130

2

T88

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

90

1

T27

1

T129

6

T314

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T2

3

T32

3

T216

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

45

1

T88

4

T39

2

T344

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T106

2

T368

1

T369

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

169

1

T31

1

T216

4

T45

24

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

96

1

T1

6

T5

14

T157

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

39

1

T27

2

T271

3

T34

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T34

2

T282

1

T370

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

73

1

T1

7

T35

7

T45

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T7

5

T105

1

T290

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T52

1

T39

2

T370

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T32

2

T371

1

T280

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T7

6

T216

1

T344

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T131

4

T157

2

T256

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T34

2

T153

5

T278

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T12

8

T278

2

T348

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

9

1

T37

3

T109

2

T121

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T135

1

T33

7

T105

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T129

2

T37

2

T370

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T346

1

T278

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded